From nobody Sun Feb 8 18:36:54 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0A9C21DB951 for ; Thu, 27 Feb 2025 18:45:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740681907; cv=none; b=hqS5HC9ZB0/tisMLxIpzQPPsLH/9aWq9x/6hd6VzwQF30wYy+F7ic+/lFtgXF2hcoCUp6Uw3m2oCHKUJDX1H5RBHVmX8hth+t9VhYjjJEXtX/ls4/Mz7Q1IGV0gyYXUyfJgq2X1BNi1Q/rd6oHpUrJU61ABuMXy5mL/8T1HY9o4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740681907; c=relaxed/simple; bh=AmRvvFfOyTl10D2JcoNSvocA7vsRifO+isIesvxtbaU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=f5OtlpsVUGAcpgB90lXCteynm+YGhQmaQgdykhWrTuJ7WboDqX8l41uq8UPu62hotRbISNIWbypT182N6ucI4weWjNio2fJR9Hg4hgXJmEpoiyeNR4YgS5XC35X3HcS2ax0OyzZ5KltvvzHr+SVpeAJzMsjHJUUnE4HNygF/JUc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=C8E6iiwV; arc=none smtp.client-ip=198.175.65.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="C8E6iiwV" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1740681906; x=1772217906; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=AmRvvFfOyTl10D2JcoNSvocA7vsRifO+isIesvxtbaU=; b=C8E6iiwV7YdYNU0orUmlyR5chPiEqjNjGbvLcaBSYkrPoPiLle4ETmOI xt+3+eJOWVBId9FiFxuxl7POZWs1dXqRoZz2ocTuOjD4xkz/vsn8NvhBp nhQgyuQolP+frrZ+DH95x7Dd0w0JrGpO3mSyxgNCuAr9sO4BliXE0pVKI gTAI2QdxVVsxmUNQSdPx628T3yhqKAFfufM2fqMXCM4jp0HOrT9rdKF1y rLbCH+Es6bLMG8OXKpkSovA8b/Kj/++ODuLQNIaLrYw5roWnYkUplRd5m 4ZUQ9qYF3k3SMLhFSHm/9MJ4Kk+VkhqCh66JI2sNKI98gVK9F2iVSNNCV Q==; X-CSE-ConnectionGUID: R6q+X4A5SIysHgfhPdQh8g== X-CSE-MsgGUID: LqJuuvxhTceXZ1cuxuehuA== X-IronPort-AV: E=McAfee;i="6700,10204,11358"; a="41720858" X-IronPort-AV: E=Sophos;i="6.13,320,1732608000"; d="scan'208";a="41720858" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Feb 2025 10:45:06 -0800 X-CSE-ConnectionGUID: AEn5FupTRuqlqcQFdyZ85Q== X-CSE-MsgGUID: u6LORMWMS7C/ivfGXo2pgA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,320,1732608000"; d="scan'208";a="117767371" Received: from cbae1-mobl.amr.corp.intel.com (HELO cbae1-mobl.intel.com) ([10.246.154.132]) by fmviesa009.fm.intel.com with ESMTP; 27 Feb 2025 10:45:04 -0800 From: "Chang S. Bae" To: linux-kernel@vger.kernel.org Cc: x86@kernel.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, chang.seok.bae@intel.com Subject: [PATCH RFC v1 01/11] x86/fpu/xstate: Simplify print_xstate_features() Date: Thu, 27 Feb 2025 10:44:46 -0800 Message-ID: <20250227184502.10288-2-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250227184502.10288-1-chang.seok.bae@intel.com> References: <20250227184502.10288-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" print_xstate_features() currently invokes print_xstate_feature() multiple times on separate lines, which can be simplified in a loop. print_xstate_feature() already checks the feature's enabled status and is only called within print_xstate_features(). Inline print_xstate_feature() and iterate over features in a loop to streamline the enabling message. No functional changes. Signed-off-by: Chang S. Bae Reviewed-by: Dave Hansen --- I find it difficult to justify using separate lines for printing when they can be efficiently grouped under a simple for-loop. While this cleanup isn't directly related to APX, it felt like a necessary improvement, especially when new xstates are introduced. --- arch/x86/kernel/fpu/xstate.c | 30 +++++++++--------------------- 1 file changed, 9 insertions(+), 21 deletions(-) diff --git a/arch/x86/kernel/fpu/xstate.c b/arch/x86/kernel/fpu/xstate.c index 27417b685c1d..6a41d1610d8b 100644 --- a/arch/x86/kernel/fpu/xstate.c +++ b/arch/x86/kernel/fpu/xstate.c @@ -259,32 +259,20 @@ static void __init setup_xstate_cache(void) } } =20 -static void __init print_xstate_feature(u64 xstate_mask) -{ - const char *feature_name; - - if (cpu_has_xfeatures(xstate_mask, &feature_name)) - pr_info("x86/fpu: Supporting XSAVE feature 0x%03Lx: '%s'\n", xstate_mask= , feature_name); -} - /* * Print out all the supported xstate features: */ static void __init print_xstate_features(void) { - print_xstate_feature(XFEATURE_MASK_FP); - print_xstate_feature(XFEATURE_MASK_SSE); - print_xstate_feature(XFEATURE_MASK_YMM); - print_xstate_feature(XFEATURE_MASK_BNDREGS); - print_xstate_feature(XFEATURE_MASK_BNDCSR); - print_xstate_feature(XFEATURE_MASK_OPMASK); - print_xstate_feature(XFEATURE_MASK_ZMM_Hi256); - print_xstate_feature(XFEATURE_MASK_Hi16_ZMM); - print_xstate_feature(XFEATURE_MASK_PKRU); - print_xstate_feature(XFEATURE_MASK_PASID); - print_xstate_feature(XFEATURE_MASK_CET_USER); - print_xstate_feature(XFEATURE_MASK_XTILE_CFG); - print_xstate_feature(XFEATURE_MASK_XTILE_DATA); + int i; + + for (i =3D 0; i < XFEATURE_MAX; i++) { + u64 mask =3D BIT_ULL(i); + const char *name; + + if (cpu_has_xfeatures(mask, &name)) + pr_info("x86/fpu: Supporting XSAVE feature 0x%03Lx: '%s'\n", mask, name= ); + } } =20 /* --=20 2.45.2 From nobody Sun Feb 8 18:36:54 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 37F0126B966 for ; Thu, 27 Feb 2025 18:45:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740681908; cv=none; b=mgFJYzyjfRoPWIv06cQxkU3UF2cIhbWZxBLUr7kUn0LvRnewbIPv5o3EhsIA6PcQhA/9Deui2PUGc9to0Zx1rfbIj467+b4W7+vBvZlM3au6Sl4s3/ChWlf3rau2fpLbKWVIJGckpiL6rLs8MNIasAZAwoa+aMHg9wrBJys/3Qw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740681908; c=relaxed/simple; bh=xeZi8+e1HOiLrt4irUuPbX2XdqRh/jCjNzv6den6hjA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=SFwm7LM9AnL08Pz291p3Ykn/IJgdZlsES+cVYPV8bfUXLjM/Tq929ecBu2Vi+Ft4SXxQO9PWd8/Gl2N3BpTCyUF3QSywzcFBFVv4TmtsaxSmRd8ZLX6ofXOjfLZSkUSeXZWjyrZAmFC+IyfdZwpVdyON8O9/CiEfWKorxjHLfog= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=DCul949R; arc=none smtp.client-ip=198.175.65.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="DCul949R" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1740681907; x=1772217907; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=xeZi8+e1HOiLrt4irUuPbX2XdqRh/jCjNzv6den6hjA=; b=DCul949RLoe+T5Gbw7oU834iAFlBzT4ikYAhVs7bGze9Ms9Cnj8tj6+8 McjV1g7oUdWQ+sMRfXvwq27hjzBVhU3AvtZNY97KYuNhbZwOMILINITCp 2FYLb4UvslOTcrMngyhmysT110nAr5YY8lFfSW9Y+5q8La4KJPrHlrXuf TkePphL+O0b1S3NQrUNwP/qdZ3E8T5miuY9wUAbXrZ0SW/xMTo8iy2rZb ATYAg7ORlJK+h120AwGOxtFc30Yvl68FlnG/3lv1f4QvyrB9ZrZVnJqBO pnBZ8uPw9xbAjCxGTTI6w1JrciRNrnfk3wjvcxJzTlpczHPiGGdAkdyWV Q==; X-CSE-ConnectionGUID: YkWUJzCJRx+2RDS8RRezKQ== X-CSE-MsgGUID: VtchJlpES0Ka+WE98gJR/Q== X-IronPort-AV: E=McAfee;i="6700,10204,11358"; a="41720863" X-IronPort-AV: E=Sophos;i="6.13,320,1732608000"; d="scan'208";a="41720863" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Feb 2025 10:45:06 -0800 X-CSE-ConnectionGUID: n9kNdMlYTwKoPL5QDHGP2Q== X-CSE-MsgGUID: 0i7MoiuMRySCfb+c/giU/w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,320,1732608000"; d="scan'208";a="117767380" Received: from cbae1-mobl.amr.corp.intel.com (HELO cbae1-mobl.intel.com) ([10.246.154.132]) by fmviesa009.fm.intel.com with ESMTP; 27 Feb 2025 10:45:06 -0800 From: "Chang S. Bae" To: linux-kernel@vger.kernel.org Cc: x86@kernel.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, chang.seok.bae@intel.com Subject: [PATCH RFC v1 02/11] x86/fpu/xstate: Introduce xstate order table and accessor macro Date: Thu, 27 Feb 2025 10:44:47 -0800 Message-ID: <20250227184502.10288-3-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250227184502.10288-1-chang.seok.bae@intel.com> References: <20250227184502.10288-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The kernel has largely assumed that higher xstate component numbers correspond to later offsets in the buffer. However, this assumption does not hold for the non-compacted format, where a newer state component may have a lower offset. When iterating over xstate components in offset order, using the feature number as an index may be misleading. At the same time, the CPU exposes each component=E2=80=99s size and offset based on its feature number, makin= g it a key for state information. To provide flexibility in handling xstate ordering, add a mapping table: feature order -> feature number. This new array stores feature numbers in offset order, accompanied by an accessor macro. The macro enables sequential traversal of xstate components based on their actual buffer positions, given a feature bitmask. This will be particularly useful for computing customized non-compacted format sizes and sequentially accessing xstate offsets over non-compacted buffers. Suggested-by: Dave Hansen Signed-off-by: Chang S. Bae --- This lays the groundwork for handling APX, which has feature number 19 but appears immediately after FEATURE_YMM, occupying the space previously reserved for the now-deprecated MPX state. --- arch/x86/kernel/fpu/xstate.c | 37 ++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/x86/kernel/fpu/xstate.c b/arch/x86/kernel/fpu/xstate.c index 6a41d1610d8b..cee9a1e454b7 100644 --- a/arch/x86/kernel/fpu/xstate.c +++ b/arch/x86/kernel/fpu/xstate.c @@ -91,6 +91,43 @@ static unsigned int xstate_flags[XFEATURE_MAX] __ro_afte= r_init; #define XSTATE_FLAG_SUPERVISOR BIT(0) #define XSTATE_FLAG_ALIGNED64 BIT(1) =20 +/* + * Ordering of xstate components in non-compacted format: The xfeature + * number does not necessarily indicate its position in the XSAVE buffer. + * This array defines the traversal order of xstate features, included in + * XFEATURE_MASK_USER_SUPPORTED. + */ +static const enum xfeature xfeature_noncompact_order[] =3D { + XFEATURE_FP, + XFEATURE_SSE, + XFEATURE_YMM, + XFEATURE_BNDREGS, + XFEATURE_BNDCSR, + XFEATURE_OPMASK, + XFEATURE_ZMM_Hi256, + XFEATURE_Hi16_ZMM, + XFEATURE_PKRU, + XFEATURE_XTILE_CFG, + XFEATURE_XTILE_DATA, +}; + +static inline unsigned int next_xfeature_order(unsigned int i, u64 mask) +{ + for (; i < ARRAY_SIZE(xfeature_noncompact_order); i++) { + if (mask & BIT_ULL(xfeature_noncompact_order[i])) + break; + } + + return i; +} + +/* Iterate xstate features in non-compacted order */ +#define for_each_extended_xfeature_in_order(i, mask) \ + for (i =3D XFEATURE_YMM; \ + i =3D next_xfeature_order(i, mask), \ + i < ARRAY_SIZE(xfeature_noncompact_order); \ + i++) + /* * Return whether the system supports a given xfeature. * --=20 2.45.2 From nobody Sun Feb 8 18:36:54 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C73C626B97F for ; Thu, 27 Feb 2025 18:45:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740681909; cv=none; b=glk/BLBAqJwKbMfKGJJPDeV4J52wyCjlUamZ7c8rpvJkK/pdEMgC2o5SACDo5nUk5yK0xIUZTJgSD+JONkT7hp5qhWrG5AvFHQGVYmDyGPAH+8zOlaUs/HodkIfoOzwPO68P+SuQ+8/lrJW8Ll/Pn72xmipLzGAd8c8vFxjaL+0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740681909; c=relaxed/simple; bh=M67rS9H7Qso6AOXIDWb/hoSSdA5CWVIzCPpTU22f688=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=rJuxSa2rsJCD7xsRbM0zrPq4BUtbvu826kVQxcgtXv0tWHSoTt2kGteoYxHtwLhTeBT3QaIss84McBzxFGU6Oc8InGutXvH/DadlqLZ/Z+t7eLEMuIKEZ10fEzI1qQtP/WRZTSV4mMzHglvjSHtL+vZRxuVfg6+DSxCQsSRsVO8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=RJKdUbIi; arc=none smtp.client-ip=198.175.65.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="RJKdUbIi" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1740681908; x=1772217908; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=M67rS9H7Qso6AOXIDWb/hoSSdA5CWVIzCPpTU22f688=; b=RJKdUbIicghEeG0XsDH5vn9a8CSkWW+OkfwLdxZLT/3zPCQhjsfAux7U JPh/Qc9h6kAW6vc37Hwy5D5KL+GwVcDbBOdmxBLevQfFkRjeLZRgL1DHR +/YOkOaPL41Ds2Ni4b1eVAX/Mo0A9NiZ0U7lNw0bi8Q4IyyS/IAI1PwZ2 x++PoMzI2vB+Voo6cG3lFpF8tsRRz1z3by8NvO57zNaMlQLqtA/vMSjUC A3tbd9W/mubo/fig3XxbzMzdQ1ysymYXQ4HxXcwsUyzxFXMLHcIOiGwip 3ICEbRlhI3JACNwEbLkjKnjAkMrQwQcUA7IOOP820qdxaJYpPD8PfiQgt A==; X-CSE-ConnectionGUID: a7HdJwAwSimSi8Mm2ELOtw== X-CSE-MsgGUID: WZD2wjSoRemUfUT6C+9keQ== X-IronPort-AV: E=McAfee;i="6700,10204,11358"; a="41720870" X-IronPort-AV: E=Sophos;i="6.13,320,1732608000"; d="scan'208";a="41720870" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Feb 2025 10:45:07 -0800 X-CSE-ConnectionGUID: fUS3uTsuTD2ONtuDIDYXhw== X-CSE-MsgGUID: 3cl642s2Rh6WtyVGt7TtYg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,320,1732608000"; d="scan'208";a="117767387" Received: from cbae1-mobl.amr.corp.intel.com (HELO cbae1-mobl.intel.com) ([10.246.154.132]) by fmviesa009.fm.intel.com with ESMTP; 27 Feb 2025 10:45:07 -0800 From: "Chang S. Bae" To: linux-kernel@vger.kernel.org Cc: x86@kernel.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, chang.seok.bae@intel.com Subject: [PATCH RFC v1 03/11] x86/fpu/xstate: Remove xstate offset check Date: Thu, 27 Feb 2025 10:44:48 -0800 Message-ID: <20250227184502.10288-4-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250227184502.10288-1-chang.seok.bae@intel.com> References: <20250227184502.10288-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Traditionally, new xstate components have been assigned sequentially, aligning feature numbers with their offsets in the XSAVE buffer. However, this ordering is not architecturally mandated in the non-compacted format, where a component's offset may not correspond to its feature number. The kernel caches CPUID-reported xstate component details, including size and offset in the non-compacted format. As part of this process, a sanity check is also conducted to ensure alignment between feature numbers and offsets. This check was likely intended as a general guideline rather than a strict requirement. As part of supporting out-of-order offsets, remove this unnecessary validation. Signed-off-by: Chang S. Bae --- arch/x86/kernel/fpu/xstate.c | 13 ------------- 1 file changed, 13 deletions(-) diff --git a/arch/x86/kernel/fpu/xstate.c b/arch/x86/kernel/fpu/xstate.c index cee9a1e454b7..c6f825bb744b 100644 --- a/arch/x86/kernel/fpu/xstate.c +++ b/arch/x86/kernel/fpu/xstate.c @@ -253,9 +253,6 @@ static bool xfeature_enabled(enum xfeature xfeature) static void __init setup_xstate_cache(void) { u32 eax, ebx, ecx, edx, i; - /* start at the beginning of the "extended state" */ - unsigned int last_good_offset =3D offsetof(struct xregs_state, - extended_state_area); /* * The FP xstates and SSE xstates are legacy states. They are always * in the fixed offsets in the xsave area in either compacted form @@ -283,16 +280,6 @@ static void __init setup_xstate_cache(void) continue; =20 xstate_offsets[i] =3D ebx; - - /* - * In our xstate size checks, we assume that the highest-numbered - * xstate feature has the highest offset in the buffer. Ensure - * it does. - */ - WARN_ONCE(last_good_offset > xstate_offsets[i], - "x86/fpu: misordered xstate at %d\n", last_good_offset); - - last_good_offset =3D xstate_offsets[i]; } } =20 --=20 2.45.2 From nobody Sun Feb 8 18:36:54 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D045426D5A9 for ; Thu, 27 Feb 2025 18:45:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740681911; cv=none; b=C/B2GVvJ4NYdRABpevX9mBRFU75K/DUFFzJcC+QhX7WBa4wsTOt/+2yyYE6lm7RX6j9AR/vnormSi+uugOV7NR0bGTZLfY53YQPyxpUYYDL9D5xsUpsNtyx/98MrcPJhepYzOMYY7xrwnDsFhrIxolshvgZasHE0O6rBDbgHxuI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740681911; c=relaxed/simple; bh=j+BCRed+9G0JDy4ms61fhOSISvI8yxPsmuGYZ95UX3Q=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ZMgHugPNOhLAK7FGtknmzS1LHvubo8K1XR8C1FDP0KoKcwkHMJVDMDCMK2IPYQ1H56XDmD9/OJCFHlOMhToLC3iEaGgbsf37TDa3iEkKzdmG9sEU0vxhyYyqO0vWgKKHovPoPaZp513FUjhtw/Ulyy7BVYGPkdp3O87ZKDaI2T4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=N6qHBZRB; arc=none smtp.client-ip=198.175.65.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="N6qHBZRB" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1740681909; x=1772217909; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=j+BCRed+9G0JDy4ms61fhOSISvI8yxPsmuGYZ95UX3Q=; b=N6qHBZRBFh8k6IvIYdev74aU4kCcB9l2CoFv3swOSyR83xnzy0vvNI8D f0EAom5Lbgg5y+REz2ZGXS7Pq4X1UZDZxIWR4XzT8RFp8rVv0mCu2I4za 5lEG0ZjFMdmxg2+fRmD1fFJTug1QWAo25aXoGTox4fFHR3sCpGhTmeELk I3axDKpXtX0+InWLGUhcQgUGZeK5RBz0Q7co9ieVMN4dKvt7ibWuxAEjs yiMYZy9ODJQWKY7F0C5Cn9hQuT6zNa6U6tQGzDd18mF3kE58jAAJDzE77 8Gtw0l26yd2klPijSLiN7y8ipI+vVz1UhHvzGZ6EymKrTPGTkxxwu9bwg A==; X-CSE-ConnectionGUID: WbMJyKLiQXaSmdxXCgSuFw== X-CSE-MsgGUID: Gj7IxRXWS8WfTeieh3KIgA== X-IronPort-AV: E=McAfee;i="6700,10204,11358"; a="41720876" X-IronPort-AV: E=Sophos;i="6.13,320,1732608000"; d="scan'208";a="41720876" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Feb 2025 10:45:08 -0800 X-CSE-ConnectionGUID: 5M9e5LwFR1uJZ4dkZtgwmA== X-CSE-MsgGUID: x4ujSbY5SMqrFq6If0Ct0w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,320,1732608000"; d="scan'208";a="117767396" Received: from cbae1-mobl.amr.corp.intel.com (HELO cbae1-mobl.intel.com) ([10.246.154.132]) by fmviesa009.fm.intel.com with ESMTP; 27 Feb 2025 10:45:08 -0800 From: "Chang S. Bae" To: linux-kernel@vger.kernel.org Cc: x86@kernel.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, chang.seok.bae@intel.com Subject: [PATCH RFC v1 04/11] x86/fpu/xstate: Adjust XSAVE buffer size calculation Date: Thu, 27 Feb 2025 10:44:49 -0800 Message-ID: <20250227184502.10288-5-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250227184502.10288-1-chang.seok.bae@intel.com> References: <20250227184502.10288-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The current xstate size calculation assumes that the highest-numbered xstate feature has the highest offset in the buffer, determining the size based on the topmost bit in the feature mask. However, this assumption is not architecturally guaranteed -- higher-numbered features may have lower offsets. With the introduction of the xfeature order table and its helper macro, xstate components can now be traversed in their positional order. Update the non-compacted format handling to iterate through the table to determine the last-positioned feature. Then, set the offset accordingly. Since size calculation primarily occurs during initialization or in non-critical paths, looping to find the last feature is not expected to have a meaningful performance impact. Signed-off-by: Chang S. Bae --- arch/x86/kernel/fpu/xstate.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/fpu/xstate.c b/arch/x86/kernel/fpu/xstate.c index c6f825bb744b..06d2be602ea9 100644 --- a/arch/x86/kernel/fpu/xstate.c +++ b/arch/x86/kernel/fpu/xstate.c @@ -576,13 +576,20 @@ static bool __init check_xstate_against_struct(int nr) static unsigned int xstate_calculate_size(u64 xfeatures, bool compacted) { unsigned int topmost =3D fls64(xfeatures) - 1; - unsigned int offset =3D xstate_offsets[topmost]; + unsigned int offset, i; =20 if (topmost <=3D XFEATURE_SSE) return sizeof(struct xregs_state); =20 - if (compacted) + if (compacted) { offset =3D xfeature_get_offset(xfeatures, topmost); + } else { + /* Walk through the xfeature order to pick the last */ + for_each_extended_xfeature_in_order(i, xfeatures) + topmost =3D xfeature_noncompact_order[i]; + offset =3D xstate_offsets[topmost]; + } + return offset + xstate_sizes[topmost]; } =20 --=20 2.45.2 From nobody Sun Feb 8 18:36:54 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 64FF126D5B7 for ; Thu, 27 Feb 2025 18:45:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740681911; cv=none; b=XESErk64ak9nQiKMA7dFkB3+MGLz5A9wVD2UhA8lkRmCzJ+j5qouMvUcaHk4md76iWGIjw/dVHWrsSh62HmeKOEg1YMvOrN17H5hwivTYvDQcUZ7d0hiS1TijgkBuDuNjeaSMlMLrCT+irFImvBCm75aGmHHoekp/aJ+KgrZhVE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740681911; c=relaxed/simple; bh=v3kIX0ZxQDiQq9ytxtP1qxcASSi89ty5zyeqjVl/ciA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=mwm2IEaQWMsxAJruLTyaOvRjRh37sRL2UQ6qrn4pxmSujD94aILa+0QEssFmSGp12rotz29/RZOrEPb2aHOG3uqDe3TdA9o/ka89FGciyzc5I8L6fxVO+eagueorMgJj8AyU5RWR+v13aZtHQqXX/vt7DCZ7mR127sKAVIiFATE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=VKqclqxO; arc=none smtp.client-ip=198.175.65.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="VKqclqxO" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1740681910; x=1772217910; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=v3kIX0ZxQDiQq9ytxtP1qxcASSi89ty5zyeqjVl/ciA=; b=VKqclqxO07gbpZ1Q001VsqnSvaPRMAx+2xhGD4AqV6mdFD7BVRgebrNC GEMqgnAygRd3OKEuAwJoXofCNW+7lJWON6GfnHKyMpK6SAdHXncdg336o p3Nf/HbNm1jtV24z1NYh8twAKTp6lc+4tdnIyT2yHCuJLq5IQROebufG+ 76/aTixDQqc5klFZTmQPhR/g/irf9WucK53S85FrZNKQMR+YVqVFqRJ21 N3PVdn3YpZZ9InAmCYR9qnu1O6QCeovWdvJjlC80pBiLBrrY69jX4VNtc ls/xVPhkedpNHRrdMsUY2q1gs0JVvsHEYNBPUIQ+D6RnHJPvleISGxhAl w==; X-CSE-ConnectionGUID: yTqy82NASwSEKrPvz/w7jw== X-CSE-MsgGUID: a8ogsUqiQ+iGQ6F7IshxWQ== X-IronPort-AV: E=McAfee;i="6700,10204,11358"; a="41720884" X-IronPort-AV: E=Sophos;i="6.13,320,1732608000"; d="scan'208";a="41720884" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Feb 2025 10:45:09 -0800 X-CSE-ConnectionGUID: WBVJT+7vRMKCuQvDS28alw== X-CSE-MsgGUID: 7+yFHzS/RDuvfapBDp6ajw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,320,1732608000"; d="scan'208";a="117767403" Received: from cbae1-mobl.amr.corp.intel.com (HELO cbae1-mobl.intel.com) ([10.246.154.132]) by fmviesa009.fm.intel.com with ESMTP; 27 Feb 2025 10:45:08 -0800 From: "Chang S. Bae" To: linux-kernel@vger.kernel.org Cc: x86@kernel.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, chang.seok.bae@intel.com Subject: [PATCH RFC v1 05/11] x86/fpu/xstate: Adjust xstate copying logic for user ABI Date: Thu, 27 Feb 2025 10:44:50 -0800 Message-ID: <20250227184502.10288-6-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250227184502.10288-1-chang.seok.bae@intel.com> References: <20250227184502.10288-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable =3D=3D Background =3D=3D As feature positions in the userspace XSAVE buffer do not always align with their feature numbers, the XSAVE format conversion needs to be reconsidered to align with the revised xstate size calculation logic. * For signal handling, XSAVE and XRSTOR are used directly to save and restore extended registers. * For ptrace, KVM, and signal returns (for 32-bit frame), the kernel copies data between its internal buffer and the userspace XSAVE buffer. If memcpy() were used for these cases, existing offset helpers =E2=80=94 = such as __raw_xsave_addr() or xstate_offsets[] =E2=80=94 would be sufficient to handle the format conversion. =3D=3D Problem =3D=3D When copying data from the compacted in-kernel buffer to the non-compacted userspace buffer, the function follows the user_regset_get2_fn() prototype. This means it utilizes struct membuf helpers for the destination buffer. As defined in regset.h, these helpers update the memory pointer during the copy process, enforcing sequential writes within the loop. Since xstate components are processed sequentially, any component whose buffer position does not align with its feature number has an issue. =3D=3D Solution =3D=3D Replace for_each_extended_xfeature() with the newly introduced for_each_extended_xfeature_in_order(). This macro ensures xstate components are handled in the correct order based on their actual positions in the destination buffer, rather than their feature numbers. Signed-off-by: Chang S. Bae --- arch/x86/kernel/fpu/xstate.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/x86/kernel/fpu/xstate.c b/arch/x86/kernel/fpu/xstate.c index 06d2be602ea9..d04221d0fa0a 100644 --- a/arch/x86/kernel/fpu/xstate.c +++ b/arch/x86/kernel/fpu/xstate.c @@ -1102,10 +1102,9 @@ void __copy_xstate_to_uabi_buf(struct membuf to, str= uct fpstate *fpstate, const unsigned int off_mxcsr =3D offsetof(struct fxregs_state, mxcsr); struct xregs_state *xinit =3D &init_fpstate.regs.xsave; struct xregs_state *xsave =3D &fpstate->regs.xsave; + unsigned int zerofrom, i, xfeature; struct xstate_header header; - unsigned int zerofrom; u64 mask; - int i; =20 memset(&header, 0, sizeof(header)); header.xfeatures =3D xsave->header.xfeatures; @@ -1174,15 +1173,16 @@ void __copy_xstate_to_uabi_buf(struct membuf to, st= ruct fpstate *fpstate, */ mask =3D header.xfeatures; =20 - for_each_extended_xfeature(i, mask) { + for_each_extended_xfeature_in_order(i, mask) { + xfeature =3D xfeature_noncompact_order[i]; /* * If there was a feature or alignment gap, zero the space * in the destination buffer. */ - if (zerofrom < xstate_offsets[i]) - membuf_zero(&to, xstate_offsets[i] - zerofrom); + if (zerofrom < xstate_offsets[xfeature]) + membuf_zero(&to, xstate_offsets[xfeature] - zerofrom); =20 - if (i =3D=3D XFEATURE_PKRU) { + if (xfeature =3D=3D XFEATURE_PKRU) { struct pkru_state pkru =3D {0}; /* * PKRU is not necessarily up to date in the @@ -1192,14 +1192,14 @@ void __copy_xstate_to_uabi_buf(struct membuf to, st= ruct fpstate *fpstate, membuf_write(&to, &pkru, sizeof(pkru)); } else { membuf_write(&to, - __raw_xsave_addr(xsave, i), - xstate_sizes[i]); + __raw_xsave_addr(xsave, xfeature), + xstate_sizes[xfeature]); } /* * Keep track of the last copied state in the non-compacted * target buffer for gap zeroing. */ - zerofrom =3D xstate_offsets[i] + xstate_sizes[i]; + zerofrom =3D xstate_offsets[xfeature] + xstate_sizes[xfeature]; } =20 out: --=20 2.45.2 From nobody Sun Feb 8 18:36:54 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6CB9E26BD9C for ; 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a="41720890" X-IronPort-AV: E=Sophos;i="6.13,320,1732608000"; d="scan'208";a="41720890" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Feb 2025 10:45:10 -0800 X-CSE-ConnectionGUID: O1saL3dxRPShIsB4o2Eljw== X-CSE-MsgGUID: eBVRfu6mTf2Fswuj/H41Ug== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,320,1732608000"; d="scan'208";a="117767409" Received: from cbae1-mobl.amr.corp.intel.com (HELO cbae1-mobl.intel.com) ([10.246.154.132]) by fmviesa009.fm.intel.com with ESMTP; 27 Feb 2025 10:45:09 -0800 From: "Chang S. Bae" To: linux-kernel@vger.kernel.org Cc: x86@kernel.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, chang.seok.bae@intel.com Subject: [PATCH RFC v1 06/11] x86/fpu/mpx: Remove MPX xstate component support Date: Thu, 27 Feb 2025 10:44:51 -0800 Message-ID: <20250227184502.10288-7-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250227184502.10288-1-chang.seok.bae@intel.com> References: <20250227184502.10288-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" A new xstate component is set to occupy the position previously used by MPX in the non-compacted format, then creating a fundamental conflict between the two. Currently, xfeature_noncompact_order[] includes MPX, but the introduction of the new feature would cause a direct conflict there unless MPX is removed. Fortunately, MPX support has already been deprecated and effectively removed by commit: 45fc24e89b7c ("x86/mpx: remove MPX from arch/x86") Explicitly disable the deprecated feature to reserve a space for the new xstate. Signed-off-by: Chang S. Bae --- Several code references to this feature macro remain, primarily on the KVM side. While they are likely to become obsolete after this patch, their cleanup has been deferred at this review stage: This can be addressed in a follow-up patch or included as an optional part of APX enablement, I suppose. --- arch/x86/include/asm/fpu/xstate.h | 2 -- arch/x86/kernel/fpu/xstate.c | 8 -------- 2 files changed, 10 deletions(-) diff --git a/arch/x86/include/asm/fpu/xstate.h b/arch/x86/include/asm/fpu/x= state.h index 7f39fe7980c5..e87d36a31ab1 100644 --- a/arch/x86/include/asm/fpu/xstate.h +++ b/arch/x86/include/asm/fpu/xstate.h @@ -30,8 +30,6 @@ XFEATURE_MASK_ZMM_Hi256 | \ XFEATURE_MASK_Hi16_ZMM | \ XFEATURE_MASK_PKRU | \ - XFEATURE_MASK_BNDREGS | \ - XFEATURE_MASK_BNDCSR | \ XFEATURE_MASK_XTILE) =20 /* diff --git a/arch/x86/kernel/fpu/xstate.c b/arch/x86/kernel/fpu/xstate.c index d04221d0fa0a..16f45fff8811 100644 --- a/arch/x86/kernel/fpu/xstate.c +++ b/arch/x86/kernel/fpu/xstate.c @@ -69,8 +69,6 @@ static unsigned short xsave_cpuid_features[] __initdata = =3D { [XFEATURE_FP] =3D X86_FEATURE_FPU, [XFEATURE_SSE] =3D X86_FEATURE_XMM, [XFEATURE_YMM] =3D X86_FEATURE_AVX, - [XFEATURE_BNDREGS] =3D X86_FEATURE_MPX, - [XFEATURE_BNDCSR] =3D X86_FEATURE_MPX, [XFEATURE_OPMASK] =3D X86_FEATURE_AVX512F, [XFEATURE_ZMM_Hi256] =3D X86_FEATURE_AVX512F, [XFEATURE_Hi16_ZMM] =3D X86_FEATURE_AVX512F, @@ -101,8 +99,6 @@ static const enum xfeature xfeature_noncompact_order[] = =3D { XFEATURE_FP, XFEATURE_SSE, XFEATURE_YMM, - XFEATURE_BNDREGS, - XFEATURE_BNDCSR, XFEATURE_OPMASK, XFEATURE_ZMM_Hi256, XFEATURE_Hi16_ZMM, @@ -360,8 +356,6 @@ static __init void os_xrstor_booting(struct xregs_state= *xstate) XFEATURE_MASK_ZMM_Hi256 | \ XFEATURE_MASK_Hi16_ZMM | \ XFEATURE_MASK_PKRU | \ - XFEATURE_MASK_BNDREGS | \ - XFEATURE_MASK_BNDCSR | \ XFEATURE_MASK_PASID | \ XFEATURE_MASK_CET_USER | \ XFEATURE_MASK_XTILE) @@ -555,8 +549,6 @@ static bool __init check_xstate_against_struct(int nr) */ switch (nr) { case XFEATURE_YMM: return XCHECK_SZ(sz, nr, struct ymmh_struct); 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d="scan'208";a="117767420" Received: from cbae1-mobl.amr.corp.intel.com (HELO cbae1-mobl.intel.com) ([10.246.154.132]) by fmviesa009.fm.intel.com with ESMTP; 27 Feb 2025 10:45:10 -0800 From: "Chang S. Bae" To: linux-kernel@vger.kernel.org Cc: x86@kernel.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, chang.seok.bae@intel.com Subject: [PATCH RFC v1 07/11] x86/cpufeatures: Add X86_FEATURE_APX Date: Thu, 27 Feb 2025 10:44:52 -0800 Message-ID: <20250227184502.10288-8-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250227184502.10288-1-chang.seok.bae@intel.com> References: <20250227184502.10288-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Intel Advanced Performance Extensions (APX) introduce a new set of general-purpose registers, managed as an extended state component via the xstate management facility. Before enabling this new xstate, define a feature flag to clarify the dependency in xsave_cpuid_features[]. APX is enumerated under CPUID level 7 with EDX=3D1. Since this CPUID leaf is not yet allocated, place the flag in a scattered feature word. While this feature is intended only for userspace, exposing it via /proc/cpuinfo is unnecessary. Instead, the existing arch_prctl(2) mechanism with the ARCH_GET_XCOMP_SUPP option can be used to query the feature availability. Finally, clarify that APX depends on XSAVE. Signed-off-by: Chang S. Bae --- Allocating a new feature word for this bit seems excessive at this stage, given that no other imminent features are quite known. --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/cpuid-deps.c | 1 + arch/x86/kernel/cpu/scattered.c | 1 + 3 files changed, 3 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpuf= eatures.h index 508c0dad116b..4f96515af7c3 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -483,6 +483,7 @@ #define X86_FEATURE_AMD_FAST_CPPC (21*32 + 5) /* Fast CPPC */ #define X86_FEATURE_AMD_HETEROGENEOUS_CORES (21*32 + 6) /* Heterogeneous C= ore Topology */ #define X86_FEATURE_AMD_WORKLOAD_CLASS (21*32 + 7) /* Workload Classificat= ion */ +#define X86_FEATURE_APX (21*32 + 8) /* Advanced Performance Extensions */ =20 /* * BUG word(s) diff --git a/arch/x86/kernel/cpu/cpuid-deps.c b/arch/x86/kernel/cpu/cpuid-d= eps.c index df838e3bdbe0..44ab6baeec42 100644 --- a/arch/x86/kernel/cpu/cpuid-deps.c +++ b/arch/x86/kernel/cpu/cpuid-deps.c @@ -84,6 +84,7 @@ static const struct cpuid_dep cpuid_deps[] =3D { { X86_FEATURE_AMX_TILE, X86_FEATURE_XFD }, { X86_FEATURE_SHSTK, X86_FEATURE_XSAVES }, { X86_FEATURE_FRED, X86_FEATURE_LKGS }, + { X86_FEATURE_APX, X86_FEATURE_XSAVE }, {} }; =20 diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattere= d.c index 16f3ca30626a..6c40d5af8479 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c @@ -54,6 +54,7 @@ static const struct cpuid_bit cpuid_bits[] =3D { { X86_FEATURE_AMD_LBR_V2, CPUID_EAX, 1, 0x80000022, 0 }, { X86_FEATURE_AMD_LBR_PMC_FREEZE, CPUID_EAX, 2, 0x80000022, 0 }, { X86_FEATURE_AMD_HETEROGENEOUS_CORES, CPUID_EAX, 30, 0x80000026, 0 }, + { X86_FEATURE_APX, CPUID_EDX, 21, 0x00000007, 1 }, { 0, 0, 0, 0, 0 } }; =20 --=20 2.45.2 From nobody Sun Feb 8 18:36:54 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 697C726E62B for ; Thu, 27 Feb 2025 18:45:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740681914; cv=none; b=VpLklKYmnO335Ex0Xjuoi7mR3v42vZqDYNF1DdVEAP/4HTyrCbI/B2X7X0TcDT1Ag6qocNncPlCGvceScZ//CH+zWqUjp8LELttp/s/kz4YgDHWAx33uaagbC1uvRR1+qYTuqX9iFRFznZwCKB5qIRM2/hYw7Yf74ZFZPW0THik= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740681914; c=relaxed/simple; bh=REmHNjR8Fo9U3fYKvVBoHL/0BHoODOVa27a+IerHqUk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=rc9l35tM8pfpniO9s2gzGdx1BIMa1hKuAX2GGIj+W+oj0tVmfZKqHGz7jjJnwocA78XNB+AiDVb0+5xlbKREyk9NcQ7EYV5fanmjU5JSGWs/oe/XZRVu6acCXNqFt35rmTJX7xu196ATlt6PAz6DToOBQmSFKby462rj1lmX/rE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=EftE+tCO; arc=none smtp.client-ip=198.175.65.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="EftE+tCO" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1740681913; x=1772217913; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=REmHNjR8Fo9U3fYKvVBoHL/0BHoODOVa27a+IerHqUk=; b=EftE+tCO3ZHfIqFPqhAmSHcA/dpSuA+tlNKD1mjubRh3DKPnojLe/sTq IhDVOPN0nWPB3B2rt+dl+rO6dKWWPYc/ijSMjZj1WfCh7xIvvzsJKEswO ejYt1SjJFGMv34yWbI/cYT02/vuWezdL53yStUxTxkEQ3p9mCiXwxtz/k CLVebpeNtCSpRGYVmBQGnNWIIUUzvEjtdfDuJoGkYWfgcp/HZBTzLpTFP Oh9gpmLLMdJK08MeRg9Umb3wZCRFh8nUiQHfcT+js7Pj/j9eYt9WCayuF K9rbunk1UfwJK6n4oeLqQQpXn8PqI7FWEMDYMecPBJMODaRzIyrulhW/6 g==; X-CSE-ConnectionGUID: lIjasAn6TTe/hWXjpDWydA== X-CSE-MsgGUID: NigtH3fpSl+m5IsLVJqHeg== X-IronPort-AV: E=McAfee;i="6700,10204,11358"; a="41720904" X-IronPort-AV: E=Sophos;i="6.13,320,1732608000"; d="scan'208";a="41720904" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Feb 2025 10:45:12 -0800 X-CSE-ConnectionGUID: zh9BqUzTRuG+gw+WMqsJ6A== X-CSE-MsgGUID: cz0J8MLzTG6PXRjyUSVrgw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,320,1732608000"; d="scan'208";a="117767424" Received: from cbae1-mobl.amr.corp.intel.com (HELO cbae1-mobl.intel.com) ([10.246.154.132]) by fmviesa009.fm.intel.com with ESMTP; 27 Feb 2025 10:45:11 -0800 From: "Chang S. Bae" To: linux-kernel@vger.kernel.org Cc: x86@kernel.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, chang.seok.bae@intel.com Subject: [PATCH RFC v1 08/11] x86/fpu/apx: Define APX state component Date: Thu, 27 Feb 2025 10:44:53 -0800 Message-ID: <20250227184502.10288-9-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250227184502.10288-1-chang.seok.bae@intel.com> References: <20250227184502.10288-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Previously, Advanced Performance Extensions (APX) feature flag was defined. The feature is associated with a new state component number 19. Considering the feature support, it is essential to identify the new xstate component and implement necessary sanity checks. Define the new component number, the state naming, and those registers' data type. Then, extend the size checker to ensure correct validation of the register data type and explicitly sets the APX feature flag as a dependency for the new component in xsave_cpuid_features[]. Include APX in xfeature_noncompact_order[]. Notably, this out-of-order placement demonstrates the practical value of the feature order table. Signed-off-by: Chang S. Bae --- arch/x86/include/asm/fpu/types.h | 9 +++++++++ arch/x86/kernel/fpu/xstate.c | 4 ++++ 2 files changed, 13 insertions(+) diff --git a/arch/x86/include/asm/fpu/types.h b/arch/x86/include/asm/fpu/ty= pes.h index de16862bf230..97310df3ea13 100644 --- a/arch/x86/include/asm/fpu/types.h +++ b/arch/x86/include/asm/fpu/types.h @@ -125,6 +125,7 @@ enum xfeature { XFEATURE_RSRVD_COMP_16, XFEATURE_XTILE_CFG, XFEATURE_XTILE_DATA, + XFEATURE_APX, =20 XFEATURE_MAX, }; @@ -145,6 +146,7 @@ enum xfeature { #define XFEATURE_MASK_LBR (1 << XFEATURE_LBR) #define XFEATURE_MASK_XTILE_CFG (1 << XFEATURE_XTILE_CFG) #define XFEATURE_MASK_XTILE_DATA (1 << XFEATURE_XTILE_DATA) +#define XFEATURE_MASK_APX (1 << XFEATURE_APX) =20 #define XFEATURE_MASK_FPSSE (XFEATURE_MASK_FP | XFEATURE_MASK_SSE) #define XFEATURE_MASK_AVX512 (XFEATURE_MASK_OPMASK \ @@ -303,6 +305,13 @@ struct xtile_data { struct reg_1024_byte tmm; } __packed; =20 +/* + * State component 19: 8B extended general purpose register. + */ +struct apx_state { + u64 egpr[16]; +} __packed; + /* * State component 10 is supervisor state used for context-switching the * PASID state. diff --git a/arch/x86/kernel/fpu/xstate.c b/arch/x86/kernel/fpu/xstate.c index 16f45fff8811..6a6f0e78e2c3 100644 --- a/arch/x86/kernel/fpu/xstate.c +++ b/arch/x86/kernel/fpu/xstate.c @@ -62,6 +62,7 @@ static const char *xfeature_names[] =3D "unknown xstate feature", "AMX Tile config", "AMX Tile data", + "APX registers", "unknown xstate feature", }; =20 @@ -78,6 +79,7 @@ static unsigned short xsave_cpuid_features[] __initdata = =3D { [XFEATURE_CET_USER] =3D X86_FEATURE_SHSTK, [XFEATURE_XTILE_CFG] =3D X86_FEATURE_AMX_TILE, [XFEATURE_XTILE_DATA] =3D X86_FEATURE_AMX_TILE, + [XFEATURE_APX] =3D X86_FEATURE_APX, }; =20 static unsigned int xstate_offsets[XFEATURE_MAX] __ro_after_init =3D @@ -99,6 +101,7 @@ static const enum xfeature xfeature_noncompact_order[] = =3D { XFEATURE_FP, XFEATURE_SSE, XFEATURE_YMM, + XFEATURE_APX, /* Out-of-order feature */ XFEATURE_OPMASK, XFEATURE_ZMM_Hi256, XFEATURE_Hi16_ZMM, @@ -557,6 +560,7 @@ static bool __init check_xstate_against_struct(int nr) case XFEATURE_XTILE_CFG: return XCHECK_SZ(sz, nr, struct xtile_cfg); case XFEATURE_CET_USER: return XCHECK_SZ(sz, nr, struct cet_user_state); case XFEATURE_XTILE_DATA: check_xtile_data_against_struct(sz); return tru= e; + case XFEATURE_APX: return XCHECK_SZ(sz, nr, struct apx_state); default: XSTATE_WARN_ON(1, "No structure for xstate: %d\n", nr); return false; --=20 2.45.2 From nobody Sun Feb 8 18:36:54 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 917AD26E654 for ; Thu, 27 Feb 2025 18:45:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740681915; cv=none; b=rhNTrm15XB2Dsh2JCff/iqOUBvTT0xoyLhLBoh32bmy+Qs4GN6D3vBPd1Hbjv3rlsv4TPiPvnszhZdH26++1PubPWk1UGQNX3m+9bcwiMa9pC679PWi+6NzCNDGzSAgzP2q0O5zMPvjDZowDrLfLCX4jsXpJJJVFujCr0ofOR4g= ARC-Message-Signature: i=1; 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d="scan'208";a="117767433" Received: from cbae1-mobl.amr.corp.intel.com (HELO cbae1-mobl.intel.com) ([10.246.154.132]) by fmviesa009.fm.intel.com with ESMTP; 27 Feb 2025 10:45:13 -0800 From: "Chang S. Bae" To: linux-kernel@vger.kernel.org Cc: x86@kernel.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, chang.seok.bae@intel.com Subject: [PATCH RFC v1 09/11] x86/fpu/apx: Disallow conflicting MPX presence Date: Thu, 27 Feb 2025 10:44:54 -0800 Message-ID: <20250227184502.10288-10-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250227184502.10288-1-chang.seok.bae@intel.com> References: <20250227184502.10288-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" APX is introduced as xstate component 19, following AMX. However, its offset in the non-compacted format overlaps with the area previously occupied by the now-removed MPX. As they cannot coexist, MPX support was removed from the kernel. Despite this, the kernel must ensure the CPU never expose both features at the same time. If so, it indicates unreliable hardware. In such cases, XSAVE should be disabled entirely as a precautionary measure. Add a sanity check to detect this condition and disable XSAVE if an invalid hardware configuration is identified. Signed-off-by: Chang S. Bae --- arch/x86/kernel/fpu/xstate.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/x86/kernel/fpu/xstate.c b/arch/x86/kernel/fpu/xstate.c index 6a6f0e78e2c3..0f731e11c414 100644 --- a/arch/x86/kernel/fpu/xstate.c +++ b/arch/x86/kernel/fpu/xstate.c @@ -802,6 +802,17 @@ void __init fpu__init_system_xstate(unsigned int legac= y_size) goto out_disable; } =20 + if (fpu_kernel_cfg.max_features & XFEATURE_MASK_APX && + fpu_kernel_cfg.max_features & XFEATURE_MASK_BNDREGS) { + /* + * This is a problematic CPU configuration where two + * conflicting state components are both enumerated. + */ + pr_err("x86/fpu: both APX and MPX present in the CPU's xstate features: = 0x%llx.\n", + fpu_kernel_cfg.max_features); + goto out_disable; + } + fpu_kernel_cfg.independent_features =3D fpu_kernel_cfg.max_features & XFEATURE_MASK_INDEPENDENT; =20 --=20 2.45.2 From nobody Sun Feb 8 18:36:54 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3D81026E96C for ; Thu, 27 Feb 2025 18:45:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740681916; cv=none; b=VH7/ExUeIdeQd8s8oqIlo4+E3Fw8TBSL8NQGGrM3fFM5uXAPXspYxwbfRxNN95OmAQlXpJ5HlU7KqWqOv2r6Ae/gS30R3AsNtczGxCsGkRbXIMJJpbQODJoZLZESWaUYpm9UxkZjXGaV6EiCJaomjG3GfgiU3iHBpBHSYZyoDuA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740681916; c=relaxed/simple; bh=EIA3pWCo7/nkJxTTlXr2tqOT4q6Di7DZB2KnMNenfYQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=iRMV62JgfgvXGLabh+jYvn7XNddAlWzk6UcqOKzHRRrH8MQ7e06fvPBSIvFMbiDZ5TFLb30VtH3LiAqW/vMA0JIc21sZqueTE22Fa6bjT2jTIXJlSCJP4LJFuAZcu/EU5tyOYYp6D3VRA/r6LSSIiWQoiI8OtjIVX9w8F5ic18E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Fe9ygmWv; arc=none smtp.client-ip=198.175.65.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Fe9ygmWv" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1740681915; x=1772217915; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=EIA3pWCo7/nkJxTTlXr2tqOT4q6Di7DZB2KnMNenfYQ=; b=Fe9ygmWvqbe1IGP7pEEYjY2ORWSCLQJZf1OTWpnFelX5PdaOqJ3m9THZ qghpqZ5VZtgN55lZt1oH7TJVzlOEY+EUJHov92MTKBtkRtxqZsNTnyB94 /4jFKpZmVXCsYocXBzYXPkzcv/1rCsG6jrFjVRJu9qv/I0s99vfQsvwim cbM4etbZvObuHjkHUfzFLuN0YTZJryM9ld0Fmmi/Bd7lK0VKq6TVo5gNk 2qrX6Mt9ClRC1XeLZgiIv7+uK0jRetUA3fSmiklMcZOjQ6LX2ZEwUGe5X wMM0FbCTF9OhiDqZQB473a7/WKnFe2jW3gN/TgBWn+d3siehdTwmX4HrT Q==; X-CSE-ConnectionGUID: xnVhKQP0ThCwys0OygSfcw== X-CSE-MsgGUID: vj0aJN4LT0+is3jMfxxkaw== X-IronPort-AV: E=McAfee;i="6700,10204,11358"; a="41720920" X-IronPort-AV: E=Sophos;i="6.13,320,1732608000"; d="scan'208";a="41720920" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Feb 2025 10:45:15 -0800 X-CSE-ConnectionGUID: D3MW4hf7Rm6VpVDC+UEIBA== X-CSE-MsgGUID: Oc8TRvsNQjCALQ1CxkV3JQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,320,1732608000"; d="scan'208";a="117767444" Received: from cbae1-mobl.amr.corp.intel.com (HELO cbae1-mobl.intel.com) ([10.246.154.132]) by fmviesa009.fm.intel.com with ESMTP; 27 Feb 2025 10:45:14 -0800 From: "Chang S. Bae" To: linux-kernel@vger.kernel.org Cc: x86@kernel.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, chang.seok.bae@intel.com Subject: [PATCH RFC v1 10/11] x86/fpu/apx: Enable APX state support Date: Thu, 27 Feb 2025 10:44:55 -0800 Message-ID: <20250227184502.10288-11-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250227184502.10288-1-chang.seok.bae@intel.com> References: <20250227184502.10288-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" With securing APX against conflicting MPX, it is now ready to be enabled. Include APX in the enabled xfeature set. Signed-off-by: Chang S. Bae --- arch/x86/include/asm/fpu/xstate.h | 3 ++- arch/x86/kernel/fpu/xstate.c | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/fpu/xstate.h b/arch/x86/include/asm/fpu/x= state.h index e87d36a31ab1..6e3cba7b0068 100644 --- a/arch/x86/include/asm/fpu/xstate.h +++ b/arch/x86/include/asm/fpu/xstate.h @@ -30,7 +30,8 @@ XFEATURE_MASK_ZMM_Hi256 | \ XFEATURE_MASK_Hi16_ZMM | \ XFEATURE_MASK_PKRU | \ - XFEATURE_MASK_XTILE) + XFEATURE_MASK_XTILE | \ + XFEATURE_MASK_APX) =20 /* * Features which are restored when returning to user space. diff --git a/arch/x86/kernel/fpu/xstate.c b/arch/x86/kernel/fpu/xstate.c index 0f731e11c414..d42abad5a0d4 100644 --- a/arch/x86/kernel/fpu/xstate.c +++ b/arch/x86/kernel/fpu/xstate.c @@ -361,7 +361,8 @@ static __init void os_xrstor_booting(struct xregs_state= *xstate) XFEATURE_MASK_PKRU | \ XFEATURE_MASK_PASID | \ XFEATURE_MASK_CET_USER | \ - XFEATURE_MASK_XTILE) + XFEATURE_MASK_XTILE | \ + XFEATURE_MASK_APX) =20 /* * setup the xstate image representing the init state --=20 2.45.2 From nobody Sun Feb 8 18:36:54 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A778026F450 for ; Thu, 27 Feb 2025 18:45:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740681918; cv=none; b=RlJKkTmn2j1AxKnhMV4uNSHtNKfYYU8bND2umLPipRIcC7qmTpnpDR/jQvubFJqYGgEMspQImzcAJpKn9L9oCIk3S9MYy1QURHQjIEyKUXqTAGPZHDOjS5C39VvmKAkYoJleIH/wlFFB6zFFuGl4hjqnEfrZXi2+CHsPaYihVME= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740681918; c=relaxed/simple; bh=gxC4YpulTjL4LyXhFMns9rIvzhJlui2aMfofQzc2VGA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=V9alKDl/WWxGMejvsw70lBe3Gu2HWA9RLwM9TxR2BG1AqUahSc/0p0B0XhY2+3zMrIFwpzEQSwFdeR/dBTjdMcqJeYibaxast3uyHC8hA7B7JNlffk8G952Pk2SuTeGO3B1sWCyaF+p9G87GG9wjE/wzM6JDutldfBQrNAOSrZc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=RKvFxEzq; arc=none smtp.client-ip=198.175.65.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="RKvFxEzq" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1740681917; x=1772217917; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=gxC4YpulTjL4LyXhFMns9rIvzhJlui2aMfofQzc2VGA=; b=RKvFxEzqZ1oKzq13b/wo2MSSHxGkAQso1gbfVAFzHYIYTLIqY+ESE+J9 lo8N2tsoKpwh/emqETfFoncdvvfIQCR7I6DDuTxtzumv7l/1PcRS96TnY 9Z6ok8UE4AUKc6i93nKZB6WQazDI4XvBZpOTPojGsKgFy0Phvs3DQy6jn IHQubkLj/NAbOtT6HxN2zmacqO4yYsrfRsv4JLXf5b9mxImPigkDxUcM9 7r2db+H/fj0/z9cMi4rQ7UY9jq/PkGb81i5L7JeENH0IkFtJmqgVI0zcX eZM+YP3nfMTkv02dODljUnq9r0aJT3RekjA+YeNK/kXxz6WCzZTjubSdf w==; X-CSE-ConnectionGUID: Xf3AT+PnT2GyIPo0/VdN4A== X-CSE-MsgGUID: mdBPoQZHR3GJpksg+LCBlQ== X-IronPort-AV: E=McAfee;i="6700,10204,11358"; a="41720925" X-IronPort-AV: E=Sophos;i="6.13,320,1732608000"; d="scan'208";a="41720925" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Feb 2025 10:45:16 -0800 X-CSE-ConnectionGUID: wfJMc+3LS82MOF+1S9p++A== X-CSE-MsgGUID: OfFZEz4oT+Whyw4Bl0hvkQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,320,1732608000"; d="scan'208";a="117767455" Received: from cbae1-mobl.amr.corp.intel.com (HELO cbae1-mobl.intel.com) ([10.246.154.132]) by fmviesa009.fm.intel.com with ESMTP; 27 Feb 2025 10:45:15 -0800 From: "Chang S. Bae" To: linux-kernel@vger.kernel.org Cc: x86@kernel.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, chang.seok.bae@intel.com Subject: [PATCH RFC v1 11/11] selftests/x86/apx: Add APX test Date: Thu, 27 Feb 2025 10:44:56 -0800 Message-ID: <20250227184502.10288-12-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250227184502.10288-1-chang.seok.bae@intel.com> References: <20250227184502.10288-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The extended general-purpose registers for APX may contain random data, which is currently assumed by the xstate testing framework. This allows the testing of the new userspace feature using the common test code. Invoke the test entry function from apx.c after enumerating the state component and adding it to the support list Signed-off-by: Chang S. Bae --- The patch depends on the selftest xstate series, which was just merged into the x86/fpu branch: https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git/log/?h=3Dx86/= fpu Here is the original series posting: https://lore.kernel.org/lkml/20250226010731.2456-1-chang.seok.bae@intel.c= om/ --- tools/testing/selftests/x86/Makefile | 3 ++- tools/testing/selftests/x86/apx.c | 10 ++++++++++ tools/testing/selftests/x86/xstate.c | 3 ++- tools/testing/selftests/x86/xstate.h | 1 + 4 files changed, 15 insertions(+), 2 deletions(-) create mode 100644 tools/testing/selftests/x86/apx.c diff --git a/tools/testing/selftests/x86/Makefile b/tools/testing/selftests= /x86/Makefile index 28422c32cc8f..f703fcfe9f7c 100644 --- a/tools/testing/selftests/x86/Makefile +++ b/tools/testing/selftests/x86/Makefile @@ -19,7 +19,7 @@ TARGETS_C_32BIT_ONLY :=3D entry_from_vm86 test_syscall_vd= so unwind_vdso \ test_FCMOV test_FCOMI test_FISTTP \ vdso_restorer TARGETS_C_64BIT_ONLY :=3D fsgsbase sysret_rip syscall_numbering \ - corrupt_xstate_header amx lam test_shadow_stack avx + corrupt_xstate_header amx lam test_shadow_stack avx apx # Some selftests require 32bit support enabled also on 64bit systems TARGETS_C_32BIT_NEEDED :=3D ldt_gdt ptrace_syscall =20 @@ -136,3 +136,4 @@ $(OUTPUT)/nx_stack_64: CFLAGS +=3D -Wl,-z,noexecstack $(OUTPUT)/avx_64: CFLAGS +=3D -mno-avx -mno-avx512f $(OUTPUT)/amx_64: EXTRA_FILES +=3D xstate.c $(OUTPUT)/avx_64: EXTRA_FILES +=3D xstate.c +$(OUTPUT)/apx_64: EXTRA_FILES +=3D xstate.c diff --git a/tools/testing/selftests/x86/apx.c b/tools/testing/selftests/x8= 6/apx.c new file mode 100644 index 000000000000..d9c8d41b8c5a --- /dev/null +++ b/tools/testing/selftests/x86/apx.c @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0 + +#define _GNU_SOURCE + +#include "xstate.h" + +int main(void) +{ + test_xstate(XFEATURE_APX); +} diff --git a/tools/testing/selftests/x86/xstate.c b/tools/testing/selftests= /x86/xstate.c index 23c1d6c964ea..97fe4bd8bc77 100644 --- a/tools/testing/selftests/x86/xstate.c +++ b/tools/testing/selftests/x86/xstate.c @@ -31,7 +31,8 @@ (1 << XFEATURE_OPMASK) | \ (1 << XFEATURE_ZMM_Hi256) | \ (1 << XFEATURE_Hi16_ZMM) | \ - (1 << XFEATURE_XTILEDATA)) + (1 << XFEATURE_XTILEDATA) | \ + (1 << XFEATURE_APX)) =20 static inline uint64_t xgetbv(uint32_t index) { diff --git a/tools/testing/selftests/x86/xstate.h b/tools/testing/selftests= /x86/xstate.h index 42af36ec852f..f3c25193a3be 100644 --- a/tools/testing/selftests/x86/xstate.h +++ b/tools/testing/selftests/x86/xstate.h @@ -33,6 +33,7 @@ enum xfeature { XFEATURE_RSRVD_COMP_16, XFEATURE_XTILECFG, XFEATURE_XTILEDATA, + XFEATURE_APX, =20 XFEATURE_MAX, }; --=20 2.45.2