From nobody Sun Feb 8 19:43:48 2026 Received: from mail-m32123.qiye.163.com (mail-m32123.qiye.163.com [220.197.32.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2439422D4D3; Thu, 27 Feb 2025 11:05:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.32.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740654344; cv=none; b=AflXc32PvlzNO+P6kVCMLWSORSAYac5Sri9HAlDLqBs7IEKIBznh9m7+11Q2nq8/LWU45D9Cg/3WcMdctMYo35ZczdIY9kQ0vrsaKdZoL4c395tgoBHbR5z4FCqF1efJhqUqmLQV0s5dN/uIl/2E1o/HaSTKkxWgWbT73wdQS88= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740654344; c=relaxed/simple; bh=BuLMF/+Jcandpr/xf9hkqIm5zz8DcmhFb038I3Uo7So=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Yr/F+cqH8tonvYyQym7DYkeYQtIagsV+0Xx9QPJciSc2V8w83TXdFK1koaKluqzrzVG7Zgd/VbFiE0TGswIxlw5t5efk2N1Auf0Din7tcoBq31k4HsGL1ooarr+pqagVP+5z+lrz8TiuiGthEwQG9v2i+UikWLA5LVZyAGJlE7E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com; spf=pass smtp.mailfrom=rock-chips.com; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b=eh7FZq46; arc=none smtp.client-ip=220.197.32.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="eh7FZq46" Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id c6596abe; Thu, 27 Feb 2025 19:00:24 +0800 (GMT+08:00) From: Kever Yang To: heiko@sntech.de Cc: linux-rockchip@lists.infradead.org, Finley Xiao , Kever Yang , devicetree@vger.kernel.org, Conor Dooley , Rob Herring , Detlev Casanova , linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Elaine Zhang , linux-arm-kernel@lists.infradead.org, Ulf Hansson Subject: [PATCH v3 1/2] dt-bindings: power: rockchip: Add support for RK3562 SoC Date: Thu, 27 Feb 2025 18:59:56 +0800 Message-Id: <20250227105957.2341107-2-kever.yang@rock-chips.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250227105957.2341107-1-kever.yang@rock-chips.com> References: <20250227105957.2341107-1-kever.yang@rock-chips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZGkxCTVZOTxoZTU9CHx9DT0lWFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSU9PT0 hVSktLVUpCS0tZBg++ X-HM-Tid: 0a954710995b03afkunmc6596abe X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6KzY6ECo4QzIIDQ0sEhk1OTI0 LRUaCzlVSlVKTE9LTU5PS0lNSE9MVTMWGhIXVRAeDR4JVQIaFRw7CRQYEFYYExILCFUYFBZFWVdZ EgtZQVlOQ1VJSVVMVUpKT1lXWQgBWUFJT09MNwY+ DKIM-Signature: a=rsa-sha256; b=eh7FZq46Jgp3a7HHUM5GsYUxXIrnqFiadwIPFDRTI0I2Na+jmtSTQAGUqq7a0pAQDwuV52ld7zETileUCJ/O5gPDfah+/oQmtND5ePB2sVZjBia6vuW5yJjk+Vj8Mrmyn8K20HHZmJJmmqglxp5kf0YWAn7u9cEMlbMKBK0b9H0=; c=relaxed/relaxed; s=default; d=rock-chips.com; v=1; bh=F7HQgVZMPu9CDnT8TQDoSbjTr8/jpTklnmLuWptRTyk=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" From: Finley Xiao According to a description from TRM, add all the power domains. Signed-off-by: Finley Xiao Signed-off-by: Kever Yang Reviewed-by: Heiko Stuebner --- Changes in v3: - squash the header file and the binding document - Update license Changes in v2: - rename to rockchip,rk3562-power.h - update the subject - use dual license .../power/rockchip,power-controller.yaml | 1 + .../dt-bindings/power/rockchip,rk3562-power.h | 35 +++++++++++++++++++ 2 files changed, 36 insertions(+) create mode 100644 include/dt-bindings/power/rockchip,rk3562-power.h diff --git a/Documentation/devicetree/bindings/power/rockchip,power-control= ler.yaml b/Documentation/devicetree/bindings/power/rockchip,power-controlle= r.yaml index 650dc0aae6f5..79b948518f0c 100644 --- a/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml +++ b/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml @@ -40,6 +40,7 @@ properties: - rockchip,rk3366-power-controller - rockchip,rk3368-power-controller - rockchip,rk3399-power-controller + - rockchip,rk3562-power-controller - rockchip,rk3568-power-controller - rockchip,rk3576-power-controller - rockchip,rk3588-power-controller diff --git a/include/dt-bindings/power/rockchip,rk3562-power.h b/include/dt= -bindings/power/rockchip,rk3562-power.h new file mode 100644 index 000000000000..5182c2427a55 --- /dev/null +++ b/include/dt-bindings/power/rockchip,rk3562-power.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2022-2024 Rockchip Electronics Co., Ltd. + */ +#ifndef __DT_BINDINGS_POWER_RK3562_POWER_H__ +#define __DT_BINDINGS_POWER_RK3562_POWER_H__ + +/* VD_CORE */ +#define RK3562_PD_CPU_0 0 +#define RK3562_PD_CPU_1 1 +#define RK3562_PD_CPU_2 2 +#define RK3562_PD_CPU_3 3 +#define RK3562_PD_CORE_ALIVE 4 + +/* VD_PMU */ +#define RK3562_PD_PMU 5 +#define RK3562_PD_PMU_ALIVE 6 + +/* VD_NPU */ +#define RK3562_PD_NPU 7 + +/* VD_GPU */ +#define RK3562_PD_GPU 8 + +/* VD_LOGIC */ +#define RK3562_PD_DDR 9 +#define RK3562_PD_VEPU 10 +#define RK3562_PD_VDPU 11 +#define RK3562_PD_VI 12 +#define RK3562_PD_VO 13 +#define RK3562_PD_RGA 14 +#define RK3562_PD_PHP 15 +#define RK3562_PD_LOGIC_ALIVE 16 + +#endif --=20 2.25.1 From nobody Sun Feb 8 19:43:48 2026 Received: from mail-m1973193.qiye.163.com (mail-m1973193.qiye.163.com [220.197.31.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1E3251DB122; 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arc=none smtp.client-ip=220.197.31.93 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="Txix2qS2" Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id c6596ac9; Thu, 27 Feb 2025 19:00:26 +0800 (GMT+08:00) From: Kever Yang To: heiko@sntech.de Cc: linux-rockchip@lists.infradead.org, Kever Yang , Finley Xiao , Krzysztof Kozlowski , linux-pm@vger.kernel.org, Jonathan Cameron , Detlev Casanova , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Ulf Hansson Subject: [PATCH v3 2/2] soc: rockchip: power-domain: add power domain support for rk3562 Date: Thu, 27 Feb 2025 18:59:57 +0800 Message-Id: <20250227105957.2341107-3-kever.yang@rock-chips.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250227105957.2341107-1-kever.yang@rock-chips.com> References: <20250227105957.2341107-1-kever.yang@rock-chips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZGk0ZQ1YaT00dSx8eGU5OT0hWFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSU9PT0 hVSktLVUpCS0tZBg++ X-HM-Tid: 0a9547109f3203afkunmc6596ac9 X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6NRw6NBw*KTINTg0BAiICOTIa EhwKCTVVSlVKTE9LTU5PS0lMTUJCVTMWGhIXVRAeDR4JVQIaFRw7CRQYEFYYExILCFUYFBZFWVdZ EgtZQVlOQ1VJSVVMVUpKT1lXWQgBWUFPT0lMNwY+ DKIM-Signature: a=rsa-sha256; b=Txix2qS21u7XOR6rtQdlq1PXcupaV8OhxHDt0ZzGNQe0tZU/WaBCglnB5ST5JX1Ve1TCtvJXSNtVhRWCUfM8kDyY+cX7ysamMjFWNtShxyDQnerEM8Cv/sIEgWJxiVhFl0nhtU12FHeEjQrXiNkcHhGWkW55L3CUfabm6PWVFbI=; c=relaxed/relaxed; s=default; d=rock-chips.com; v=1; bh=DKX8ERULlKOlqmEzPMDQ7tcuj/pXzM/HFpRfsyeTQqQ=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" This driver is modified to support RK3562 SoC. Add support to ungate clk. Add support to shut down memory for rk3562. Signed-off-by: Finley Xiao Signed-off-by: Kever Yang Reviewed-by: Heiko Stuebner --- Changes in v3: None Changes in v2: - update the header name drivers/pmdomain/rockchip/pm-domains.c | 48 +++++++++++++++++++++++++- 1 file changed, 47 insertions(+), 1 deletion(-) diff --git a/drivers/pmdomain/rockchip/pm-domains.c b/drivers/pmdomain/rock= chip/pm-domains.c index cb0f93800138..d05ec0a009a0 100644 --- a/drivers/pmdomain/rockchip/pm-domains.c +++ b/drivers/pmdomain/rockchip/pm-domains.c @@ -2,7 +2,7 @@ /* * Rockchip Generic power domain support. * - * Copyright (c) 2015 ROCKCHIP, Co. Ltd. + * Copyright (c) 2015 Rockchip Electronics Co., Ltd. */ =20 #include @@ -32,6 +32,7 @@ #include #include #include +#include #include #include #include @@ -129,6 +130,20 @@ struct rockchip_pmu { .active_wakeup =3D wakeup, \ } =20 +#define DOMAIN_M_G_SD(_name, pwr, status, req, idle, ack, g_mask, mem, wak= eup, keepon) \ +{ \ + .name =3D _name, \ + .pwr_w_mask =3D (pwr) << 16, \ + .pwr_mask =3D (pwr), \ + .status_mask =3D (status), \ + .req_w_mask =3D (req) << 16, \ + .req_mask =3D (req), \ + .idle_mask =3D (idle), \ + .ack_mask =3D (ack), \ + .clk_ungate_mask =3D (g_mask), \ + .active_wakeup =3D wakeup, \ +} + #define DOMAIN_M_O_R(_name, p_offset, pwr, status, m_offset, m_status, r_s= tatus, r_offset, req, idle, ack, wakeup) \ { \ .name =3D _name, \ @@ -194,6 +209,9 @@ struct rockchip_pmu { #define DOMAIN_RK3399(name, pwr, status, req, wakeup) \ DOMAIN(name, pwr, status, req, req, req, wakeup) =20 +#define DOMAIN_RK3562(name, pwr, req, g_mask, mem, wakeup) \ + DOMAIN_M_G_SD(name, pwr, pwr, req, req, req, g_mask, mem, wakeup, false) + #define DOMAIN_RK3568(name, pwr, req, wakeup) \ DOMAIN_M(name, pwr, pwr, req, req, req, wakeup) =20 @@ -1130,6 +1148,18 @@ static const struct rockchip_domain_info rk3399_pm_d= omains[] =3D { [RK3399_PD_SDIOAUDIO] =3D DOMAIN_RK3399("sdioaudio", BIT(31), BIT(31), BI= T(29), true), }; =20 +static const struct rockchip_domain_info rk3562_pm_domains[] =3D { + /* name pwr req g_mask mem wakeup */ + [RK3562_PD_GPU] =3D DOMAIN_RK3562("gpu", BIT(0), BIT(1), BIT(1),= 0, false), + [RK3562_PD_NPU] =3D DOMAIN_RK3562("npu", BIT(1), BIT(2), BIT(2),= 0, false), + [RK3562_PD_VDPU] =3D DOMAIN_RK3562("vdpu", BIT(2), BIT(6), BIT(6),= 0, false), + [RK3562_PD_VEPU] =3D DOMAIN_RK3562("vepu", BIT(3), BIT(7), BIT(7) = | BIT(3), 0, false), + [RK3562_PD_RGA] =3D DOMAIN_RK3562("rga", BIT(4), BIT(5), BIT(5) = | BIT(4), 0, false), + [RK3562_PD_VI] =3D DOMAIN_RK3562("vi", BIT(5), BIT(3), BIT(3), = 0, false), + [RK3562_PD_VO] =3D DOMAIN_RK3562("vo", BIT(6), BIT(4), BIT(4), 16, fals= e), + [RK3562_PD_PHP] =3D DOMAIN_RK3562("php", BIT(7), BIT(8), BIT(8),= 0, false), +}; + static const struct rockchip_domain_info rk3568_pm_domains[] =3D { [RK3568_PD_NPU] =3D DOMAIN_RK3568("npu", BIT(1), BIT(2), false), [RK3568_PD_GPU] =3D DOMAIN_RK3568("gpu", BIT(0), BIT(1), false), @@ -1331,6 +1361,18 @@ static const struct rockchip_pmu_info rk3399_pmu =3D= { .domain_info =3D rk3399_pm_domains, }; =20 +static const struct rockchip_pmu_info rk3562_pmu =3D { + .pwr_offset =3D 0x210, + .status_offset =3D 0x230, + .req_offset =3D 0x110, + .idle_offset =3D 0x128, + .ack_offset =3D 0x120, + .clk_ungate_offset =3D 0x140, + + .num_domains =3D ARRAY_SIZE(rk3562_pm_domains), + .domain_info =3D rk3562_pm_domains, +}; + static const struct rockchip_pmu_info rk3568_pmu =3D { .pwr_offset =3D 0xa0, .status_offset =3D 0x98, @@ -1429,6 +1471,10 @@ static const struct of_device_id rockchip_pm_domain_= dt_match[] =3D { .compatible =3D "rockchip,rk3399-power-controller", .data =3D (void *)&rk3399_pmu, }, + { + .compatible =3D "rockchip,rk3562-power-controller", + .data =3D (void *)&rk3562_pmu, + }, { .compatible =3D "rockchip,rk3568-power-controller", .data =3D (void *)&rk3568_pmu, --=20 2.25.1