From nobody Fri Dec 19 16:05:28 2025 Received: from mail-pj1-f73.google.com (mail-pj1-f73.google.com [209.85.216.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3D7938BEC for ; Thu, 27 Feb 2025 01:13:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.73 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740618810; cv=none; b=V892ULX6Of6YhVhvEL0omPuW3tT/wNv8k+AqfG64gsrn9OQS9Bdw9cljeKQ6YdgKCVI7K147wF4XUNbtOX5zhy30h40arick1fFcEReKJZdWQLkSrXkBXp34mDNrHoknFLv13NJw5akkWWCTaCR/MfEFvvOzc+fmsylB7yaSaDY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740618810; c=relaxed/simple; bh=zm2QaR360KIl6iSEbDz2zLo3X3lN7lh4lpL7RxCk81I=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=l3dg2rM7PJJUmQTPlVLagxsW0m8SmDzxEmoUNm7s3jNgdnw8JAK8xoHWSnPmy6Pxk54z0Q0DpmJVEb2KxzWYVsACNGy0qsXfU0qgu72mvjkmDHth2ia6pAAA5MtbyTQJ3OUOhRGLE6wOmlb0qb/yWKyMXLIMFXIaDTn7YILVrsg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=wRd89/ii; arc=none smtp.client-ip=209.85.216.73 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="wRd89/ii" Received: by mail-pj1-f73.google.com with SMTP id 98e67ed59e1d1-2f81a0d0a18so968683a91.3 for ; Wed, 26 Feb 2025 17:13:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1740618808; x=1741223608; darn=vger.kernel.org; h=content-transfer-encoding:cc:to:from:subject:message-id:references :mime-version:in-reply-to:date:reply-to:from:to:cc:subject:date :message-id:reply-to; bh=0b+q4LTl32D7RG/ClIETiGyEI98jipo9UuVZ1dxYatM=; b=wRd89/iii27OqFapIVMolJmD9T0c5Dy3zTnftS1MoFzmPRE4KydgURruYpBG5PNHJN t+uYDGWKxesHEg81ljVNJwFdWnPleG43Sj70vFtKr5mON2aLmTuQvWhi0b7kq4buOoL4 qkI9tdHUdfp12IJj+1dZnK8zT9nXb5KE3RM9FYpYi97LeencG+HLQdzq+yK+BdbHYtEy V6fZNMyZE1J/MspMkON4upRIpBONxjQQ3JUQaLqJmgWGGO6R1oU3u3nkDOZALQoUszS9 tqY9VzFrolqSnH6jVxWbqynJy+OjsHA4DqNpvrQZ0QgZzfVthdpIQgrKGi2l24zOA2ci i11g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740618808; x=1741223608; h=content-transfer-encoding:cc:to:from:subject:message-id:references :mime-version:in-reply-to:date:reply-to:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=0b+q4LTl32D7RG/ClIETiGyEI98jipo9UuVZ1dxYatM=; b=OupTXUbGJ3zvNUv/rYlkHu/7Uc73Fr6IK3+pjM+iweScllBRBHOEJHnbAFFjspncVK BImkfMaRdUm49N3oNr0lSRZlzL700vsJZHMLmknEmHTwhu6WVzB5gVodHxdkJ9fk00PV gGrSsKfT6ZKPukhiXkCglmmr8CWklqCjDgAXMDC/lrVTCk3Xe/5Ezmg+3SRIB+4j9d/q Y5jDzGSbI46na+Utj3/F3cHK5N9uZ4nHQKQ01bENRayGU9SNlzUsCp5LlkQhDPFiWoZT BuhZG8b4Sj7oPLaQPCK0377KgJu9gOJICBRIp4VSsxcMpSllSUX7OdknvYCwuKyO/EmV BQHg== X-Forwarded-Encrypted: i=1; AJvYcCXBiCk1OZJEsC0ujSxIijFtzoIzjNVp0duMSs1EqpE4CSRRv5YU9+xEiI5lMj40P6HBedAERp6vo3EYWr0=@vger.kernel.org X-Gm-Message-State: AOJu0YwxHHEEZqg8HaroBDowLSrTugxij9hRVbZsce9wjD7Tgo0b/FOt 5HKiiyRkgoGNl/EodmOePrZF0ENR0FEqI0XUkzeBonYJ8q16ZU5K/HK61vJRSYbbXPGDCjqr9FD 7Xw== X-Google-Smtp-Source: AGHT+IH4j2hz+QG3bfdUby9AHcMKdde1f0mz0Lh4hjfInlOzv66k2GVgHs1NibxtzgfdBTAmj0DWWrBKdCc= X-Received: from pgzz124.prod.google.com ([2002:a63:3382:0:b0:801:d5e9:804f]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6a21:3287:b0:1ee:d06c:cddc with SMTP id adf61e73a8af0-1f0fc78fb84mr17684149637.30.1740618808506; Wed, 26 Feb 2025 17:13:28 -0800 (PST) Reply-To: Sean Christopherson Date: Wed, 26 Feb 2025 17:13:17 -0800 In-Reply-To: <20250227011321.3229622-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250227011321.3229622-1-seanjc@google.com> X-Mailer: git-send-email 2.48.1.711.g2feabab25a-goog Message-ID: <20250227011321.3229622-2-seanjc@google.com> Subject: [PATCH v2 1/5] KVM: SVM: Drop DEBUGCTL[5:2] from guest's effective value From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Ravi Bangoria , Xiaoyao Li , rangemachine@gmail.com, whanos@sergal.fun Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Drop bits 5:2 from the guest's effective DEBUGCTL value, as AMD changed the architectural behavior of the bits and broke backwards compatibility. On CPUs without BusLockTrap (or at least, in APMs from before ~2023), bits 5:2 controlled the behavior of external pins: Performance-Monitoring/Breakpoint Pin-Control (PBi)=E2=80=94Bits 5:2, rea= d/write. Software uses thesebits to control the type of information reported by the four external performance-monitoring/breakpoint pins on the processor. When a PBi bit is cleared to 0, the corresponding external pin (BPi) reports performance-monitor information. When a PBi bit is set to 1, the corresponding external pin (BPi) reports breakpoint information. With the introduction of BusLockTrap, presumably to be compatible with Intel CPUs, AMD redefined bit 2 to be BLCKDB: Bus Lock #DB Trap (BLCKDB)=E2=80=94Bit 2, read/write. Software sets this = bit to enable generation of a #DB trap following successful execution of a bus lock when CPL is > 0. and redefined bits 5:3 (and bit 6) as "6:3 Reserved MBZ". Ideally, KVM would treat bits 5:2 as reserved. Defer that change to a feature cleanup to avoid breaking existing guest in LTS kernels. For now, drop the bits to retain backwards compatibility (of a sort). Note, dropping bits 5:2 is still a guest-visible change, e.g. if the guest is enabling LBRs *and* the legacy PBi bits, then the state of the PBi bits is visible to the guest, whereas now the guest will always see '0'. Reported-by: Ravi Bangoria Cc: stable@vger.kernel.org Signed-off-by: Sean Christopherson --- arch/x86/kvm/svm/svm.c | 12 ++++++++++++ arch/x86/kvm/svm/svm.h | 2 +- 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index b8aa0f36850f..2280bd1d0863 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -3165,6 +3165,18 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, struct= msr_data *msr) kvm_pr_unimpl_wrmsr(vcpu, ecx, data); break; } + + /* + * AMD changed the architectural behavior of bits 5:2. On CPUs + * without BusLockTrap, bits 5:2 control "external pins", but + * on CPUs that support BusLockDetect, bit 2 enables BusLockTrap + * and bits 5:3 are reserved-to-zero. Sadly, old KVM allowed + * the guest to set bits 5:2 despite not actually virtualizing + * Performance-Monitoring/Breakpoint external pins. Drop bits + * 5:2 for backwards compatibility. + */ + data &=3D ~GENMASK(5, 2); + if (data & DEBUGCTL_RESERVED_BITS) return 1; =20 diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h index 5b159f017055..f573548b7b41 100644 --- a/arch/x86/kvm/svm/svm.h +++ b/arch/x86/kvm/svm/svm.h @@ -582,7 +582,7 @@ static inline bool is_vnmi_enabled(struct vcpu_svm *svm) /* svm.c */ #define MSR_INVALID 0xffffffffU =20 -#define DEBUGCTL_RESERVED_BITS (~(0x3fULL)) +#define DEBUGCTL_RESERVED_BITS (~(DEBUGCTLMSR_BTF | DEBUGCTLMSR_LBR)) =20 extern bool dump_invalid_vmcb; =20 --=20 2.48.1.711.g2feabab25a-goog From nobody Fri Dec 19 16:05:28 2025 Received: from mail-pj1-f74.google.com (mail-pj1-f74.google.com [209.85.216.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 09341839F4 for ; Thu, 27 Feb 2025 01:13:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.74 ARC-Seal: i=1; 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Wed, 26 Feb 2025 17:13:30 -0800 (PST) Reply-To: Sean Christopherson Date: Wed, 26 Feb 2025 17:13:18 -0800 In-Reply-To: <20250227011321.3229622-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250227011321.3229622-1-seanjc@google.com> X-Mailer: git-send-email 2.48.1.711.g2feabab25a-goog Message-ID: <20250227011321.3229622-3-seanjc@google.com> Subject: [PATCH v2 2/5] KVM: x86: Snapshot the host's DEBUGCTL in common x86 From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Ravi Bangoria , Xiaoyao Li , rangemachine@gmail.com, whanos@sergal.fun Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Move KVM's snapshot of DEBUGCTL to kvm_vcpu_arch and take the snapshot in common x86, so that SVM can also use the snapshot. Opportunistically change the field to a u64. While bits 63:32 are reserved on AMD, not mentioned at all in Intel's SDM, and managed as an "unsigned long" by the kernel, DEBUGCTL is an MSR and therefore a 64-bit value. Reviewed-by: Xiaoyao Li Cc: stable@vger.kernel.org Signed-off-by: Sean Christopherson --- arch/x86/include/asm/kvm_host.h | 1 + arch/x86/kvm/vmx/vmx.c | 8 ++------ arch/x86/kvm/vmx/vmx.h | 2 -- arch/x86/kvm/x86.c | 1 + 4 files changed, 4 insertions(+), 8 deletions(-) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_hos= t.h index 3506f497741b..02bffe6b54c8 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -781,6 +781,7 @@ struct kvm_vcpu_arch { u32 pkru; u32 hflags; u64 efer; + u64 host_debugctl; u64 apic_base; struct kvm_lapic *apic; /* kernel irqchip context */ bool load_eoi_exitmap_pending; diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index b71392989609..729c224b72dd 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -1514,16 +1514,12 @@ void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int = cpu, */ void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu) { - struct vcpu_vmx *vmx =3D to_vmx(vcpu); - if (vcpu->scheduled_out && !kvm_pause_in_guest(vcpu->kvm)) shrink_ple_window(vcpu); =20 vmx_vcpu_load_vmcs(vcpu, cpu, NULL); =20 vmx_vcpu_pi_load(vcpu, cpu); - - vmx->host_debugctlmsr =3D get_debugctlmsr(); } =20 void vmx_vcpu_put(struct kvm_vcpu *vcpu) @@ -7458,8 +7454,8 @@ fastpath_t vmx_vcpu_run(struct kvm_vcpu *vcpu, bool f= orce_immediate_exit) } =20 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */ - if (vmx->host_debugctlmsr) - update_debugctlmsr(vmx->host_debugctlmsr); + if (vcpu->arch.host_debugctl) + update_debugctlmsr(vcpu->arch.host_debugctl); =20 #ifndef CONFIG_X86_64 /* diff --git a/arch/x86/kvm/vmx/vmx.h b/arch/x86/kvm/vmx/vmx.h index 8b111ce1087c..951e44dc9d0e 100644 --- a/arch/x86/kvm/vmx/vmx.h +++ b/arch/x86/kvm/vmx/vmx.h @@ -340,8 +340,6 @@ struct vcpu_vmx { /* apic deadline value in host tsc */ u64 hv_deadline_tsc; =20 - unsigned long host_debugctlmsr; - /* * Only bits masked by msr_ia32_feature_control_valid_bits can be set in * msr_ia32_feature_control. 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Wed, 26 Feb 2025 17:13:31 -0800 (PST) Reply-To: Sean Christopherson Date: Wed, 26 Feb 2025 17:13:19 -0800 In-Reply-To: <20250227011321.3229622-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250227011321.3229622-1-seanjc@google.com> X-Mailer: git-send-email 2.48.1.711.g2feabab25a-goog Message-ID: <20250227011321.3229622-4-seanjc@google.com> Subject: [PATCH v2 3/5] KVM: SVM: Manually context switch DEBUGCTL if LBR virtualization is disabled From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Ravi Bangoria , Xiaoyao Li , rangemachine@gmail.com, whanos@sergal.fun Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Manually load the guest's DEBUGCTL prior to VMRUN (and restore the host's value on #VMEXIT) if it diverges from the host's value and LBR virtualization is disabled, as hardware only context switches DEBUGCTL if LBR virtualization is fully enabled. Running the guest with the host's value has likely been mildly problematic for quite some time, e.g. it will result in undesirable behavior if BTF diverges. But the bug became fatal with the introduction of Bus Lock Trap ("Detect" in kernel paralance) support for AMD (commit 408eb7417a92 ("x86/bus_lock: Add support for AMD")), as a bus lock in the guest will trigger an unexpected #DB. Note, suppressing the bus lock #DB, i.e. simply resuming the guest without injecting a #DB, is not an option. It wouldn't address the general issue with DEBUGCTL, e.g. for things like BTF, and there are other guest-visible side effects if BusLockTrap is left enabled. If BusLockTrap is disabled, then DR6.BLD is reserved-to-1; any attempts to clear it by software are ignored. But if BusLockTrap is enabled, software can clear DR6.BLD: Software enables bus lock trap by setting DebugCtl MSR[BLCKDB] (bit 2) to 1. When bus lock trap is enabled, ... The processor indicates that this #DB was caused by a bus lock by clearing DR6[BLD] (bit 11). DR6[11] previously had been defined to be always 1. and clearing DR6.BLD is "sticky" in that it's not set (i.e. lowered) by other #DBs: All other #DB exceptions leave DR6[BLD] unmodified E.g. leaving BusLockTrap enable can confuse a legacy guest that writes '0' to reset DR6. Reported-by: rangemachine@gmail.com Reported-by: whanos@sergal.fun Closes: https://bugzilla.kernel.org/show_bug.cgi?id=3D219787 Closes: https://lore.kernel.org/all/bug-219787-28872@https.bugzilla.kernel.= org%2F Cc: Ravi Bangoria Cc: stable@vger.kernel.org Signed-off-by: Sean Christopherson --- arch/x86/kvm/svm/svm.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 2280bd1d0863..3924b9b198f4 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -4265,6 +4265,16 @@ static __no_kcsan fastpath_t svm_vcpu_run(struct kvm= _vcpu *vcpu, clgi(); kvm_load_guest_xsave_state(vcpu); =20 + /* + * Hardware only context switches DEBUGCTL if LBR virtualization is + * enabled. Manually load DEBUGCTL if necessary (and restore it after + * VM-Exit), as running with the host's DEBUGCTL can negatively affect + * guest state and can even be fatal, e.g. due to Bus Lock Detect. + */ + if (!(svm->vmcb->control.virt_ext & LBR_CTL_ENABLE_MASK) && + vcpu->arch.host_debugctl !=3D svm->vmcb->save.dbgctl) + update_debugctlmsr(0); + kvm_wait_lapic_expire(vcpu); =20 /* @@ -4292,6 +4302,10 @@ static __no_kcsan fastpath_t svm_vcpu_run(struct kvm= _vcpu *vcpu, if (unlikely(svm->vmcb->control.exit_code =3D=3D SVM_EXIT_NMI)) kvm_before_interrupt(vcpu, KVM_HANDLING_NMI); =20 + if (!(svm->vmcb->control.virt_ext & LBR_CTL_ENABLE_MASK) && + vcpu->arch.host_debugctl !=3D svm->vmcb->save.dbgctl) + update_debugctlmsr(vcpu->arch.host_debugctl); + kvm_load_host_xsave_state(vcpu); stgi(); =20 --=20 2.48.1.711.g2feabab25a-goog From nobody Fri Dec 19 16:05:28 2025 Received: from mail-pj1-f74.google.com (mail-pj1-f74.google.com [209.85.216.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2AFC124B28 for ; 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Wed, 26 Feb 2025 17:13:33 -0800 (PST) Reply-To: Sean Christopherson Date: Wed, 26 Feb 2025 17:13:20 -0800 In-Reply-To: <20250227011321.3229622-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250227011321.3229622-1-seanjc@google.com> X-Mailer: git-send-email 2.48.1.711.g2feabab25a-goog Message-ID: <20250227011321.3229622-5-seanjc@google.com> Subject: [PATCH v2 4/5] KVM: x86: Snapshot the host's DEBUGCTL after disabling IRQs From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Ravi Bangoria , Xiaoyao Li , rangemachine@gmail.com, whanos@sergal.fun Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Snapshot the host's DEBUGCTL after disabling IRQs, as perf can toggle debugctl bits from IRQ context, e.g. when enabling/disabling events via smp_call_function_single(). Taking the snapshot (long) before IRQs are disabled could result in KVM effectively clobbering DEBUGCTL due to using a stale snapshot. Cc: stable@vger.kernel.org Signed-off-by: Sean Christopherson --- arch/x86/kvm/x86.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 09c3d27cc01a..a2cd734beef5 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -4991,7 +4991,6 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cp= u) =20 /* Save host pkru register if supported */ vcpu->arch.host_pkru =3D read_pkru(); - vcpu->arch.host_debugctl =3D get_debugctlmsr(); =20 /* Apply any externally detected TSC adjustments (due to suspend) */ if (unlikely(vcpu->arch.tsc_offset_adjustment)) { @@ -10984,6 +10983,8 @@ static int vcpu_enter_guest(struct kvm_vcpu *vcpu) set_debugreg(0, 7); } =20 + vcpu->arch.host_debugctl =3D get_debugctlmsr(); + guest_timing_enter_irqoff(); =20 for (;;) { --=20 2.48.1.711.g2feabab25a-goog From nobody Fri Dec 19 16:05:28 2025 Received: from mail-pj1-f74.google.com (mail-pj1-f74.google.com [209.85.216.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D25BD15624B for ; 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Wed, 26 Feb 2025 17:13:35 -0800 (PST) Reply-To: Sean Christopherson Date: Wed, 26 Feb 2025 17:13:21 -0800 In-Reply-To: <20250227011321.3229622-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250227011321.3229622-1-seanjc@google.com> X-Mailer: git-send-email 2.48.1.711.g2feabab25a-goog Message-ID: <20250227011321.3229622-6-seanjc@google.com> Subject: [PATCH v2 5/5] KVM: SVM: Treat DEBUGCTL[5:2] as reserved From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Ravi Bangoria , Xiaoyao Li , rangemachine@gmail.com, whanos@sergal.fun Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Stop ignoring DEBUGCTL[5:2] on AMD CPUs and instead treat them as reserved. KVM has never properly virtualized AMD's legacy PBi bits, but did allow the guest (and host userspace) to set the bits. To avoid breaking guests when running on CPUs with BusLockTrap, which redefined bit 2 to BLCKDB and made bits 5:3 reserved, a previous KVM change ignored bits 5:3, e.g. so that legacy guest software wouldn't inadvertently enable BusLockTrap or hit a VMRUN failure due to setting reserved. To allow for virtualizing BusLockTrap and whatever future features may use bits 5:3, treat bits 5:2 as reserved (and hope that doing so doesn't break any existing guests). Signed-off-by: Sean Christopherson --- arch/x86/kvm/svm/svm.c | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 3924b9b198f4..7fc99c30d2cc 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -3166,17 +3166,6 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, struct= msr_data *msr) break; } =20 - /* - * AMD changed the architectural behavior of bits 5:2. On CPUs - * without BusLockTrap, bits 5:2 control "external pins", but - * on CPUs that support BusLockDetect, bit 2 enables BusLockTrap - * and bits 5:3 are reserved-to-zero. Sadly, old KVM allowed - * the guest to set bits 5:2 despite not actually virtualizing - * Performance-Monitoring/Breakpoint external pins. Drop bits - * 5:2 for backwards compatibility. - */ - data &=3D ~GENMASK(5, 2); - if (data & DEBUGCTL_RESERVED_BITS) return 1; =20 --=20 2.48.1.711.g2feabab25a-goog