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Thu, 27 Feb 2025 01:04:43 -0800 (PST) From: Neil Armstrong Date: Thu, 27 Feb 2025 10:04:40 +0100 Subject: [PATCH v2 2/2] arm64: dts: qcom: sm8650: add PPI interrupt partitions for the ARM PMUs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250227-topic-sm8650-pmu-ppi-partition-v2-2-b93006a65037@linaro.org> References: <20250227-topic-sm8650-pmu-ppi-partition-v2-0-b93006a65037@linaro.org> In-Reply-To: <20250227-topic-sm8650-pmu-ppi-partition-v2-0-b93006a65037@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong , Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1833; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=k/Ub0j4ZPZ5XJlCOR/aNVmHDxi435bw376+PW8znVRM=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBnwCqpDyLRWaVQvhbd2/CzIVYOqzXz5gMqHm0jDq8p UFIoxYmJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZ8AqqQAKCRB33NvayMhJ0Wx8D/ sFXR4XRXUMwe+wzOQZkk9549jr5pdzc0yfTGe8aPUSOvJ7kebnpgFn8oxriVn7ujC6W45uPEElqEmh 6oG9Z66xvenLQUyHJayjH0pnZVOgWXFfyvMBPpGRchukp2ZuKXWm1xkRjAiVHmwBPx+Lw5e+PmETYL qBLHOXGLmtPvuwIWQY4+Pmppl+6V3xtwtjxXxC7SHCMsnwhU6XLLrCBThRzMgr+hsZUBf4yDtZRVAL 3kmSXdx7GvK8A5vUiU3+Eoi8e0fJW3NfLYxwm1dHvmSw5Wb46zXeF3Nw8MALmg/xK3Z+UKCVvC6xzP baLnC0TcPN232EaM3XqbXvIBiEenwS6FkIjUakvlcZlgQJrf3Z14cJ1du+l91V422VASZNdummU1y8 mup/1cFt+6B4QoUNciUHvUi4x7GG51bKGLmPbSGFG7HFnIRwrDYj7lPkmXXpIuUH5PCvmQ3bguWJln rEQSia5gYMuooHEfPGwN2hHaxvOFHK3A1TwLDdOHeKRaC6dpJNEKcrwqB6PJ8QNyHFzf9JpFMMHdoL 5sr9ZoUqFky+1oh24qReBa5xdNHU8DfcO6Luyl+PMVdskiGKxEKQw44r+1rKsw+lsndQN+UwSPK4cf sIrhIsBXfYs2rpoyWRwbpoNwWHBsMYLre5yJWX1dR/jQCOZeyjgowOV6u5Fw== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE The PMUs shares the same per-cpu (PPI) interrupt, so declare the proper interrupt partition maps and use the 4th interrupt cell to pass the partition phandle for each ARM PMU node. Reviewed-by: Konrad Dybcio Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qco= m/sm8650.dtsi index 273170a2e9499b900b3348307f13c9bc1a9a7345..58646b50bb437fd5eb2ac8cf395= 5be2db020d6e1 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -1417,17 +1417,17 @@ opp-3302400000 { =20 pmu-a520 { compatible =3D "arm,cortex-a520-pmu"; - interrupts =3D ; + interrupts =3D ; }; =20 pmu-a720 { compatible =3D "arm,cortex-a720-pmu"; - interrupts =3D ; + interrupts =3D ; }; =20 pmu-x4 { compatible =3D "arm,cortex-x4-pmu"; - interrupts =3D ; + interrupts =3D ; }; =20 psci { @@ -6590,6 +6590,20 @@ intc: interrupt-controller@17100000 { #size-cells =3D <2>; ranges; =20 + ppi-partitions { + ppi_cluster0: interrupt-partition-0 { + affinity =3D <&cpu0 &cpu1>; + }; + + ppi_cluster1: interrupt-partition-1 { + affinity =3D <&cpu2 &cpu3 &cpu4 &cpu5 &cpu6>; + }; + + ppi_cluster2: interrupt-partition-2 { + affinity =3D <&cpu7>; + }; + }; + gic_its: msi-controller@17140000 { compatible =3D "arm,gic-v3-its"; reg =3D <0 0x17140000 0 0x20000>; --=20 2.34.1