From nobody Fri Dec 19 03:42:44 2025 Received: from mail-ed1-f46.google.com (mail-ed1-f46.google.com [209.85.208.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B39F522A4C9 for ; Thu, 27 Feb 2025 10:46:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740653201; cv=none; b=BqnM/BmQBVouXIRzfDPlrCDNt71s7voKeLX18FzNB/X9HoCDOdsNMbmYxZlJuI9s8Z/OpCx4QBIRBCr9rm8mLMjNuWAsDFnfcVQXOsU/QDEhWwAAvAczpr7iMt2hTt+HB1hP8W8g+oZfWaAidF8VZGBD5LwVr1JWoy99Jd2/axE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740653201; c=relaxed/simple; bh=Fv+Vqu4aLmTdNPILdT13ma7EJcUK4NwGz9D26gQo45Q=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=KLkXNIxt7hTYMa+UwDx2zpfTPN4ZyRqBBg1F7/YoUQ6nhcylCOhpGd9nA1KkszZOCMFbzmYVQPiFIPwy+w3DtloM91A2IA9762EOvEmXy0KeXpXl65SUS5t4TqXqlVIa2CTGiH1hNVmln7VQIUl/FLkdbGOyxlqOvMT5IS1u2ic= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=z5LfcoJn; arc=none smtp.client-ip=209.85.208.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="z5LfcoJn" Received: by mail-ed1-f46.google.com with SMTP id 4fb4d7f45d1cf-5e0373c7f55so1091727a12.0 for ; Thu, 27 Feb 2025 02:46:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1740653198; x=1741257998; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=8k4UeAxgXPxbM8uTLcaaHeF7Iy7tq78qIdeyogxmduc=; b=z5LfcoJnf7eQcCuUhLj8zVyU28bV1z4K1zRdG4ZGt9h05sJvq26TBBZiL68WFFkT5X G+ZAQW+jiXqswyDQwi6AGPJc4ILM11gdPvh+FsDbBSnwhXMQZymoUhe2IIu4InqIij8+ 34fVLJoLhYgcKoz9CJj4JkDbS5akLHrZF9NDRz/d0CWVxK+dwQ5HIK81upuwOkz3RsrR /nKQ5Ud4iAImQIRUnqzjtxL5hmKD53JPydm4POLyye7u5/Y3zZWxx76cUuYBuv+NwcNM tEXzxusepb7Upqu0vSq6vXwBflNQ2FzthjPBV/97NoN1ngscKi6HHWl55/Qb/qB77enG ldRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740653198; x=1741257998; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8k4UeAxgXPxbM8uTLcaaHeF7Iy7tq78qIdeyogxmduc=; b=jVufL30bZuaZ0Lt4PcdPxuiYwAujNz6bJYEZWOLb/D31PuPv+jUagHIDgozRFpNsnV SIrY5xnVbsZZT5WxBmQnbf6mV719XpYiswSmKi0ixpVY3SwjPONRm6k2KinSPwMF4Zms 2NJ3dmD4QGOgkn/1ZEkkkr5Y4CVrseSP/d8r45GTZZM25l9sIcMaYd7vEGIU7c18+mK+ MbYDsxq3Zg1lt6gIQ0XBLkBNw2jG7S8hfL8p0/vJfN4xiYYpMNnwnQ21QAdtSCQsq9K2 EAVo+us/D4f23kqkny7hFQ1w63TkAyfqIdHoSrRvcvqixg4JvgRrNZt8BGvB1D6lv7aT zzMQ== X-Forwarded-Encrypted: i=1; AJvYcCX7KK2GKkmewbOn6dX6Y2fmdNA1ZehtBBsWIVbfyeyDoru52wc5FmgFsMPGL4pnlTHDwEM4wXzCbOUQelc=@vger.kernel.org X-Gm-Message-State: AOJu0YwjNvwlkmduNxeVENYO40zP6M5uguEjYM8UW472X25aH+HvkYhl Fz9vEnD2xvnSxR3J0UDhsZJkOcps4xiA4csSxseFgrvDXmoj86TMETDiiwXOMiz9otP/A9YrXpn RdPI= X-Gm-Gg: ASbGnct+bzO9FUEwN4EbVPdgUthrbEIQxwTsI0z9a7iogE5DxcX/8YUnuslONCL8BXe PzX9g9usifVXsLIo1XnEF88N3elyRE0DoceLB8GjlKiR3HiZSKLhHT4LE07bPM/8r5XUlRYiO34 8XT3y/pfYeL+uWg7W0diH/iPjxa9qVlXSb9nu9VdP7SS259Tk5mLbnH6ztuJOe1VGrmYpo2jaJd Bu8IZpLKJiIamk51ctA21o6eypcvTsXmTxcLyPMsyW/M6Qb+E8F88NomsZElIKX7FvGYFXCiomN +0ShwpNlLeVs0Wz2ewnIsHPm+kIU/q2gLeoffdLFdoeLH+lymf7YJG3Qbs4cEJqL0B7mA017NLH ss4ej02fB+Q== X-Google-Smtp-Source: AGHT+IFo+oKuun2HuLc+8veX5xMjZbpzxtHRPbWgeY3acHUg0egOWClYav/m4dncD6RgXkaOD/3PgQ== X-Received: by 2002:a05:6402:5208:b0:5da:105b:86c1 with SMTP id 4fb4d7f45d1cf-5e4a0e01567mr8727100a12.23.1740653198027; Thu, 27 Feb 2025 02:46:38 -0800 (PST) Received: from puffmais.c.googlers.com (30.171.91.34.bc.googleusercontent.com. [34.91.171.30]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5e4c3bb5ad8sm901032a12.34.2025.02.27.02.46.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Feb 2025 02:46:37 -0800 (PST) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Thu, 27 Feb 2025 10:46:13 +0000 Subject: [PATCH v3 1/2] dt-bindings: reset: syscon-reboot: support reset modes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250227-syscon-reboot-reset-mode-v3-1-959ac53c338a@linaro.org> References: <20250227-syscon-reboot-reset-mode-v3-0-959ac53c338a@linaro.org> In-Reply-To: <20250227-syscon-reboot-reset-mode-v3-0-959ac53c338a@linaro.org> To: Sebastian Reichel , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Peter Griffin , Tudor Ambarus , Will McVicker , kernel-team@android.com, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.14.2 Add support for specifying different register/mask/value combinations for different types of reset. In particular, update the binding to allow platforms to specify the following reset modes: soft, warm, cold, hard. Linux can perform different types of reset using its reboot=3D kernel command line argument, and some platforms also wish to reset differently based on whether or not e.g. contents of RAM should be retained across the reboot. The new properties match the existing properties, just prefixed with one of the reset modes mentioned above. Signed-off-by: Andr=C3=A9 Draszik --- .../bindings/power/reset/syscon-reboot.yaml | 74 ++++++++++++++++++= ++++ 1 file changed, 74 insertions(+) diff --git a/Documentation/devicetree/bindings/power/reset/syscon-reboot.ya= ml b/Documentation/devicetree/bindings/power/reset/syscon-reboot.yaml index 19d3093e6cd2f7e39d94c56636dc202a4427ffc3..1bd821877a16b274ac78a80017d= 003f1aa9fd471 100644 --- a/Documentation/devicetree/bindings/power/reset/syscon-reboot.yaml +++ b/Documentation/devicetree/bindings/power/reset/syscon-reboot.yaml @@ -18,6 +18,11 @@ description: |+ parental dt-node. So the SYSCON reboot node should be represented as a sub-node of a "syscon", "simple-mfd" node. Though the regmap property pointing to the system controller node is also supported. + This also supports specification of separate sets of register/mask/value + pairs for different types of reset: cold, hard, soft and warm, using + the respective properties with the respective reset type prefix. If pref= ixed + properties are not specified for a reset type, the non-prefixed properti= es + will be used for that reset type. =20 properties: compatible: @@ -49,12 +54,41 @@ properties: priority: default: 192 =20 +patternProperties: + "^(cold|hard|soft|warm)-(mask|offset|value)$": + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Optional alternative offset / mask / value combinations for specific + reboot modes. The mask is optional. + + "^(cold|hard|soft|warm)-reg$": + description: + Optional alternative base address and size for the reboot register f= or + specific reboot modes. + oneOf: - required: - offset - required: - reg =20 +dependencies: + cold-mask: [ cold-value ] + cold-offset: [ cold-value ] + cold-reg: [ cold-value ] + + hard-mask: [ hard-value ] + hard-offset: [ hard-value ] + hard-reg: [ hard-value ] + + soft-mask: [ soft-value ] + soft-offset: [ soft-value ] + soft-reg: [ soft-value ] + + warm-mask: [ warm-value ] + warm-offset: [ warm-value ] + warm-reg: [ warm-value ] + required: - compatible =20 @@ -70,6 +104,46 @@ allOf: required: - value =20 + - if: + required: + - cold-value + then: + oneOf: + - required: + - cold-offset + - required: + - cold-reg + + - if: + required: + - hard-value + then: + oneOf: + - required: + - hard-offset + - required: + - hard-reg + + - if: + required: + - soft-value + then: + oneOf: + - required: + - soft-offset + - required: + - soft-reg + + - if: + required: + - warm-value + then: + oneOf: + - required: + - warm-offset + - required: + - warm-reg + examples: - | reboot { --=20 2.48.1.711.g2feabab25a-goog From nobody Fri Dec 19 03:42:44 2025 Received: from mail-ed1-f50.google.com (mail-ed1-f50.google.com [209.85.208.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A6C7322A4E1 for ; Thu, 27 Feb 2025 10:46:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740653203; cv=none; b=hh58yWY8lGQ+Dkh0n5vZ6Jg4Lz7tYwNuUAb1S/hMRp5o59qG3j26QTSE3ojPPlYbrVR+oJQNvRvPupdikNLlaESrqtMvtJEN35F2h7TOPsFZVakrlHTSDfWfJIZll7q/UqE9ByvjRda7irQmtL/Yx51M7exdAZbH6c6dm7/wpkw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740653203; c=relaxed/simple; bh=W9D+anLswderraXRnZUvbxnOgYIsKuJjLY7iig4it4o=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=GSQog1H11xCfXHfOWPbWPb5ppeeq1NFX8B6IFrb5eTY/eHKK8Y5y8H7KOqED1Zoo0wr7m0aAqyaawHbv8XEL0VzMXNVXvKNnZLoI+caoR0PeZ8PQnkq0kC690VHchbL43W0REd2hFfsItenfxChPhin5f9ash585LTt+C2j4ecM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=GommgqJB; arc=none smtp.client-ip=209.85.208.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="GommgqJB" Received: by mail-ed1-f50.google.com with SMTP id 4fb4d7f45d1cf-5dec996069aso1175803a12.2 for ; Thu, 27 Feb 2025 02:46:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1740653199; x=1741257999; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=2GinroxZiXaUl0iulTclS3Q5Hjx+0LaS8RfRGW3GbBU=; b=GommgqJBDnmdCWUQoaT/QRdTmY4OZMLY4f/lOQxdY3kKNUeZ/Kh9UTxpVkOimpzOg1 7IiL9URGjV3A1ZmfU+jVStjqJCC/ACb+SukMt9LcTfzudK2jAzQhG3jUcgCsHgT5qjNw xHdmwj5xg3Kso1JBMzfgJYKheV/jDJtHuWTpNRgZBgW9FnLzuoC4sgtxRb1tPPfGkAK0 iTkbE+8O6bSEqMQTIZnALNvJSXiipBycvL7E1mNtsx4WWuq+5/DC9wm3IKTcCZxxtHb6 PvuoD21i4ZTag2K9CiGyoAyFI3ktwX2nbjVGx+bwwcYW7UBUY6kznuYcO4KLmho0M5AQ xEVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740653199; x=1741257999; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2GinroxZiXaUl0iulTclS3Q5Hjx+0LaS8RfRGW3GbBU=; b=F0drAhJfwwmfdXb0e5IPNI7zURzU/Zj2XvhWNlrlSj2eOATaqZ3opk3Y5FDgzh/p4o MuD5fpasPEthicA3uWtcduFIP/3KFvu9yNtmINMER/U1QcX0foP0nJsne0VZgQB+N1NM tiOZD9yzp3j8kGg2v8CcQxNyDIIMYDMKhWwfLxIVnMEFjYThbbZNbH/cM2R0ogngrpGF 2yFtE2qQsOetawYFGTnkTIUKkXrWK70kk/HoWGnu/Bnqr1WFoJWmXxkwi3BhZnbda5mp 0OygwDnP7uBOE0M2iGyyeE8BX8kYa/5TkFT6R9uf2gPSRZUuvyeOkNkX7IfX7pHNRQH6 XSow== X-Forwarded-Encrypted: i=1; AJvYcCVNqdoXPUYGCrqhE8D6xL/nzVFG/T7NaxskwmZs+uVpg9Ys9jgDq0uxo9bt/jdB89gzNzhAYC8fq60ydy0=@vger.kernel.org X-Gm-Message-State: AOJu0YxRDO42g0sNezYHhW0BBLNwVWkGSoNBlen3yStjqoO4LIyri+Sy BWSwT82RXAn1DBK6E/bWKuQ7KPH5skKcQ6m1MdcnNiMyzQcjOSHVMYyIcCKN4EguIj1v0yEqv6t cX+o= X-Gm-Gg: ASbGncsH5cxoAp7hufS0xmTc/wJiThr6s5eclLu0xKXNOwgqe6QG5w9MCkehNHGuYVq Ec/j/Nj9mon9kV8RmsoP0bsg3/35sOqsNWF0cxjw0osYG84k/hqsKnXcAVxdqSpeuwf0QToqEPU XQcvi+Jx0ZrtpVzup1hQIOwFtrCtn9MEWkzrSA3bQ+tffPItvGbMp0JQkkuGTarF44XMUCMKsTf HRRAOT/4/+5qvyk7QjOhW/J2A5slMU2WZ1E1/Yr+ZD5xU5P4/xxKJmTHdqEQr5RBFbxyyElOMmi vwnB4QIibFVXqYra+UTyGdvp9yMhR9/gEbEGJtud4WpKvVaFAWWiskULm4AmYl3D6i87OPTz0xR 1vNO1OZnQ2g== X-Google-Smtp-Source: AGHT+IFqCgtaEn18UyqkDgMvhRqj12YBC1o82ZagmdpxbrZDloQykLk5OMYN37B77iU31+3OfQ8GNw== X-Received: by 2002:a05:6402:27d3:b0:5e0:82a0:50ab with SMTP id 4fb4d7f45d1cf-5e4a0e160e3mr9376148a12.27.1740653198730; Thu, 27 Feb 2025 02:46:38 -0800 (PST) Received: from puffmais.c.googlers.com (30.171.91.34.bc.googleusercontent.com. [34.91.171.30]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5e4c3bb5ad8sm901032a12.34.2025.02.27.02.46.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Feb 2025 02:46:38 -0800 (PST) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Thu, 27 Feb 2025 10:46:14 +0000 Subject: [PATCH v3 2/2] power: reset: syscon-reboot: support different reset modes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250227-syscon-reboot-reset-mode-v3-2-959ac53c338a@linaro.org> References: <20250227-syscon-reboot-reset-mode-v3-0-959ac53c338a@linaro.org> In-Reply-To: <20250227-syscon-reboot-reset-mode-v3-0-959ac53c338a@linaro.org> To: Sebastian Reichel , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Peter Griffin , Tudor Ambarus , Will McVicker , kernel-team@android.com, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.14.2 Linux supports a couple different reset modes, but this driver here doesn't distinguish between them and issues the same syscon register write irrespective of the reset mode requested by the kernel. Update this driver to support most of Linux' reset modes: cold, hard, warm, and soft. The actions to take for these are taken from DT, and are all new optional properties. The property names match the existing properties supported but should be prefixed with the reset mode. This change is meant to be backwards compatible with existing DTs, and if Linux requests a reset mode that this driver doesn't support, or that the DT doesn't specify, the reset is triggered using the fallback / default entry. As an example why this is useful, other than properly supporting the Linux reboot=3D kernel command line option or sysfs entry, this change allows platforms to e.g. default to a more secure cold-reset, but also to do a warm-reset in case RAM contents needs to be retained across the reset. Signed-off-by: Andr=C3=A9 Draszik --- drivers/power/reset/syscon-reboot.c | 96 ++++++++++++++++++++++++++++++++-= ---- 1 file changed, 85 insertions(+), 11 deletions(-) diff --git a/drivers/power/reset/syscon-reboot.c b/drivers/power/reset/sysc= on-reboot.c index d623d77e657e4c233d8ae88bb099bee13c48a9ef..81b917a531b8bf04d7c5e7027bd= c3290f2183eb0 100644 --- a/drivers/power/reset/syscon-reboot.c +++ b/drivers/power/reset/syscon-reboot.c @@ -14,11 +14,29 @@ #include #include =20 -struct syscon_reboot_context { - struct regmap *map; +/* REBOOT_GPIO doesn't make sense for syscon-reboot */ +static const struct { + enum reboot_mode mode; + const char *prefix; +} prefix_map[] =3D { + { .mode =3D REBOOT_COLD, .prefix =3D "cold" }, + { .mode =3D REBOOT_WARM, .prefix =3D "warm" }, + { .mode =3D REBOOT_HARD, .prefix =3D "hard" }, + { .mode =3D REBOOT_SOFT, .prefix =3D "soft" }, +}; + +struct reboot_mode_bits { u32 offset; u32 value; u32 mask; + bool valid; +}; + +struct syscon_reboot_context { + struct regmap *map; + + struct reboot_mode_bits mode_bits[REBOOT_SOFT + 1]; + struct reboot_mode_bits catchall; struct notifier_block restart_handler; }; =20 @@ -28,9 +46,16 @@ static int syscon_restart_handle(struct notifier_block *= this, struct syscon_reboot_context *ctx =3D container_of(this, struct syscon_reboot_context, restart_handler); + const struct reboot_mode_bits *mode_bits; + + if (mode < ARRAY_SIZE(ctx->mode_bits) && ctx->mode_bits[mode].valid) + mode_bits =3D &ctx->mode_bits[mode]; + else + mode_bits =3D &ctx->catchall; =20 /* Issue the reboot */ - regmap_update_bits(ctx->map, ctx->offset, ctx->mask, ctx->value); + regmap_update_bits(ctx->map, mode_bits->offset, mode_bits->mask, + mode_bits->value); =20 mdelay(1000); =20 @@ -60,12 +85,61 @@ static int syscon_reboot_probe(struct platform_device *= pdev) if (of_property_read_s32(pdev->dev.of_node, "priority", &priority)) priority =3D 192; =20 - if (of_property_read_u32(pdev->dev.of_node, "offset", &ctx->offset)) - if (of_property_read_u32(pdev->dev.of_node, "reg", &ctx->offset)) + /* try to catch enum reboot_mode changing in any incompatible way */ + BUILD_BUG_ON(ARRAY_SIZE(prefix_map) !=3D ARRAY_SIZE(ctx->mode_bits)); + BUILD_BUG_ON(ARRAY_SIZE(ctx->mode_bits) <=3D REBOOT_COLD); + BUILD_BUG_ON(ARRAY_SIZE(ctx->mode_bits) <=3D REBOOT_WARM); + BUILD_BUG_ON(ARRAY_SIZE(ctx->mode_bits) <=3D REBOOT_HARD); + BUILD_BUG_ON(ARRAY_SIZE(ctx->mode_bits) <=3D REBOOT_SOFT); + + for (int i =3D 0; i < ARRAY_SIZE(prefix_map); ++i) { + const char * const prefix =3D prefix_map[i].prefix; + struct reboot_mode_bits * const mode_bits =3D + &ctx->mode_bits[prefix_map[i].mode]; + char prop[32]; + + snprintf(prop, sizeof(prop), "%s-offset", prefix); + if (of_property_read_u32(pdev->dev.of_node, prop, + &mode_bits->offset)) { + snprintf(prop, sizeof(prop), "%s-reg", prefix); + if (of_property_read_u32(pdev->dev.of_node, prop, + &mode_bits->offset)) + continue; + } + + snprintf(prop, sizeof(prop), "%s-value", prefix); + if (of_property_read_u32(pdev->dev.of_node, prop, + &mode_bits->value)) { + /* + * unlike catchall below, don't support old binding + * here + */ + dev_err(dev, "'%s' is mandatory\n", prop); + continue; + } + + snprintf(prop, sizeof(prop), "%s-mask", prefix); + mask_err =3D of_property_read_u32(pdev->dev.of_node, prop, + &mode_bits->mask); + + if (mask_err) + /* support value without mask */ + mode_bits->mask =3D 0XFFFFFFFF; + + mode_bits->valid =3D true; + } + + /* catch-all entry */ + if (of_property_read_u32(pdev->dev.of_node, "offset", + &ctx->catchall.offset)) + if (of_property_read_u32(pdev->dev.of_node, "reg", + &ctx->catchall.offset)) return -EINVAL; =20 - value_err =3D of_property_read_u32(pdev->dev.of_node, "value", &ctx->valu= e); - mask_err =3D of_property_read_u32(pdev->dev.of_node, "mask", &ctx->mask); + value_err =3D of_property_read_u32(pdev->dev.of_node, "value", + &ctx->catchall.value); + mask_err =3D of_property_read_u32(pdev->dev.of_node, "mask", + &ctx->catchall.mask); if (value_err && mask_err) { dev_err(dev, "unable to read 'value' and 'mask'"); return -EINVAL; @@ -73,11 +147,11 @@ static int syscon_reboot_probe(struct platform_device = *pdev) =20 if (value_err) { /* support old binding */ - ctx->value =3D ctx->mask; - ctx->mask =3D 0xFFFFFFFF; + ctx->catchall.value =3D ctx->catchall.mask; + ctx->catchall.mask =3D 0xFFFFFFFF; } else if (mask_err) { - /* support value without mask*/ - ctx->mask =3D 0xFFFFFFFF; + /* support value without mask */ + ctx->catchall.mask =3D 0xFFFFFFFF; } =20 ctx->restart_handler.notifier_call =3D syscon_restart_handle; --=20 2.48.1.711.g2feabab25a-goog