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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-223504dc86esm25058925ad.172.2025.02.27.21.38.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Feb 2025 21:38:26 -0800 (PST) From: Unnathi Chalicheemala Date: Thu, 27 Feb 2025 21:38:16 -0800 Subject: [PATCH v5 1/2] firmware: qcom_scm: Add API to get waitqueue IRQ info Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250227-multi_waitq_scm-v5-1-16984ea97edf@oss.qualcomm.com> References: <20250227-multi_waitq_scm-v5-0-16984ea97edf@oss.qualcomm.com> In-Reply-To: <20250227-multi_waitq_scm-v5-0-16984ea97edf@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, kernel@oss.qualcomm.com, Bartosz Golaszewski , Prasad Sodagudi , Satya Durga Srinivasu Prabhala , Trilok Soni , Unnathi Chalicheemala X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1740721104; l=4268; i=unnathi.chalicheemala@oss.qualcomm.com; s=20240514; h=from:subject:message-id; bh=OqK+6bYKkV3iT+dYNoLFz1KU+sVRWlpSWMpzlk1uVVU=; b=/FjwIud489kNkvfzeN/1ib3iISgcoC/q4fUHrnRY1SIb44gIOblUXga/9qYO6EC7ItfVL17LL S2TqzfOG+NMB1DRGuG3paI/CAJrklKU3Wusj36ZLDyg8sYXW6RKnKgF X-Developer-Key: i=unnathi.chalicheemala@oss.qualcomm.com; a=ed25519; pk=o+hVng49r5k2Gc/f9xiwzvR3y1q4kwLOASwo+cFowXI= X-Proofpoint-GUID: H-FtLpwVloPt-7SkwOIFVrvlx_3Ti3kQ X-Proofpoint-ORIG-GUID: H-FtLpwVloPt-7SkwOIFVrvlx_3Ti3kQ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-27_08,2025-02-27_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 mlxscore=0 mlxlogscore=999 bulkscore=0 adultscore=0 phishscore=0 priorityscore=1501 lowpriorityscore=0 malwarescore=0 clxscore=1011 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2502100000 definitions=main-2502280038 Bootloader and firmware for SM8650 and older chipsets expect node name as "qcom_scm", in order to patch the wait queue IRQ information. However, DeviceTree uses node name "scm" and this mismatch prevents firmware from correctly identifying waitqueue IRQ information. Waitqueue IRQ is used for signaling between secure and non-secure worlds. To resolve this, introduce qcom_scm_get_waitq_irq() that'll get the hardware IRQ number to be used from firmware instead of relying on data provided by devicetree, thereby bypassing the DeviceTree node name mismatch. This hardware IRQ number is converted to a Linux IRQ number using newly defined fill_irq_fwspec_params(). This Linux IRQ number is then supplied to the threaded_irq call. Signed-off-by: Unnathi Chalicheemala Reviewed-by: Bartosz Golaszewski --- drivers/firmware/qcom/qcom_scm.c | 60 ++++++++++++++++++++++++++++++++++++= +++- drivers/firmware/qcom/qcom_scm.h | 1 + 2 files changed, 60 insertions(+), 1 deletion(-) diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_= scm.c index f0569bb9411f7175c97a4ede50b3775fece330cf..1aa42685640da8a14191557896f= bb49423697a10 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -29,12 +29,18 @@ #include #include #include +#include =20 #include "qcom_scm.h" #include "qcom_tzmem.h" =20 static u32 download_mode; =20 +#define GIC_SPI_BASE 32 +#define GIC_MAX_SPI 1019 // SPIs in GICv3 spec range from 32..1019 +#define GIC_ESPI_BASE 4096 +#define GIC_MAX_ESPI 5119 // ESPIs in GICv3 spec range from 4096..5119 + struct qcom_scm { struct device *dev; struct clk *core_clk; @@ -2094,6 +2100,55 @@ bool qcom_scm_is_available(void) } EXPORT_SYMBOL_GPL(qcom_scm_is_available); =20 +static int qcom_scm_fill_irq_fwspec_params(struct irq_fwspec *fwspec, u32 = virq) +{ + if (virq >=3D GIC_SPI_BASE && virq <=3D GIC_MAX_SPI) { + fwspec->param[0] =3D GIC_SPI; + fwspec->param[1] =3D virq - GIC_SPI_BASE; + } else if (virq >=3D GIC_ESPI_BASE && virq <=3D GIC_MAX_ESPI) { + fwspec->param[0] =3D GIC_ESPI; + fwspec->param[1] =3D virq - GIC_ESPI_BASE; + } else { + WARN(1, "Unexpected virq: %d\n", virq); + return -ENXIO; + } + fwspec->param[2] =3D IRQ_TYPE_EDGE_RISING; + fwspec->param_count =3D 3; + + return 0; +} + +static int qcom_scm_get_waitq_irq(void) +{ + int ret; + u32 hwirq; + struct qcom_scm_desc desc =3D { + .svc =3D QCOM_SCM_SVC_WAITQ, + .cmd =3D QCOM_SCM_WAITQ_GET_INFO, + .owner =3D ARM_SMCCC_OWNER_SIP + }; + struct qcom_scm_res res; + struct irq_fwspec fwspec; + struct device_node *parent_irq_node; + + ret =3D qcom_scm_call_atomic(__scm->dev, &desc, &res); + if (ret) + return ret; + + hwirq =3D res.result[1] & GENMASK(15, 0); + + ret =3D qcom_scm_fill_irq_fwspec_params(&fwspec, hwirq); + if (ret) + return ret; + parent_irq_node =3D of_irq_find_parent(__scm->dev->of_node); + + fwspec.fwnode =3D of_node_to_fwnode(parent_irq_node); + + ret =3D irq_create_fwspec_mapping(&fwspec); + + return ret; +} + static int qcom_scm_assert_valid_wq_ctx(u32 wq_ctx) { /* FW currently only supports a single wq_ctx (zero). @@ -2250,7 +2305,10 @@ static int qcom_scm_probe(struct platform_device *pd= ev) /* Paired with smp_load_acquire() in qcom_scm_is_available(). */ smp_store_release(&__scm, scm); =20 - irq =3D platform_get_irq_optional(pdev, 0); + irq =3D qcom_scm_get_waitq_irq(); + if (irq < 0) + irq =3D platform_get_irq_optional(pdev, 0); + if (irq < 0) { if (irq !=3D -ENXIO) { ret =3D irq; diff --git a/drivers/firmware/qcom/qcom_scm.h b/drivers/firmware/qcom/qcom_= scm.h index 097369d38b84efbce5d672c4f36cc87373aac24b..7c6cb3154b394ab910bf7775a5a= e07a28e0b57a5 100644 --- a/drivers/firmware/qcom/qcom_scm.h +++ b/drivers/firmware/qcom/qcom_scm.h @@ -148,6 +148,7 @@ struct qcom_tzmem_pool *qcom_scm_get_tzmem_pool(void); #define QCOM_SCM_SVC_WAITQ 0x24 #define QCOM_SCM_WAITQ_RESUME 0x02 #define QCOM_SCM_WAITQ_GET_WQ_CTX 0x03 +#define QCOM_SCM_WAITQ_GET_INFO 0x04 =20 #define QCOM_SCM_SVC_GPU 0x28 #define QCOM_SCM_SVC_GPU_INIT_REGS 0x01 --=20 2.34.1