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Wed, 26 Feb 2025 15:43:00 -0800 (PST) From: Inochi Amaoto To: Philipp Zabel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen Wang , Inochi Amaoto , Paul Walmsley , Palmer Dabbelt , Albert Ou , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Guo Ren Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, sophgo@lists.linux.dev, linux-riscv@lists.infradead.org, Yixun Lan , Longbin Li Subject: [PATCH v2 1/5] dt-bindings: reset: add generic bit reset controller Date: Thu, 27 Feb 2025 07:42:29 +0800 Message-ID: <20250226234234.125305-2-inochiama@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250226234234.125305-1-inochiama@gmail.com> References: <20250226234234.125305-1-inochiama@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some SoCs from Aspeed, Allwinner, Sophgo and Synopsys have a simple reset controller by toggling bit. It is a hard time for each device to add its own compatible to the driver. Since these devices share a common design, it is possible to add a common device to reduce these unnecessary change for the driver. Add common binding for these kind generic reset controller. Check the binding description for its requirement and suitable scenarios. Signed-off-by: Inochi Amaoto --- .../bindings/reset/reset-simple.yaml | 61 +++++++++++++++++++ 1 file changed, 61 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/reset-simple.ya= ml diff --git a/Documentation/devicetree/bindings/reset/reset-simple.yaml b/Do= cumentation/devicetree/bindings/reset/reset-simple.yaml new file mode 100644 index 000000000000..86c33a608148 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/reset-simple.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/reset-simple.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Generic Bit Reset Controller + +maintainers: + - Inochi Amaoto + +description: | + This document defines device tree properties common to reset + controller devices that perform assert/deassert by simply + toggling bit. + + All devices in this binding should satisfy the following requirement: + - There is a single, contiguous range of 32-bit registers. + - All bits in each register directly control a reset line. + - There are no self-deasserting resets. + - There are no timing requirements. + - The bits are exclusively resets, nothing else. + - All bits behave the same, so all reset bits are either + active-high or all are active-low. + - The bits can be read back, but the read status may + be active-low independently from the writes. + + If the device is not meet the requirement, it should use its + own binding to describe the device. + +properties: + compatible: + const: reset-simple + + reg: + maxItems: 1 + + "#reset-cells": + const: 1 + + active-low: + type: boolean + description: + If true, bits are cleared to assert the reset. Otherwise, + bits are set to assert the reset. This also applies to + read back. + +required: + - compatible + - reg + - "#reset-cells" + +additionalProperties: false + +examples: + - | + reset-controller@1000000 { + compatible =3D "reset-simple"; + reg =3D <0x1000000 0x1000>; + #reset-cells =3D <1>; + }; --=20 2.48.1