From nobody Wed Dec 17 12:43:44 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 35EA625B672; Wed, 26 Feb 2025 21:37:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740605857; cv=none; b=NxUIHjoXviA0iFLqg9Vi1QFEAPnJOnM+YRNZlBZ8uql7GXyBwnRtz3jKMUzN8QqiWq/B4UZYTg3/IXkjneO95XoLy+MVFHBXER67GSfOPm/mIRKJSQozwSMrEuOssNqVdYs2RNdjLYckVEEkpLs2Oq0ARU//06uy/VWAtTNhvGE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740605857; c=relaxed/simple; bh=RlkJX0MrhsJeOtYwbzKz9uU11pc4QQCMS9xkZOpuwfo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=HXNOZfi/6aKvbR5Nlh8KuRTtsBqfOnnIt81vrQDAW1WKA7k/ui8BytzJoqJHESXfZ514NeBjYo/2XnL2TRIX3H8i6RjWm6LpvNmrWLcb+UQBQk+rn7qeZzoptbmzNKWLqwjouMv9A1WqZe2BBxQiYehYDWka506M9l3jRZZ5ZqI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=CE7ISIiE; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="CE7ISIiE" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C017BC4CEE7; Wed, 26 Feb 2025 21:37:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1740605857; bh=RlkJX0MrhsJeOtYwbzKz9uU11pc4QQCMS9xkZOpuwfo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CE7ISIiEN2Hji+NgktAwqWFB07Os68S3dsCqnBgMW8k5xkOo5gWM6ysoxNTbFa+o/ XSEC8UUczGK2nqzN+qXaVnVkdvoqFi9YjqEGo5nrwC87gjPNHiBK90Q4qO1Xihv3c4 ZmNI3Y7tUf/rvLd8cevbn949rbxKouDFTZF82gH/WTXDLvrGkwunrR/ngFLYdJmjoC a7fzjlv7IkJzofmfb4iXE3nKwVGBuHcT24stYO7p86P2tq6fimGaoybjN28LiZsk8r 61asg/oLuTd0VrDPKhjLbDZro7leV5fV/mzDbhNvV5vukRnQYGSReTZxCjLObwyPIh 30sCj1B/Pcu4Q== From: Arnd Bergmann To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Arnd Bergmann , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Linus Torvalds , Andy Shevchenko , Matthew Wilcox , stable@vger.kernel.org Subject: [PATCH v3 01/10] x86/Kconfig: Geode CPU has cmpxchg8b Date: Wed, 26 Feb 2025 22:37:05 +0100 Message-Id: <20250226213714.4040853-2-arnd@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250226213714.4040853-1-arnd@kernel.org> References: <20250226213714.4040853-1-arnd@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Arnd Bergmann An older cleanup of mine inadvertently removed geode-gx1 and geode-lx from the list of CPUs that are known to support a working cmpxchg8b. Fixes: 88a2b4edda3d ("x86/Kconfig: Rework CONFIG_X86_PAE dependency") Cc: stable@vger.kernel.org Signed-off-by: Arnd Bergmann --- arch/x86/Kconfig.cpu | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu index 2a7279d80460..42e6a40876ea 100644 --- a/arch/x86/Kconfig.cpu +++ b/arch/x86/Kconfig.cpu @@ -368,7 +368,7 @@ config X86_HAVE_PAE =20 config X86_CMPXCHG64 def_bool y - depends on X86_HAVE_PAE || M586TSC || M586MMX || MK6 || MK7 + depends on X86_HAVE_PAE || M586TSC || M586MMX || MK6 || MK7 || MGEODEGX1 = || MGEODE_LX =20 # this should be set for all -march=3D.. options where the compiler # generates cmov. --=20 2.39.5 From nobody Wed Dec 17 12:43:44 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1D35325D547 for ; Wed, 26 Feb 2025 21:37:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740605860; cv=none; b=QTzh5XMaiexCY8P+tX+bvjWLlklds/jEtlPYjEDycPSbpITXxJUBwLyAh3YCUF/iwnYsrc7az6xcTyN4JJ4CX9Wa0CNFVV4r/edU1ThYz3BTFKVH5DHiN4QYyvxIY5SgSu7t5dKTDHJtE2Wpt5qdN3a3Hh8YxlOFF3qKmzPGwdY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740605860; c=relaxed/simple; bh=crXP1Ouatdf2x6aP5TkGMgQuZwKDhYLTGhBQaqUk7As=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=mqNXtgz6U8pZpZnX9zF0hws1Fp3tWB+Ln+OCsn3UJfOX3bjhpzEMSK0PUFW8W5dhSBMYYErtEOKVsfB6aIFYxr5doCB9Z5QYUpm3tE6CJjTxmFFNz2do5LnDNF8uwjXl4/im4uwpFvblr+p60lXd6fqdFZSCJj+gBAAzi8vKcGk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=qgwWOBsD; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="qgwWOBsD" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7C137C4CEE9; Wed, 26 Feb 2025 21:37:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1740605859; bh=crXP1Ouatdf2x6aP5TkGMgQuZwKDhYLTGhBQaqUk7As=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=qgwWOBsDqsKj3ZBnp35cBQ7FdHOS84pzSm231/5Ou4CQ+rROC72Pp8Z6Om+8gxYaw KalWXo5VBukzPMfvo6WtBHE5tNxxxo04FzqAZAAWfmsfYCZW1y1vpOThzKygdcrITr RnYcGWR7PqkkUr3eMhUpdPFamfb1qmXuNjHAGCrdpT5rvuO0jNdtCty8UHSom4fLIz rguJ1Dikbte4is6ntnkrYQ5qcmyFKopJnAzRD154sXixjxOK0dxxEbPBIJ/oi03nWg kube8TLQuOfFSnPqzHMDqNo+nWZm7EJnL5dIejIegrCM/QibL1SxmjJrdRkYzPYQkj 701gdXe3qMTzw== From: Arnd Bergmann To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Arnd Bergmann , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Linus Torvalds , Andy Shevchenko , Matthew Wilcox Subject: [PATCH v3 02/10] x86: drop 32-bit "bigsmp" machine support Date: Wed, 26 Feb 2025 22:37:06 +0100 Message-Id: <20250226213714.4040853-3-arnd@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250226213714.4040853-1-arnd@kernel.org> References: <20250226213714.4040853-1-arnd@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Arnd Bergmann The x86-32 kernel used to support multiple platforms with more than eight logical CPUs, from the 1999-2003 timeframe: Sequent NUMA-Q, IBM Summit, Unisys ES7000 and HP F8. Support for all except the latter was dropped back in 2014, leaving only the F8 based DL740 and DL760 G2 machines in this catery, with up to eight single-core Socket-603 Xeon-MP processors with hyperthreading. Like the already removed machines, the HP F8 servers at the cost upwards of $100k in typical configurations, but were quickly obsoleted by their 64-bit Socket-604 cousins and the AMD Opteron. Earlier servers with up to 8 Pentium Pro or Xeon processors remain fully supported as they had no hyperthreading. Similarly, the more common 4-socket Xeon-MP machines with hyperthreading using Intel or ServerWorks chipsets continue to work without this, and all the multi-core Xeon processors also run 64-bit kernels. While the "bigsmp" support can also be used to run on later 64-bit machines (including VM guests), it seems best to discourage that and get any remaining users to update their kernels to 64-bit builds on these. As a side-effect of this, there is also no more need to support NUMA configurations on 32-bit x86, as all true 32-bit NUMA platforms are already gone. Signed-off-by: Arnd Bergmann --- .../admin-guide/kernel-parameters.txt | 4 - arch/x86/Kconfig | 20 +--- arch/x86/kernel/apic/Makefile | 3 - arch/x86/kernel/apic/apic.c | 3 - arch/x86/kernel/apic/bigsmp_32.c | 105 ------------------ arch/x86/kernel/apic/local.h | 13 --- arch/x86/kernel/apic/probe_32.c | 29 ----- 7 files changed, 4 insertions(+), 173 deletions(-) delete mode 100644 arch/x86/kernel/apic/bigsmp_32.c diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentatio= n/admin-guide/kernel-parameters.txt index fb8752b42ec8..8f923770a566 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -416,10 +416,6 @@ Format: { quiet (default) | verbose | debug } Change the amount of debugging information output when initialising the APIC and IO-APIC components. - For X86-32, this can also be used to specify an APIC - driver name. - Format: apic=3Ddriver_name - Examples: apic=3Dbigsmp =20 apic_extnmi=3D [APIC,X86,EARLY] External NMI delivery setting Format: { bsp (default) | all | none } diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 87198d957e2f..4a1205b22ae2 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -530,12 +530,6 @@ config X86_FRED ring transitions and exception/interrupt handling if the system supports it. =20 -config X86_BIGSMP - bool "Support for big SMP systems with more than 8 CPUs" - depends on SMP && X86_32 - help - This option is needed for the systems that have more than 8 CPUs. - config X86_EXTENDED_PLATFORM bool "Support for extended (non-PC) x86 platforms" default y @@ -734,8 +728,8 @@ config X86_32_NON_STANDARD depends on X86_32 && SMP depends on X86_EXTENDED_PLATFORM help - This option compiles in the bigsmp and STA2X11 default - subarchitectures. It is intended for a generic binary + This option compiles in the STA2X11 default + subarchitecture. It is intended for a generic binary kernel. If you select them all, kernel will probe it one by one and will fallback to default. =20 @@ -1012,8 +1006,7 @@ config NR_CPUS_RANGE_BEGIN config NR_CPUS_RANGE_END int depends on X86_32 - default 64 if SMP && X86_BIGSMP - default 8 if SMP && !X86_BIGSMP + default 8 if SMP default 1 if !SMP =20 config NR_CPUS_RANGE_END @@ -1026,7 +1019,6 @@ config NR_CPUS_RANGE_END config NR_CPUS_DEFAULT int depends on X86_32 - default 32 if X86_BIGSMP default 8 if SMP default 1 if !SMP =20 @@ -1573,8 +1565,7 @@ config AMD_MEM_ENCRYPT config NUMA bool "NUMA Memory Allocation and Scheduler Support" depends on SMP - depends on X86_64 || (X86_32 && HIGHMEM64G && X86_BIGSMP) - default y if X86_BIGSMP + depends on X86_64 select USE_PERCPU_NUMA_NODE_ID select OF_NUMA if OF help @@ -1587,9 +1578,6 @@ config NUMA For 64-bit this is recommended if the system is Intel Core i7 (or later), AMD Opteron, or EM64T NUMA. =20 - For 32-bit this is only needed if you boot a 32-bit - kernel on a 64-bit NUMA platform. - Otherwise, you should say N. =20 config AMD_NUMA diff --git a/arch/x86/kernel/apic/Makefile b/arch/x86/kernel/apic/Makefile index 3bf0487cf3b7..52d1808ee360 100644 --- a/arch/x86/kernel/apic/Makefile +++ b/arch/x86/kernel/apic/Makefile @@ -23,8 +23,5 @@ obj-$(CONFIG_X86_X2APIC) +=3D x2apic_cluster.o obj-y +=3D apic_flat_64.o endif =20 -# APIC probe will depend on the listing order here -obj-$(CONFIG_X86_BIGSMP) +=3D bigsmp_32.o - # For 32bit, probe_32 need to be listed last obj-$(CONFIG_X86_LOCAL_APIC) +=3D probe_$(BITS).o diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c index e893dc6f11c1..ddca8da6d468 100644 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -1371,8 +1371,6 @@ void __init apic_intr_mode_init(void) =20 x86_64_probe_apic(); =20 - x86_32_install_bigsmp(); - if (x86_platform.apic_post_init) x86_platform.apic_post_init(); =20 @@ -1674,7 +1672,6 @@ static __init void apic_read_boot_cpu_id(bool x2apic) boot_cpu_apic_version =3D GET_APIC_VERSION(apic_read(APIC_LVR)); } topology_register_boot_apic(boot_cpu_physical_apicid); - x86_32_probe_bigsmp_early(); } =20 #ifdef CONFIG_X86_X2APIC diff --git a/arch/x86/kernel/apic/bigsmp_32.c b/arch/x86/kernel/apic/bigsmp= _32.c deleted file mode 100644 index 9285d500d5b4..000000000000 --- a/arch/x86/kernel/apic/bigsmp_32.c +++ /dev/null @@ -1,105 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * APIC driver for "bigsmp" xAPIC machines with more than 8 virtual CPUs. - * - * Drives the local APIC in "clustered mode". - */ -#include -#include -#include - -#include -#include - -#include "local.h" - -static u32 bigsmp_get_apic_id(u32 x) -{ - return (x >> 24) & 0xFF; -} - -static void bigsmp_send_IPI_allbutself(int vector) -{ - default_send_IPI_mask_allbutself_phys(cpu_online_mask, vector); -} - -static void bigsmp_send_IPI_all(int vector) -{ - default_send_IPI_mask_sequence_phys(cpu_online_mask, vector); -} - -static int dmi_bigsmp; /* can be set by dmi scanners */ - -static int hp_ht_bigsmp(const struct dmi_system_id *d) -{ - printk(KERN_NOTICE "%s detected: force use of apic=3Dbigsmp\n", d->ident); - dmi_bigsmp =3D 1; - - return 0; -} - - -static const struct dmi_system_id bigsmp_dmi_table[] =3D { - { hp_ht_bigsmp, "HP ProLiant DL760 G2", - { DMI_MATCH(DMI_BIOS_VENDOR, "HP"), - DMI_MATCH(DMI_BIOS_VERSION, "P44-"), - } - }, - - { hp_ht_bigsmp, "HP ProLiant DL740", - { DMI_MATCH(DMI_BIOS_VENDOR, "HP"), - DMI_MATCH(DMI_BIOS_VERSION, "P47-"), - } - }, - { } /* NULL entry stops DMI scanning */ -}; - -static int probe_bigsmp(void) -{ - return dmi_check_system(bigsmp_dmi_table); -} - -static struct apic apic_bigsmp __ro_after_init =3D { - - .name =3D "bigsmp", - .probe =3D probe_bigsmp, - - .dest_mode_logical =3D false, - - .disable_esr =3D 1, - - .cpu_present_to_apicid =3D default_cpu_present_to_apicid, - - .max_apic_id =3D 0xFE, - .get_apic_id =3D bigsmp_get_apic_id, - - .calc_dest_apicid =3D apic_default_calc_apicid, - - .send_IPI =3D default_send_IPI_single_phys, - .send_IPI_mask =3D default_send_IPI_mask_sequence_phys, - .send_IPI_mask_allbutself =3D NULL, - .send_IPI_allbutself =3D bigsmp_send_IPI_allbutself, - .send_IPI_all =3D bigsmp_send_IPI_all, - .send_IPI_self =3D default_send_IPI_self, - - .read =3D native_apic_mem_read, - .write =3D native_apic_mem_write, - .eoi =3D native_apic_mem_eoi, - .icr_read =3D native_apic_icr_read, - .icr_write =3D native_apic_icr_write, - .wait_icr_idle =3D apic_mem_wait_icr_idle, - .safe_wait_icr_idle =3D apic_mem_wait_icr_idle_timeout, -}; - -bool __init apic_bigsmp_possible(bool cmdline_override) -{ - return apic =3D=3D &apic_bigsmp || !cmdline_override; -} - -void __init apic_bigsmp_force(void) -{ - if (apic !=3D &apic_bigsmp) - apic_install_driver(&apic_bigsmp); -} - -apic_driver(apic_bigsmp); diff --git a/arch/x86/kernel/apic/local.h b/arch/x86/kernel/apic/local.h index 842fe28496be..bdcf609eb283 100644 --- a/arch/x86/kernel/apic/local.h +++ b/arch/x86/kernel/apic/local.h @@ -65,17 +65,4 @@ void default_send_IPI_self(int vector); void default_send_IPI_mask_sequence_logical(const struct cpumask *mask, in= t vector); void default_send_IPI_mask_allbutself_logical(const struct cpumask *mask, = int vector); void default_send_IPI_mask_logical(const struct cpumask *mask, int vector); -void x86_32_probe_bigsmp_early(void); -void x86_32_install_bigsmp(void); -#else -static inline void x86_32_probe_bigsmp_early(void) { } -static inline void x86_32_install_bigsmp(void) { } -#endif - -#ifdef CONFIG_X86_BIGSMP -bool apic_bigsmp_possible(bool cmdline_selected); -void apic_bigsmp_force(void); -#else -static inline bool apic_bigsmp_possible(bool cmdline_selected) { return fa= lse; }; -static inline void apic_bigsmp_force(void) { } #endif diff --git a/arch/x86/kernel/apic/probe_32.c b/arch/x86/kernel/apic/probe_3= 2.c index f75ee345c02d..87bc9e7ca5d6 100644 --- a/arch/x86/kernel/apic/probe_32.c +++ b/arch/x86/kernel/apic/probe_32.c @@ -93,35 +93,6 @@ static int __init parse_apic(char *arg) } early_param("apic", parse_apic); =20 -void __init x86_32_probe_bigsmp_early(void) -{ - if (nr_cpu_ids <=3D 8 || xen_pv_domain()) - return; - - if (IS_ENABLED(CONFIG_X86_BIGSMP)) { - switch (boot_cpu_data.x86_vendor) { - case X86_VENDOR_INTEL: - if (!APIC_XAPIC(boot_cpu_apic_version)) - break; - /* P4 and above */ - fallthrough; - case X86_VENDOR_HYGON: - case X86_VENDOR_AMD: - if (apic_bigsmp_possible(cmdline_apic)) - return; - break; - } - } - pr_info("Limiting to 8 possible CPUs\n"); - set_nr_cpu_ids(8); -} - -void __init x86_32_install_bigsmp(void) -{ - if (nr_cpu_ids > 8 && !xen_pv_domain()) - apic_bigsmp_force(); -} - void __init x86_32_probe_apic(void) { if (!cmdline_apic) { --=20 2.39.5 From nobody Wed Dec 17 12:43:44 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B81BF25E44D for ; Wed, 26 Feb 2025 21:37:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740605862; cv=none; b=XW3XwBZu5t0QTfWMCbFP3zPOnSK6esZQGC2Rwdcg893mfwNj7tE07E1efZaMI7XPv2RpQi77M8XhCD7mcsglYH9WETNCBK+othPoC78c2p5pSfjaOvDrBGPRZK84v+FxXRfBP+RHW6uhK2MsYsvfoMMPtKwVtCbgVTVB4WIanDw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740605862; c=relaxed/simple; bh=RaOxny5lKPwI/fcP9pPId4nMHRz9abskR9v27E849o0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=X6c2T9zQWLZuKdTPla16IStQ08ZGak990FyNCszQs5i3mlt9cXNG3vRas0kVemsIRFhtYPI7GGxRbSrefInN3uobRQbUqgTpv1uOqFGsrXYI8tlHLf/bbwpDlIok0JKUb0y5FH/2AcgKPKXKkYRpGyj608stgy+AKchgbPDdhDk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=DPqlmb5O; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="DPqlmb5O" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0F841C4CEE7; Wed, 26 Feb 2025 21:37:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1740605862; bh=RaOxny5lKPwI/fcP9pPId4nMHRz9abskR9v27E849o0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=DPqlmb5Ov4QvzzT94sMlm6XJr3zvIyGmtGgPZGAAwlH45fIi7Jf7e+Q7SlmeqOCgu 8Njdzr4sMmgfrqKOLpjPo169U+dgi4T4nL91zFZkuNzGXBxy83x92ZkRneYiwLp+9H GOmneWRVCSsQW0ruPxPi5/JhgYseEeBnF4mfWFuxM2G+NkK3ihEa1e2zFcFkHKnvtr n5xcJ5gDw+9oPDWBRYmJPKoghlhFEAJzZR6agxFFc14xTGe5JQZ3/ztcECREOua1MP XoddDnxa9MQSiuklka1agypZdiZW1i895PkLH2ahEzHVMweUjnVIIhY6fqKT39nvn4 kbzPGBuL8AUOQ== From: Arnd Bergmann To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Arnd Bergmann , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Linus Torvalds , Andy Shevchenko , Matthew Wilcox Subject: [PATCH v3 03/10] x86: rework CONFIG_GENERIC_CPU compiler flags Date: Wed, 26 Feb 2025 22:37:07 +0100 Message-Id: <20250226213714.4040853-4-arnd@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250226213714.4040853-1-arnd@kernel.org> References: <20250226213714.4040853-1-arnd@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Arnd Bergmann Building an x86-64 kernel with CONFIG_GENERIC_CPU is documented to run on all CPUs, but the Makefile does not actually pass an -march=3D argument, instead relying on the default that was used to configure the toolchain. In many cases, gcc will be configured to -march=3Dx86-64 or -march=3Dk8 for maximum compatibility, but in other cases a distribution default may be either raised to a more recent ISA, or set to -march=3Dnative to build for the CPU used for compilation. This still works in the case of building a custom kernel for the local machine. The point where it breaks down is building a kernel for another machine that is older the the default target. Changing the default to -march=3Dx86-64 would make it work reliable, but possibly produce worse code on distros that intentionally default to a newer ISA. To allow reliably building a kernel for either the oldest x86-64 CPUs, pass the -march=3Dx86-64 flag to the compiler. This was not possible in early versions of x86-64 gcc, but works on all currently supported versions down to at least gcc-5. Signed-off-by: Arnd Bergmann --- arch/x86/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/Makefile b/arch/x86/Makefile index 5b773b34768d..5af3172fd51c 100644 --- a/arch/x86/Makefile +++ b/arch/x86/Makefile @@ -183,14 +183,14 @@ else cflags-$(CONFIG_MPSC) +=3D -march=3Dnocona cflags-$(CONFIG_MCORE2) +=3D -march=3Dcore2 cflags-$(CONFIG_MATOM) +=3D -march=3Datom - cflags-$(CONFIG_GENERIC_CPU) +=3D -mtune=3Dgeneric + cflags-$(CONFIG_GENERIC_CPU) +=3D -march=3Dx86-64 -mtune=3Dgeneric KBUILD_CFLAGS +=3D $(cflags-y) =20 rustflags-$(CONFIG_MK8) +=3D -Ctarget-cpu=3Dk8 rustflags-$(CONFIG_MPSC) +=3D -Ctarget-cpu=3Dnocona rustflags-$(CONFIG_MCORE2) +=3D -Ctarget-cpu=3Dcore2 rustflags-$(CONFIG_MATOM) +=3D -Ctarget-cpu=3Datom - rustflags-$(CONFIG_GENERIC_CPU) +=3D -Ztune-cpu=3Dgeneric + rustflags-$(CONFIG_GENERIC_CPU) +=3D -Ctarget-cpu=3Dx86-64 -Ztune-= cpu=3Dgeneric KBUILD_RUSTFLAGS +=3D $(rustflags-y) =20 KBUILD_CFLAGS +=3D -mno-red-zone --=20 2.39.5 From nobody Wed Dec 17 12:43:44 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3D4A025E463 for ; Wed, 26 Feb 2025 21:37:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740605865; cv=none; b=Q6+3BvV8voF+cirprOZVjt7MEOFnN8yIIS0gC1w/qOMLHM6XzPqVJnJKXyNXHq/cjuSDOIY9eXyCfUJoG2k18v92o5Wq4xz6vMp+6veE/0FtFkPwYBl5dvHDwALazK3mPBHqir++iowx9yJChyrg+Q9JxSl3RqTpb7q2R8SmzGo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740605865; c=relaxed/simple; bh=rrTm035FMZ6jPcTCYgwd6AAGCEWqVHAjB1QvrC4DWjE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=mF1YVYSecBxmHgQ0K92dyOY5Q6xt989XCEn+x94okmuap/vJ68NaqGLEtUjAPhYnyTKT/c/UPhqdurM+mTQqYwaNR2emlCn+Nfw/p0R3/TUjopV4H5HOSYL6UIyp44k++1kMxRRCJBpkZI5eP5crlJw+AssAMiLCxabcmxfmAu8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=V3fKPcOj; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="V3fKPcOj" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 98B21C4CEE9; Wed, 26 Feb 2025 21:37:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1740605864; bh=rrTm035FMZ6jPcTCYgwd6AAGCEWqVHAjB1QvrC4DWjE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=V3fKPcOjKogVK4gBBKFHMO2WLh74W3RVRSnVdc+bdvdJpATMlYYd9S7xPEgMQ5jLe Lpe4C7WNQ3RAqv66yuMj8R2/k5wx1ZeW1M3yTKmFkzraX3+wcbXmyVN4I39jBxS3aI c56QCmvjXE2FU+ZGij6amDF2uGZTA3xERdMKr4rzXK6i8xg7krBQOgmhT8VTLW/+2k 7tmJoM3s95WSaapRJGNF1SAsP8BruASufkMGMc/PSU2Px7D0OqK4hQBEhecUgrSR7T XOw60kvaMUdg5UzMebyUKNu0mjJwhnejMt8EDSqE5PjgHosznqpjsVkXX2w84F2czA TGkovoY30+cGA== From: Arnd Bergmann To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Arnd Bergmann , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Linus Torvalds , Andy Shevchenko , Matthew Wilcox Subject: [PATCH v3 04/10] x86: drop configuration options for early 64-bit CPUs Date: Wed, 26 Feb 2025 22:37:08 +0100 Message-Id: <20250226213714.4040853-5-arnd@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250226213714.4040853-1-arnd@kernel.org> References: <20250226213714.4040853-1-arnd@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Arnd Bergmann The x86 CPU selection menu is confusing for a number of reasons: When configuring 32-bit kernels, it shows a small number of early 64-bit microarchitectures (K8, Core 2) but not the regular generic 64-bit target that is the normal default. There is no longer a reason to run 32-bit kernels on production 64-bit systems, so only actual 32-bit CPUs need to be shown here. When configuring 64-bit kernels, the options also pointless as there is no way to pick any CPU from the past 15 years, leaving GENERIC_CPU as the only sensible choice. Address both of the above by removing the obsolete options and making all 64-bit kernels run on both Intel and AMD CPUs from any generation. Testing generic 32-bit kernels on 64-bit hardware remains possible, just not building a 32-bit kernel that requires a 64-bit CPU. Signed-off-by: Arnd Bergmann --- arch/x86/Kconfig.cpu | 95 +++++---------------------------- arch/x86/Makefile | 16 +----- arch/x86/Makefile_32.cpu | 5 +- arch/x86/include/asm/vermagic.h | 4 -- drivers/misc/mei/Kconfig | 2 +- 5 files changed, 18 insertions(+), 104 deletions(-) diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu index 42e6a40876ea..8fcb8ccee44b 100644 --- a/arch/x86/Kconfig.cpu +++ b/arch/x86/Kconfig.cpu @@ -1,9 +1,9 @@ # SPDX-License-Identifier: GPL-2.0 # Put here option for CPU selection and depending optimization choice - prompt "Processor family" - default M686 if X86_32 - default GENERIC_CPU if X86_64 + prompt "x86-32 Processor family" + depends on X86_32 + default M686 help This is the processor type of your CPU. This information is used for optimizing purposes. In order to compile a kernel @@ -31,7 +31,6 @@ choice - "Pentium-4" for the Intel Pentium 4 or P4-based Celeron. - "K6" for the AMD K6, K6-II and K6-III (aka K6-3D). - "Athlon" for the AMD K7 family (Athlon/Duron/Thunderbird). - - "Opteron/Athlon64/Hammer/K8" for all K8 and newer AMD CPUs. - "Crusoe" for the Transmeta Crusoe series. - "Efficeon" for the Transmeta Efficeon series. - "Winchip-C6" for original IDT Winchip. @@ -42,13 +41,10 @@ choice - "CyrixIII/VIA C3" for VIA Cyrix III or VIA C3. - "VIA C3-2" for VIA C3-2 "Nehemiah" (model 9 and above). - "VIA C7" for VIA C7. - - "Intel P4" for the Pentium 4/Netburst microarchitecture. - - "Core 2/newer Xeon" for all core2 and newer Intel CPUs. - "Intel Atom" for the Atom-microarchitecture CPUs. - - "Generic-x86-64" for a kernel which runs on any x86-64 CPU. =20 See each option's help text for additional details. If you don't know - what to do, choose "486". + what to do, choose "Pentium-Pro". =20 config M486SX bool "486SX" @@ -114,11 +110,11 @@ config MPENTIUMIII extensions. =20 config MPENTIUMM - bool "Pentium M" + bool "Pentium M/Pentium Dual Core/Core Solo/Core Duo" depends on X86_32 help Select this for Intel Pentium M (not Pentium-4 M) - notebook chips. + "Merom" Core Solo/Duo notebook chips =20 config MPENTIUM4 bool "Pentium-4/Celeron(P4-based)/Pentium-4 M/older Xeon" @@ -139,22 +135,10 @@ config MPENTIUM4 -Mobile Pentium 4 -Mobile Pentium 4 M -Extreme Edition (Gallatin) - -Prescott - -Prescott 2M - -Cedar Mill - -Presler - -Smithfiled Xeons (Intel Xeon, Xeon MP, Xeon LV, Xeon MV) corename: -Foster -Prestonia -Gallatin - -Nocona - -Irwindale - -Cranford - -Potomac - -Paxville - -Dempsey - =20 config MK6 bool "K6/K6-II/K6-III" @@ -172,13 +156,6 @@ config MK7 some extended instructions, and passes appropriate optimization flags to GCC. =20 -config MK8 - bool "Opteron/Athlon64/Hammer/K8" - help - Select this for an AMD Opteron or Athlon64 Hammer-family processor. - Enables use of some extended instructions, and passes appropriate - optimization flags to GCC. - config MCRUSOE bool "Crusoe" depends on X86_32 @@ -258,42 +235,14 @@ config MVIAC7 Select this for a VIA C7. Selecting this uses the correct cache shift and tells gcc to treat the CPU as a 686. =20 -config MPSC - bool "Intel P4 / older Netburst based Xeon" - depends on X86_64 - help - Optimize for Intel Pentium 4, Pentium D and older Nocona/Dempsey - Xeon CPUs with Intel 64bit which is compatible with x86-64. - Note that the latest Xeons (Xeon 51xx and 53xx) are not based on the - Netburst core and shouldn't use this option. You can distinguish them - using the cpu family field - in /proc/cpuinfo. Family 15 is an older Xeon, Family 6 a newer one. - -config MCORE2 - bool "Core 2/newer Xeon" - help - - Select this for Intel Core 2 and newer Core 2 Xeons (Xeon 51xx and - 53xx) CPUs. You can distinguish newer from older Xeons by the CPU - family in /proc/cpuinfo. Newer ones have 6 and older ones 15 - (not a typo) - config MATOM bool "Intel Atom" help - Select this for the Intel Atom platform. Intel Atom CPUs have an in-order pipelining architecture and thus can benefit from accordingly optimized code. Use a recent GCC with specific Atom support in order to fully benefit from selecting this option. =20 -config GENERIC_CPU - bool "Generic-x86-64" - depends on X86_64 - help - Generic x86-64 CPU. - Run equally well on all x86-64 CPUs. - endchoice =20 config X86_GENERIC @@ -317,8 +266,8 @@ config X86_INTERNODE_CACHE_SHIFT =20 config X86_L1_CACHE_SHIFT int - default "7" if MPENTIUM4 || MPSC - default "6" if MK7 || MK8 || MPENTIUMM || MCORE2 || MATOM || MVIAC7 || X8= 6_GENERIC || GENERIC_CPU + default "7" if MPENTIUM4 + default "6" if MK7 || MPENTIUMM || MATOM || MVIAC7 || X86_GENERIC || X86_= 64 default "4" if MELAN || M486SX || M486 || MGEODEGX1 default "5" if MWINCHIP3D || MWINCHIPC6 || MCRUSOE || MEFFICEON || MCYRIX= III || MK6 || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || M5= 86 || MVIAC3_2 || MGEODE_LX =20 @@ -336,35 +285,19 @@ config X86_ALIGNMENT_16 =20 config X86_INTEL_USERCOPY def_bool y - depends on MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M586MMX= || X86_GENERIC || MK8 || MK7 || MEFFICEON || MCORE2 + depends on MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M586MMX= || X86_GENERIC || MK7 || MEFFICEON =20 config X86_USE_PPRO_CHECKSUM def_bool y - depends on MWINCHIP3D || MWINCHIPC6 || MCYRIXIII || MK7 || MK6 || MPENTIU= M4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MK8 || MVIAC3_2 || = MVIAC7 || MEFFICEON || MGEODE_LX || MCORE2 || MATOM - -# -# P6_NOPs are a relatively minor optimization that require a family >=3D -# 6 processor, except that it is broken on certain VIA chips. -# Furthermore, AMD chips prefer a totally different sequence of NOPs -# (which work on all CPUs). In addition, it looks like Virtual PC -# does not understand them. -# -# As a result, disallow these if we're not compiling for X86_64 (these -# NOPs do work on all x86-64 capable chips); the list of processors in -# the right-hand clause are the cores that benefit from this optimization. -# -config X86_P6_NOP - def_bool y - depends on X86_64 - depends on (MCORE2 || MPENTIUM4 || MPSC) + depends on MWINCHIP3D || MWINCHIPC6 || MCYRIXIII || MK7 || MK6 || MPENTIU= M4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7 = || MEFFICEON || MGEODE_LX || MATOM =20 config X86_TSC def_bool y - depends on (MWINCHIP3D || MCRUSOE || MEFFICEON || MCYRIXIII || MK7 || MK6= || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX = || M586TSC || MK8 || MVIAC3_2 || MVIAC7 || MGEODEGX1 || MGEODE_LX || MCORE2= || MATOM) || X86_64 + depends on (MWINCHIP3D || MCRUSOE || MEFFICEON || MCYRIXIII || MK7 || MK6= || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX = || M586TSC || MVIAC3_2 || MVIAC7 || MGEODEGX1 || MGEODE_LX || MATOM) || X86= _64 =20 config X86_HAVE_PAE def_bool y - depends on MCRUSOE || MEFFICEON || MCYRIXIII || MPENTIUM4 || MPENTIUMM ||= MPENTIUMIII || MPENTIUMII || M686 || MK8 || MVIAC7 || MCORE2 || MATOM || X= 86_64 + depends on MCRUSOE || MEFFICEON || MCYRIXIII || MPENTIUM4 || MPENTIUMM ||= MPENTIUMIII || MPENTIUMII || M686 || MVIAC7 || MATOM || X86_64 =20 config X86_CMPXCHG64 def_bool y @@ -374,12 +307,12 @@ config X86_CMPXCHG64 # generates cmov. config X86_CMOV def_bool y - depends on (MK8 || MK7 || MCORE2 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII= || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7 || MCRUSOE || MEFFICEON || X86= _64 || MATOM || MGEODE_LX) + depends on (MK7 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII ||= M686 || MVIAC3_2 || MVIAC7 || MCRUSOE || MEFFICEON || MATOM || MGEODE_LX |= | X86_64) =20 config X86_MINIMUM_CPU_FAMILY int default "64" if X86_64 - default "6" if X86_32 && (MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTI= UMII || M686 || MVIAC3_2 || MVIAC7 || MEFFICEON || MATOM || MCORE2 || MK7 |= | MK8) + default "6" if X86_32 && (MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTI= UMII || M686 || MVIAC3_2 || MVIAC7 || MEFFICEON || MATOM || MK7) default "5" if X86_32 && X86_CMPXCHG64 default "4" =20 diff --git a/arch/x86/Makefile b/arch/x86/Makefile index 5af3172fd51c..8120085b00a4 100644 --- a/arch/x86/Makefile +++ b/arch/x86/Makefile @@ -178,20 +178,8 @@ else # Use -mskip-rax-setup if supported. KBUILD_CFLAGS +=3D $(call cc-option,-mskip-rax-setup) =20 - # FIXME - should be integrated in Makefile.cpu (Makefile_32.cpu) - cflags-$(CONFIG_MK8) +=3D -march=3Dk8 - cflags-$(CONFIG_MPSC) +=3D -march=3Dnocona - cflags-$(CONFIG_MCORE2) +=3D -march=3Dcore2 - cflags-$(CONFIG_MATOM) +=3D -march=3Datom - cflags-$(CONFIG_GENERIC_CPU) +=3D -march=3Dx86-64 -mtune=3Dgeneric - KBUILD_CFLAGS +=3D $(cflags-y) - - rustflags-$(CONFIG_MK8) +=3D -Ctarget-cpu=3Dk8 - rustflags-$(CONFIG_MPSC) +=3D -Ctarget-cpu=3Dnocona - rustflags-$(CONFIG_MCORE2) +=3D -Ctarget-cpu=3Dcore2 - rustflags-$(CONFIG_MATOM) +=3D -Ctarget-cpu=3Datom - rustflags-$(CONFIG_GENERIC_CPU) +=3D -Ctarget-cpu=3Dx86-64 -Ztune-= cpu=3Dgeneric - KBUILD_RUSTFLAGS +=3D $(rustflags-y) + KBUILD_CFLAGS +=3D -march=3Dx86-64 -mtune=3Dgeneric + KBUILD_RUSTFLAGS +=3D -Ctarget-cpu=3Dx86-64 -Ztune-cpu=3Dgeneric =20 KBUILD_CFLAGS +=3D -mno-red-zone KBUILD_CFLAGS +=3D -mcmodel=3Dkernel diff --git a/arch/x86/Makefile_32.cpu b/arch/x86/Makefile_32.cpu index 94834c4b5e5e..af7de9a42752 100644 --- a/arch/x86/Makefile_32.cpu +++ b/arch/x86/Makefile_32.cpu @@ -24,7 +24,6 @@ cflags-$(CONFIG_MK6) +=3D -march=3Dk6 # Please note, that patches that add -march=3Dathlon-xp and friends are po= intless. # They make zero difference whatsosever to performance at this time. cflags-$(CONFIG_MK7) +=3D -march=3Dathlon -cflags-$(CONFIG_MK8) +=3D $(call cc-option,-march=3Dk8,-march=3Dathlon) cflags-$(CONFIG_MCRUSOE) +=3D -march=3Di686 $(align) cflags-$(CONFIG_MEFFICEON) +=3D -march=3Di686 $(call tune,pentium3) $(alig= n) cflags-$(CONFIG_MWINCHIPC6) +=3D $(call cc-option,-march=3Dwinchip-c6,-mar= ch=3Di586) @@ -32,9 +31,7 @@ cflags-$(CONFIG_MWINCHIP3D) +=3D $(call cc-option,-march= =3Dwinchip2,-march=3Di586) cflags-$(CONFIG_MCYRIXIII) +=3D $(call cc-option,-march=3Dc3,-march=3Di486= ) $(align) cflags-$(CONFIG_MVIAC3_2) +=3D $(call cc-option,-march=3Dc3-2,-march=3Di68= 6) cflags-$(CONFIG_MVIAC7) +=3D -march=3Di686 -cflags-$(CONFIG_MCORE2) +=3D -march=3Di686 $(call tune,core2) -cflags-$(CONFIG_MATOM) +=3D $(call cc-option,-march=3Datom,$(call cc-opti= on,-march=3Dcore2,-march=3Di686)) \ - $(call cc-option,-mtune=3Datom,$(call cc-option,-mtune=3Dgeneric)) +cflags-$(CONFIG_MATOM) +=3D -march=3Datom =20 # AMD Elan support cflags-$(CONFIG_MELAN) +=3D -march=3Di486 diff --git a/arch/x86/include/asm/vermagic.h b/arch/x86/include/asm/vermagi= c.h index 75884d2cdec3..5d471253c755 100644 --- a/arch/x86/include/asm/vermagic.h +++ b/arch/x86/include/asm/vermagic.h @@ -15,8 +15,6 @@ #define MODULE_PROC_FAMILY "586TSC " #elif defined CONFIG_M586MMX #define MODULE_PROC_FAMILY "586MMX " -#elif defined CONFIG_MCORE2 -#define MODULE_PROC_FAMILY "CORE2 " #elif defined CONFIG_MATOM #define MODULE_PROC_FAMILY "ATOM " #elif defined CONFIG_M686 @@ -33,8 +31,6 @@ #define MODULE_PROC_FAMILY "K6 " #elif defined CONFIG_MK7 #define MODULE_PROC_FAMILY "K7 " -#elif defined CONFIG_MK8 -#define MODULE_PROC_FAMILY "K8 " #elif defined CONFIG_MELAN #define MODULE_PROC_FAMILY "ELAN " #elif defined CONFIG_MCRUSOE diff --git a/drivers/misc/mei/Kconfig b/drivers/misc/mei/Kconfig index 67d9391f1855..7575fee96cc6 100644 --- a/drivers/misc/mei/Kconfig +++ b/drivers/misc/mei/Kconfig @@ -3,7 +3,7 @@ config INTEL_MEI tristate "Intel Management Engine Interface" depends on X86 && PCI - default GENERIC_CPU || MCORE2 || MATOM || X86_GENERIC + default X86_64 || MATOM help The Intel Management Engine (Intel ME) provides Manageability, Security and Media services for system containing Intel chipsets. --=20 2.39.5 From nobody Wed Dec 17 12:43:44 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CE935260A55 for ; Wed, 26 Feb 2025 21:37:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740605867; cv=none; b=UfAtw92XkxzutjiOQoX+15TVN0qU2L6t/nJ9SJk7gMojx0m9dtQ5RY/9cQO2S7NMpIqJGv7snVeDaOpTKQeGPtAYwR1T7WTE38+ZCwoU1YVk/XnUMTACLI7vZtX0txAXqUWlFKZILWc8tf12+Zi8ojqoAhWSTXIyYk94alz1Tm8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740605867; c=relaxed/simple; bh=L5R9ym4W6KQoLLxPMTgtV+YOFfYlUcuMTifad91/4Q0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=RLEiicQtmtL/1qVfvYd8sXr234oDk840HQXQ8034UhrSn4KR/Mt5LKTVXUJYjcJuCXLjMjAKpBALKWWMcACHAuRuvjyrhq/J3yQmnzgPdIOhM/L5385xal9MgLMZQ9P0tIycMdAyTR2Z/duM5hpvMLKX4Hl+s6Tvh/hRcJJ7KQU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=i4b4JSnI; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="i4b4JSnI" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2FC35C4CEE8; Wed, 26 Feb 2025 21:37:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1740605867; bh=L5R9ym4W6KQoLLxPMTgtV+YOFfYlUcuMTifad91/4Q0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=i4b4JSnIxfaJP4xyENOWtiSHJTfaOcwN7pdGqH+Xp47F3jUyEfF7yXN7XUw0CP7w9 a6aaSBhTlZD5ozvPDPy4I/5HlYvJTkBQNgkxm0CnBklDxJp3BRMziGnFeYDp+8oz+1 j46o3IUe2r5BHEQqoq9DVMQ3BiT5yojPh4tN2oRC0+TJkKmt4W9tyVC6KDvaGtz9hc IKYgzSE8laaTNJ0BascfPuR4D+vcqumhtj6i9Xy4sgpo+f0TLQVXQCaAL304ga2cgg EEitR97I2bPMBa1EtSw7/2Lc60O0UecrY+bFOMbzZ+X019GKAXywtUUkZTr2z5rxmO 6Q4U9RDqwWh8g== From: Arnd Bergmann To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Arnd Bergmann , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Linus Torvalds , Andy Shevchenko , Matthew Wilcox Subject: [PATCH v3 05/10] x86: remove HIGHMEM64G support Date: Wed, 26 Feb 2025 22:37:09 +0100 Message-Id: <20250226213714.4040853-6-arnd@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250226213714.4040853-1-arnd@kernel.org> References: <20250226213714.4040853-1-arnd@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Arnd Bergmann The HIGHMEM64G support was added in linux-2.3.25 to support (then) high-end Pentium Pro and Pentium III Xeon servers with more than 4GB of addressing, NUMA and PCI-X slots started appearing. I have found no evidence of this ever being used in regular dual-socket servers or consumer devices, all the users seem obsolete these days, even by i386 standards: - Support for NUMA servers (NUMA-Q, IBM x440, unisys) was already removed ten years ago. - 4+ socket non-NUMA servers based on Intel 450GX/450NX, HP F8 and ServerWorks ServerSet/GrandChampion could theoretically still work with 8GB, but these were exceptionally rare even 20 years ago and would have usually been equipped with than the maximum amount of RAM. - Some SKUs of the Celeron D from 2004 had 64-bit mode fused off but could still work in a Socket 775 mainboard designed for the later Core 2 Duo and 8GB. Apparently most BIOSes at the time only allowed 64-bit CPUs. - The rare Xeon LV "Sossaman" came on a few motherboards with registered DDR2 memory support up to 16GB. - In the early days of x86-64 hardware, there was sometimes the need to run a 32-bit kernel to work around bugs in the hardware drivers, or in the syscall emulation for 32-bit userspace. This likely still works but there should never be a need for this any more. PAE mode is still required to get access to the 'NX' bit on Atom 'Pentium M' and 'Core Duo' CPUs. Signed-off-by: Arnd Bergmann --- Documentation/admin-guide/kdump/kdump.rst | 4 -- Documentation/arch/x86/usb-legacy-support.rst | 11 +---- arch/x86/Kconfig | 46 +++---------------- arch/x86/configs/xen.config | 2 - arch/x86/include/asm/page_32_types.h | 4 +- arch/x86/mm/init_32.c | 9 +--- 6 files changed, 11 insertions(+), 65 deletions(-) diff --git a/Documentation/admin-guide/kdump/kdump.rst b/Documentation/admi= n-guide/kdump/kdump.rst index 5376890adbeb..1f7f14c6e184 100644 --- a/Documentation/admin-guide/kdump/kdump.rst +++ b/Documentation/admin-guide/kdump/kdump.rst @@ -180,10 +180,6 @@ Dump-capture kernel config options (Arch Dependent, i3= 86 and x86_64) 1) On i386, enable high memory support under "Processor type and features":: =20 - CONFIG_HIGHMEM64G=3Dy - - or:: - CONFIG_HIGHMEM4G =20 2) With CONFIG_SMP=3Dy, usually nr_cpus=3D1 need specified on the kernel diff --git a/Documentation/arch/x86/usb-legacy-support.rst b/Documentation/= arch/x86/usb-legacy-support.rst index e01c08b7c981..b17bf122270a 100644 --- a/Documentation/arch/x86/usb-legacy-support.rst +++ b/Documentation/arch/x86/usb-legacy-support.rst @@ -20,11 +20,7 @@ It has several drawbacks, though: features (wheel, extra buttons, touchpad mode) of the real PS/2 mouse m= ay not be available. =20 -2) If CONFIG_HIGHMEM64G is enabled, the PS/2 mouse emulation can cause - system crashes, because the SMM BIOS is not expecting to be in PAE mode. - The Intel E7505 is a typical machine where this happens. - -3) If AMD64 64-bit mode is enabled, again system crashes often happen, +2) If AMD64 64-bit mode is enabled, again system crashes often happen, because the SMM BIOS isn't expecting the CPU to be in 64-bit mode. The BIOS manufacturers only test with Windows, and Windows doesn't do 64-bit yet. @@ -38,11 +34,6 @@ Problem 1) compiled-in, too. =20 Problem 2) - can currently only be solved by either disabling HIGHMEM64G - in the kernel config or USB Legacy support in the BIOS. A BIOS update - could help, but so far no such update exists. - -Problem 3) is usually fixed by a BIOS update. Check the board manufacturers web site. If an update is not available, disable USB Legacy support in the BIOS. If this alone doesn't help, try also adding diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 4a1205b22ae2..d785cb368125 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1387,15 +1387,11 @@ config X86_CPUID with major 203 and minors 0 to 31 for /dev/cpu/0/cpuid to /dev/cpu/31/cpuid. =20 -choice - prompt "High Memory Support" - default HIGHMEM4G +config HIGHMEM4G + bool "High Memory Support" depends on X86_32 - -config NOHIGHMEM - bool "off" help - Linux can use up to 64 Gigabytes of physical memory on x86 systems. + Linux can use up to 4 Gigabytes of physical memory on x86 systems. However, the address space of 32-bit x86 processors is only 4 Gigabytes large. That means that, if you have a large amount of physical memory, not all of it can be "permanently mapped" by the @@ -1411,38 +1407,9 @@ config NOHIGHMEM possible. =20 If the machine has between 1 and 4 Gigabytes physical RAM, then - answer "4GB" here. + answer "Y" here. =20 - If more than 4 Gigabytes is used then answer "64GB" here. This - selection turns Intel PAE (Physical Address Extension) mode on. - PAE implements 3-level paging on IA32 processors. PAE is fully - supported by Linux, PAE mode is implemented on all recent Intel - processors (Pentium Pro and better). NOTE: If you say "64GB" here, - then the kernel will not boot on CPUs that don't support PAE! - - The actual amount of total physical memory will either be - auto detected or can be forced by using a kernel command line option - such as "mem=3D256M". (Try "man bootparam" or see the documentation of - your boot loader (lilo or loadlin) about how to pass options to the - kernel at boot time.) - - If unsure, say "off". - -config HIGHMEM4G - bool "4GB" - help - Select this if you have a 32-bit processor and between 1 and 4 - gigabytes of physical RAM. - -config HIGHMEM64G - bool "64GB" - depends on X86_HAVE_PAE - select X86_PAE - help - Select this if you have a 32-bit processor and more than 4 - gigabytes of physical RAM. - -endchoice + If unsure, say N. =20 choice prompt "Memory split" if EXPERT @@ -1488,8 +1455,7 @@ config PAGE_OFFSET depends on X86_32 =20 config HIGHMEM - def_bool y - depends on X86_32 && (HIGHMEM64G || HIGHMEM4G) + def_bool HIGHMEM4G =20 config X86_PAE bool "PAE (Physical Address Extension) Support" diff --git a/arch/x86/configs/xen.config b/arch/x86/configs/xen.config index 581296255b39..d5d091e03bd3 100644 --- a/arch/x86/configs/xen.config +++ b/arch/x86/configs/xen.config @@ -1,6 +1,4 @@ # global x86 required specific stuff -# On 32-bit HIGHMEM4G is not allowed -CONFIG_HIGHMEM64G=3Dy CONFIG_64BIT=3Dy =20 # These enable us to allow some of the diff --git a/arch/x86/include/asm/page_32_types.h b/arch/x86/include/asm/pa= ge_32_types.h index faf9cc1c14bb..25c32652f404 100644 --- a/arch/x86/include/asm/page_32_types.h +++ b/arch/x86/include/asm/page_32_types.h @@ -11,8 +11,8 @@ * a virtual address space of one gigabyte, which limits the * amount of physical memory you can use to about 950MB. * - * If you want more physical memory than this then see the CONFIG_HIGHMEM4G - * and CONFIG_HIGHMEM64G options in the kernel configuration. + * If you want more physical memory than this then see the CONFIG_VMSPLIT_= 2G + * and CONFIG_HIGHMEM4G options in the kernel configuration. */ #define __PAGE_OFFSET_BASE _AC(CONFIG_PAGE_OFFSET, UL) #define __PAGE_OFFSET __PAGE_OFFSET_BASE diff --git a/arch/x86/mm/init_32.c b/arch/x86/mm/init_32.c index ac41b1e0940d..f288aad8dc74 100644 --- a/arch/x86/mm/init_32.c +++ b/arch/x86/mm/init_32.c @@ -582,7 +582,7 @@ static void __init lowmem_pfn_init(void) "only %luMB highmem pages available, ignoring highmem size of %luMB!\n" =20 #define MSG_HIGHMEM_TRIMMED \ - "Warning: only 4GB will be used. Use a HIGHMEM64G enabled kernel!\n" + "Warning: only 4GB will be used. Support for for CONFIG_HIGHMEM64G was re= moved!\n" /* * We have more RAM than fits into lowmem - we try to put it into * highmem, also taking the highmem=3Dx boot parameter into account: @@ -606,18 +606,13 @@ static void __init highmem_pfn_init(void) #ifndef CONFIG_HIGHMEM /* Maximum memory usable is what is directly addressable */ printk(KERN_WARNING "Warning only %ldMB will be used.\n", MAXMEM>>20); - if (max_pfn > MAX_NONPAE_PFN) - printk(KERN_WARNING "Use a HIGHMEM64G enabled kernel.\n"); - else - printk(KERN_WARNING "Use a HIGHMEM enabled kernel.\n"); + printk(KERN_WARNING "Use a HIGHMEM enabled kernel.\n"); max_pfn =3D MAXMEM_PFN; #else /* !CONFIG_HIGHMEM */ -#ifndef CONFIG_HIGHMEM64G if (max_pfn > MAX_NONPAE_PFN) { max_pfn =3D MAX_NONPAE_PFN; printk(KERN_WARNING MSG_HIGHMEM_TRIMMED); } -#endif /* !CONFIG_HIGHMEM64G */ #endif /* !CONFIG_HIGHMEM */ } =20 --=20 2.39.5 From nobody Wed Dec 17 12:43:44 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0ADCD261571 for ; Wed, 26 Feb 2025 21:37:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740605870; cv=none; b=Mhy9u+ow9enAQqQxwFZ7ZoeA4azVpWYYIyge/PcbK1XtbQ9DbfBVZnQKq10D8gG113BMyrB/aJWb2ulSOZJVviwNUNPSH+PB/jOjjn3+x6BzJU0fg3eGYjI+vsUYHaPfPkWQcuKoR0makEVCGNrbfRad/5RNFMHnhyLA4tHwsNY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740605870; c=relaxed/simple; bh=nfF50qU0K8TasWt7EehLA/reFwMuJ1HxCQcE1bCyR+s=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=bmZi2xNTIBTuIO8TerG7Ym+9QuhPte4azp5HlMIKq3Mom9D1Ob0qvZiiCLDCcUxJuaMmXrK0+ejyOYwl72rd27fyIp+NRsIewg/NlKPbqLt3GqBdkhu9btlNI4WVz3owS6qqlyzyuKe/e9DLFpt6a3KlpL2bYWFHrPd8p2qhZZ0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=L0e3TEVG; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="L0e3TEVG" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B67E5C4CED6; Wed, 26 Feb 2025 21:37:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1740605869; bh=nfF50qU0K8TasWt7EehLA/reFwMuJ1HxCQcE1bCyR+s=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=L0e3TEVG5g8DCgONdIOzy3GUGIKZhjnDhKkCV1SHe4bfTi0e9+OiWgzG+CSc06XUz rzpRLsq/6RtCPSFfAwmZWMW3LwGnLDwhOkT/qawpxKa4QnI1AoDCN4cqiMUr6l7igM h9426T9qTMdduPpuC5opmCvT5cU4MYj7bsvSfaWj52Xw5cDOsPH9HyEQdTfjUkveXL rYJlKlDoMuIGOhUVtPrHpkF0SU+46RDx9S4sDLaGRtIxnfztIOnTCh2q6/4i/3sHuy 4t5gsL0V2QAwbgj/Z8FWmDd5O6mx9xZYQ7vShV1FDV6jITd7L5/qwlDn+iMnxPk5j2 k2MSQr1W0egCA== From: Arnd Bergmann To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Arnd Bergmann , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Linus Torvalds , Andy Shevchenko , Matthew Wilcox Subject: [PATCH v3 06/10] x86: drop SWIOTLB for PAE Date: Wed, 26 Feb 2025 22:37:10 +0100 Message-Id: <20250226213714.4040853-7-arnd@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250226213714.4040853-1-arnd@kernel.org> References: <20250226213714.4040853-1-arnd@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Arnd Bergmann Since kernels with and without CONFIG_X86_PAE are now limited to the low 4GB of physical address space, there is no need to use swiotlb any more, so stop selecting this. Signed-off-by: Arnd Bergmann --- arch/x86/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index d785cb368125..2810482dc183 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1461,7 +1461,6 @@ config X86_PAE bool "PAE (Physical Address Extension) Support" depends on X86_32 && X86_HAVE_PAE select PHYS_ADDR_T_64BIT - select SWIOTLB help PAE is required for NX support, and furthermore enables larger swapspace support for non-overcommit purposes. It --=20 2.39.5 From nobody Wed Dec 17 12:43:44 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 99E5B2627F9 for ; Wed, 26 Feb 2025 21:37:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740605872; cv=none; b=L9PhVZk+NDLBwjFX8qYktsBPnG8HywynzTBiDR94g9LRepMF813mn3ckuCrubr4J55hU/il6UlXFhTn1Z+iME5cu2ULtMouDEnMCVDnFE5Mv1Pg1DIflaFB0U9EL1j+VRcIdgdVirRfc0uObzGbjyDFqpiRDqe+AmQ0mcU2pBm4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740605872; c=relaxed/simple; bh=xj/gLOZ/k2k+B/blJANMifXDpdMYDOOrLdtoa3y2btI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=omF9dI72BnSLNlZUsAOGeTCk6/nzlQ+o5Gcg20zMwJ5ILsAOvgfjlWyy+OFW1T7mgNx+AHxdC7+FCb+zuGymgK75Y2N7yqgK+z9RE1xTeOkSYGbu1n4FnTZXFUfrOQ8daEAqob7AUqRsfI1Zyvq/Qxyj1fhHxeO+Q51dgRoVNnQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=D4MWJ+n0; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="D4MWJ+n0" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 52110C4CEF1; Wed, 26 Feb 2025 21:37:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1740605872; bh=xj/gLOZ/k2k+B/blJANMifXDpdMYDOOrLdtoa3y2btI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=D4MWJ+n0WIVD4HgQicoRwhG2JTQFtfijB7juAATE/bwkZmCIJwHFIKaQFy3RDPuVs UPFpDqexwxETqjy+NJWJzYutvaLi1/xi8/2D5REUTWTd+uU24xfiOwgITjZ1XXGnmE OPm1EpZ7kBPuV0ZgQTJj+L5ZUB7y+BH25h/aTZVACqv2rvO8u0cCWXONILRGtn2og6 YmIRh1x129yISFf+S43VOxvDl9lM+t4XFVZr+8Gx4KCu6Bx1GDxDIOxsfHTjacNGT2 Q22LgxTLJTGGwHvmmUWvGywGxqZso+w/ycT5vLV2523NAQT2C2XS9lmy7ie3TdKa3e F+6MiBITjpebA== From: Arnd Bergmann To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Arnd Bergmann , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Linus Torvalds , Andy Shevchenko , Matthew Wilcox Subject: [PATCH v3 07/10] x86: drop support for CONFIG_HIGHPTE Date: Wed, 26 Feb 2025 22:37:11 +0100 Message-Id: <20250226213714.4040853-8-arnd@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250226213714.4040853-1-arnd@kernel.org> References: <20250226213714.4040853-1-arnd@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Arnd Bergmann With the maximum amount of RAM now 4GB, there is very little point to still have PTE pages in highmem. Drop this for simplification. The only other architecture supporting HIGHPTE is 32-bit arm, and once that feature is removed as well, the highpte logic can be dropped from common code as well. Signed-off-by: Arnd Bergmann --- .../admin-guide/kernel-parameters.txt | 7 ----- arch/x86/Kconfig | 9 ------- arch/x86/include/asm/pgalloc.h | 5 ---- arch/x86/mm/pgtable.c | 27 +------------------ 4 files changed, 1 insertion(+), 47 deletions(-) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentatio= n/admin-guide/kernel-parameters.txt index 8f923770a566..93177630cefb 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -7668,13 +7668,6 @@ 16 - SIGBUS faults Example: user_debug=3D31 =20 - userpte=3D - [X86,EARLY] Flags controlling user PTE allocations. - - nohigh =3D do not allocate PTE pages in - HIGHMEM regardless of setting - of CONFIG_HIGHPTE. - vdso=3D [X86,SH,SPARC] On X86_32, this is an alias for vdso32=3D. Otherwise: =20 diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 2810482dc183..aba32f88870d 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1627,15 +1627,6 @@ config X86_PMEM_LEGACY =20 Say Y if unsure. =20 -config HIGHPTE - bool "Allocate 3rd-level pagetables from highmem" - depends on HIGHMEM - help - The VM uses one page table entry for each page of physical memory. - For systems with a lot of RAM, this can be wasteful of precious - low memory. Setting this option will put user-space page table - entries in high memory. - config X86_CHECK_BIOS_CORRUPTION bool "Check for low memory corruption" help diff --git a/arch/x86/include/asm/pgalloc.h b/arch/x86/include/asm/pgalloc.h index dd4841231bb9..a33147520044 100644 --- a/arch/x86/include/asm/pgalloc.h +++ b/arch/x86/include/asm/pgalloc.h @@ -29,11 +29,6 @@ static inline void paravirt_release_pud(unsigned long pf= n) {} static inline void paravirt_release_p4d(unsigned long pfn) {} #endif =20 -/* - * Flags to use when allocating a user page table page. - */ -extern gfp_t __userpte_alloc_gfp; - #ifdef CONFIG_MITIGATION_PAGE_TABLE_ISOLATION /* * Instead of one PGD, we acquire two PGDs. Being order-1, it is diff --git a/arch/x86/mm/pgtable.c b/arch/x86/mm/pgtable.c index 1fef5ad32d5a..94b5601f2cd8 100644 --- a/arch/x86/mm/pgtable.c +++ b/arch/x86/mm/pgtable.c @@ -12,12 +12,6 @@ phys_addr_t physical_mask __ro_after_init =3D (1ULL << _= _PHYSICAL_MASK_SHIFT) - 1; EXPORT_SYMBOL(physical_mask); #endif =20 -#ifdef CONFIG_HIGHPTE -#define PGTABLE_HIGHMEM __GFP_HIGHMEM -#else -#define PGTABLE_HIGHMEM 0 -#endif - #ifndef CONFIG_PARAVIRT #ifndef CONFIG_PT_RECLAIM static inline @@ -37,29 +31,10 @@ void paravirt_tlb_remove_table(struct mmu_gather *tlb, = void *table) #endif /* !CONFIG_PT_RECLAIM */ #endif /* !CONFIG_PARAVIRT */ =20 -gfp_t __userpte_alloc_gfp =3D GFP_PGTABLE_USER | PGTABLE_HIGHMEM; - pgtable_t pte_alloc_one(struct mm_struct *mm) { - return __pte_alloc_one(mm, __userpte_alloc_gfp); -} - -static int __init setup_userpte(char *arg) -{ - if (!arg) - return -EINVAL; - - /* - * "userpte=3Dnohigh" disables allocation of user pagetables in - * high memory. - */ - if (strcmp(arg, "nohigh") =3D=3D 0) - __userpte_alloc_gfp &=3D ~__GFP_HIGHMEM; - else - return -EINVAL; - return 0; + return __pte_alloc_one(mm, GFP_PGTABLE_USER); } -early_param("userpte", setup_userpte); =20 void ___pte_free_tlb(struct mmu_gather *tlb, struct page *pte) { --=20 2.39.5 From nobody Wed Dec 17 12:43:44 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4C9122661B5 for ; Wed, 26 Feb 2025 21:37:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740605875; cv=none; b=LsSdoTB+BVmE6z9bTbc0IGe6STkDenQ3NF3/cPq33QH2Q9nTpwg475Wn60xKcrl1xfBDrbN/Sd4EDodSDNODxJAWDJeN5ftm2O2cZeAbUas1PKcXyFrf1nAYRzVLeIFQ+pn0vshygrvVGPeW+ID1hG9kuaxwd49SNZptZNRkDqI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740605875; c=relaxed/simple; bh=zFHhKHiqgU3FhAAL2PwPWvWsa0XESYEOYyIQF5YlQzY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=bLQmZxwbTFNUa5w53hwsfAnFEoVNGRbXL+5MHDhh9nojLkbLMyQNB3NgBAWeyumOlZ7sgMQldR5+D6xnyz4PF4ZEmERVHcmSrR0bVSk+T+QrRmW9kBYFhPrX2bAW/o6VB05QfQnHtvcJCp6EbxsldxLMuG3uHOk86vbDHNviPjs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=nFN2OZSN; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="nFN2OZSN" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D93F4C4CED6; Wed, 26 Feb 2025 21:37:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1740605875; bh=zFHhKHiqgU3FhAAL2PwPWvWsa0XESYEOYyIQF5YlQzY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=nFN2OZSNJ2KW6Q7Ls3iiQ+ZGPTcAv3lJXsm6H1tDXiRGXqUTrxoi3zwcNmAgw7RuV MB6NkIQgW0l8Ltpn8qty5UDH5aEGLeglAC7PyWUacAoBk5DojKLYJBg38zqd4Pz8wb z9CoW/e/hgivu4oULpn+MiLaPMnekTcpc2x6Jteo0Q8l6DsIIjMHlhhZxZFrmFT+M9 kZqUBbrCR1LfOopgpuCAk/DLMsYsbmbZNbM3oy5UVRzdEs7GuFn+4flPXeFSxTUD9N TW2nwnZ32PeWlwZdUXl+cWKXluAUcwkJOExiubD2igezv0MGzPe6Yey3g7K0b6RIom WrJJEOmeszTlA== From: Arnd Bergmann To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Arnd Bergmann , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Linus Torvalds , Andy Shevchenko , Matthew Wilcox , Ferry Toth Subject: [PATCH v3 08/10] x86: document X86_INTEL_MID as 64-bit-only Date: Wed, 26 Feb 2025 22:37:12 +0100 Message-Id: <20250226213714.4040853-9-arnd@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250226213714.4040853-1-arnd@kernel.org> References: <20250226213714.4040853-1-arnd@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Arnd Bergmann The X86_INTEL_MID code was originally introduced for the 32-bit Moorestown/Medfield/Clovertrail platform, later the 64-bit Merrifield/Moorefield variants were added, but the final Morganfield 14nm platform was canceled before it hit the market. To help users understand what the option actually refers to, update the help text, and add a dependency on 64-bit kernels. Ferry confirmed that all the hardware can run 64-bit kernels these days, but is still testing 32-bit kernels on the Intel Edison board, so this remains possible, but is guarded by a CONFIG_EXPERT dependency now, to gently push remaining users towards using CONFIG_64BIT. Cc: Ferry Toth Link: https://lore.kernel.org/lkml/d890eecc-97de-4abf-8e0e-b881d5db5c1d@gma= il.com/ Acked-by: Andy Shevchenko Signed-off-by: Arnd Bergmann --- arch/x86/Kconfig | 50 ++++++++++++++++++++++++++++-------------------- 1 file changed, 29 insertions(+), 21 deletions(-) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index aba32f88870d..42dd3c58abfb 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -548,12 +548,12 @@ config X86_EXTENDED_PLATFORM RDC R-321x SoC SGI 320/540 (Visual Workstation) STA2X11-based (e.g. Northville) - Moorestown MID devices =20 64-bit platforms (CONFIG_64BIT=3Dy): Numascale NumaChip ScaleMP vSMP SGI Ultraviolet + Merrifield/Moorefield MID devices =20 If you have one of these systems, or if you want to build a generic distribution kernel, say Y here - otherwise say N. @@ -598,8 +598,31 @@ config X86_UV This option is needed in order to support SGI Ultraviolet systems. If you don't have one of these, you should say N here. =20 -# Following is an alphabetically sorted list of 32 bit extended platforms -# Please maintain the alphabetic order if and when there are additions +config X86_INTEL_MID + bool "Intel Z34xx/Z35xx MID platform support" + depends on X86_EXTENDED_PLATFORM + depends on X86_PLATFORM_DEVICES + depends on PCI + depends on X86_64 || (EXPERT && PCI_GOANY) + depends on X86_IO_APIC + select I2C + select DW_APB_TIMER + select INTEL_SCU_PCI + help + Select to build a kernel capable of supporting 64-bit Intel MID + (Mobile Internet Device) platform systems which do not have + the PCI legacy interfaces. + + The only supported devices are the 22nm Merrified (Z34xx) + and Moorefield (Z35xx) SoC used in the Intel Edison board and + a small number of Android devices such as the Asus Zenfone 2, + Asus FonePad 8 and Dell Venue 7. + + If you are building for a PC class system or non-MID tablet + SoCs like Bay Trail (Z36xx/Z37xx), say N here. + + Intel MID platforms are based on an Intel processor and chipset which + consume less power than most of the x86 derivatives. =20 config X86_GOLDFISH bool "Goldfish (Virtual Platform)" @@ -609,6 +632,9 @@ config X86_GOLDFISH for Android development. Unless you are building for the Android Goldfish emulator say N here. =20 +# Following is an alphabetically sorted list of 32 bit extended platforms +# Please maintain the alphabetic order if and when there are additions + config X86_INTEL_CE bool "CE4100 TV platform" depends on PCI @@ -624,24 +650,6 @@ config X86_INTEL_CE This option compiles in support for the CE4100 SOC for settop boxes and media devices. =20 -config X86_INTEL_MID - bool "Intel MID platform support" - depends on X86_EXTENDED_PLATFORM - depends on X86_PLATFORM_DEVICES - depends on PCI - depends on X86_64 || (PCI_GOANY && X86_32) - depends on X86_IO_APIC - select I2C - select DW_APB_TIMER - select INTEL_SCU_PCI - help - Select to build a kernel capable of supporting Intel MID (Mobile - Internet Device) platform systems which do not have the PCI legacy - interfaces. If you are building for a PC class system say N here. - - Intel MID platforms are based on an Intel processor and chipset which - consume less power than most of the x86 derivatives. - config X86_INTEL_QUARK bool "Intel Quark platform support" depends on X86_32 --=20 2.39.5 From nobody Wed Dec 17 12:43:44 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7DCF92661B5 for ; Wed, 26 Feb 2025 21:37:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740605878; cv=none; b=nmbGr6OrWR0iIU+nvGRyunRGl3eYFjvqOZ7aJxggbbbmGi2TuVXJ4cJegg/FKVH4/4ZGKL7iDgwigWK9O4yw+oiKHD4NQF965j4D/D2MfI3YhUeqPVYSmoO4ixXvWfQfxices6Ayf6HudJVv680YRLgvNeTKMkzBa6FtHM2hbS4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740605878; c=relaxed/simple; bh=ifI9Snfcz3zQLA9mdjWdKtA//RgDy8KyxkOighq+7AM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=T4S4jIkEqihnHspvRbzzWIIsYd/bq3BDhTiLq9+MqCKHbUFyOu1Nl/kF/m4x3HeOWcJlpwjYrjpc51BzdIPDlmBVPT2mhQA6HKGTw/43DxQRtMJkycbZSy9EIv+uCnvwj68HoZUJCC4GPOuEJCrQK3ce18ZsPNyQ7FtES754n4Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=syFJyoYO; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="syFJyoYO" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 94508C4CED6; Wed, 26 Feb 2025 21:37:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1740605877; bh=ifI9Snfcz3zQLA9mdjWdKtA//RgDy8KyxkOighq+7AM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=syFJyoYO9efFR9Nf4TZf/C3HO3vUfSoLg+jGDXpSz/z5h2Lw7F4nHXrG22ngzTSjI fKCw1uLhfIYDaICw3Az9kCCcdrFApLt1I21hePwgj/e6xlef7ZIBkGOy975N/g3Ywh uUIkh/B61Ir1Thnb2KWzg9o/RQLP+g21cPZ4Cd251h6Z8zB5mCpMHSK81Jle/7m88J ELGc9TPb2wFxysy2c3fmpo2C0ZQUdUcGgy8mk8R3tP1UQoQfICaaWMDwLL8L3NCZgZ Tnw6Ax93puIlirmEVX4BhiJiI0FrLJAI5OSdyJBHPxJL7luqiPJaulzgExnHbhCAiL mYUjfZfFGMsOg== From: Arnd Bergmann To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Arnd Bergmann , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Linus Torvalds , Andy Shevchenko , Matthew Wilcox , Davide Ciminaghi Subject: [PATCH v3 09/10] x86: remove old STA2x11 support Date: Wed, 26 Feb 2025 22:37:13 +0100 Message-Id: <20250226213714.4040853-10-arnd@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250226213714.4040853-1-arnd@kernel.org> References: <20250226213714.4040853-1-arnd@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Arnd Bergmann ST ConneXt STA2x11 was an interface chip for Atom E6xx processors, using a number of components usually found on Arm SoCs. Most of this was merged upstream, but it was never complete enough to actually work and has been abandoned for many years. We already had an agreement on removing it in 2022, but nobody ever submitted the patch to do it. Without STA2x11, the CONFIG_X86_32_NON_STANDARD no longer has any use. Suggested-by: Davide Ciminaghi Link: https://lore.kernel.org/lkml/Yw3DKCuDoPkCaqxE@arcana.i.gnudd.com/ Signed-off-by: Arnd Bergmann --- arch/x86/Kconfig | 32 +---- arch/x86/include/asm/sta2x11.h | 13 -- arch/x86/pci/Makefile | 2 - arch/x86/pci/sta2x11-fixup.c | 233 --------------------------------- 4 files changed, 3 insertions(+), 277 deletions(-) delete mode 100644 arch/x86/include/asm/sta2x11.h delete mode 100644 arch/x86/pci/sta2x11-fixup.c diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 42dd3c58abfb..14dd7b5abd5d 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -547,7 +547,6 @@ config X86_EXTENDED_PLATFORM AMD Elan RDC R-321x SoC SGI 320/540 (Visual Workstation) - STA2X11-based (e.g. Northville) =20 64-bit platforms (CONFIG_64BIT=3Dy): Numascale NumaChip @@ -731,18 +730,6 @@ config X86_RDC321X as R-8610-(G). If you don't have one of these chips, you should say N here. =20 -config X86_32_NON_STANDARD - bool "Support non-standard 32-bit SMP architectures" - depends on X86_32 && SMP - depends on X86_EXTENDED_PLATFORM - help - This option compiles in the STA2X11 default - subarchitecture. It is intended for a generic binary - kernel. If you select them all, kernel will probe it one by - one and will fallback to default. - -# Alphabetically sorted list of Non standard 32 bit platforms - config X86_SUPPORTS_MEMORY_FAILURE def_bool y # MCE code calls memory_failure(): @@ -752,19 +739,6 @@ config X86_SUPPORTS_MEMORY_FAILURE depends on X86_64 || !SPARSEMEM select ARCH_SUPPORTS_MEMORY_FAILURE =20 -config STA2X11 - bool "STA2X11 Companion Chip Support" - depends on X86_32_NON_STANDARD && PCI - select SWIOTLB - select MFD_STA2X11 - select GPIOLIB - help - This adds support for boards based on the STA2X11 IO-Hub, - a.k.a. "ConneXt". The chip is used in place of the standard - PC chipset, so all "standard" peripherals are missing. If this - option is selected the kernel will still be able to boot on - standard PC machines. - config X86_32_IRIS tristate "Eurobraille/Iris poweroff module" depends on X86_32 @@ -1102,7 +1076,7 @@ config UP_LATE_INIT config X86_UP_APIC bool "Local APIC support on uniprocessors" if !PCI_MSI default PCI_MSI - depends on X86_32 && !SMP && !X86_32_NON_STANDARD + depends on X86_32 && !SMP help A local APIC (Advanced Programmable Interrupt Controller) is an integrated interrupt controller in the CPU. If you have a single-CPU @@ -1127,7 +1101,7 @@ config X86_UP_IOAPIC =20 config X86_LOCAL_APIC def_bool y - depends on X86_64 || SMP || X86_32_NON_STANDARD || X86_UP_APIC || PCI_MSI + depends on X86_64 || SMP || X86_UP_APIC || PCI_MSI select IRQ_DOMAIN_HIERARCHY =20 config ACPI_MADT_WAKEUP @@ -1589,7 +1563,7 @@ config ARCH_FLATMEM_ENABLE =20 config ARCH_SPARSEMEM_ENABLE def_bool y - depends on X86_64 || NUMA || X86_32 || X86_32_NON_STANDARD + depends on X86_64 || NUMA || X86_32 select SPARSEMEM_STATIC if X86_32 select SPARSEMEM_VMEMMAP_ENABLE if X86_64 =20 diff --git a/arch/x86/include/asm/sta2x11.h b/arch/x86/include/asm/sta2x11.h deleted file mode 100644 index e0975e9c4f47..000000000000 --- a/arch/x86/include/asm/sta2x11.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Header file for STMicroelectronics ConneXt (STA2X11) IOHub - */ -#ifndef __ASM_STA2X11_H -#define __ASM_STA2X11_H - -#include - -/* This needs to be called from the MFD to configure its sub-devices */ -struct sta2x11_instance *sta2x11_get_instance(struct pci_dev *pdev); - -#endif /* __ASM_STA2X11_H */ diff --git a/arch/x86/pci/Makefile b/arch/x86/pci/Makefile index 48bcada5cabe..4933fb337983 100644 --- a/arch/x86/pci/Makefile +++ b/arch/x86/pci/Makefile @@ -12,8 +12,6 @@ obj-$(CONFIG_X86_INTEL_CE) +=3D ce4100.o obj-$(CONFIG_ACPI) +=3D acpi.o obj-y +=3D legacy.o irq.o =20 -obj-$(CONFIG_STA2X11) +=3D sta2x11-fixup.o - obj-$(CONFIG_X86_NUMACHIP) +=3D numachip.o =20 obj-$(CONFIG_X86_INTEL_MID) +=3D intel_mid_pci.o diff --git a/arch/x86/pci/sta2x11-fixup.c b/arch/x86/pci/sta2x11-fixup.c deleted file mode 100644 index 8c8ddc4dcc08..000000000000 --- a/arch/x86/pci/sta2x11-fixup.c +++ /dev/null @@ -1,233 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * DMA translation between STA2x11 AMBA memory mapping and the x86 memory = mapping - * - * ST Microelectronics ConneXt (STA2X11/STA2X10) - * - * Copyright (c) 2010-2011 Wind River Systems, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#define STA2X11_SWIOTLB_SIZE (4*1024*1024) - -/* - * We build a list of bus numbers that are under the ConneXt. The - * main bridge hosts 4 busses, which are the 4 endpoints, in order. - */ -#define STA2X11_NR_EP 4 /* 0..3 included */ -#define STA2X11_NR_FUNCS 8 /* 0..7 included */ -#define STA2X11_AMBA_SIZE (512 << 20) - -struct sta2x11_ahb_regs { /* saved during suspend */ - u32 base, pexlbase, pexhbase, crw; -}; - -struct sta2x11_mapping { - int is_suspended; - struct sta2x11_ahb_regs regs[STA2X11_NR_FUNCS]; -}; - -struct sta2x11_instance { - struct list_head list; - int bus0; - struct sta2x11_mapping map[STA2X11_NR_EP]; -}; - -static LIST_HEAD(sta2x11_instance_list); - -/* At probe time, record new instances of this bridge (likely one only) */ -static void sta2x11_new_instance(struct pci_dev *pdev) -{ - struct sta2x11_instance *instance; - - instance =3D kzalloc(sizeof(*instance), GFP_ATOMIC); - if (!instance) - return; - /* This has a subordinate bridge, with 4 more-subordinate ones */ - instance->bus0 =3D pdev->subordinate->number + 1; - - if (list_empty(&sta2x11_instance_list)) { - int size =3D STA2X11_SWIOTLB_SIZE; - /* First instance: register your own swiotlb area */ - dev_info(&pdev->dev, "Using SWIOTLB (size %i)\n", size); - if (swiotlb_init_late(size, GFP_DMA, NULL)) - dev_emerg(&pdev->dev, "init swiotlb failed\n"); - } - list_add(&instance->list, &sta2x11_instance_list); -} -DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_STMICRO, 0xcc17, sta2x11_new_instan= ce); - -/* - * Utility functions used in this file from below - */ -static struct sta2x11_instance *sta2x11_pdev_to_instance(struct pci_dev *p= dev) -{ - struct sta2x11_instance *instance; - int ep; - - list_for_each_entry(instance, &sta2x11_instance_list, list) { - ep =3D pdev->bus->number - instance->bus0; - if (ep >=3D 0 && ep < STA2X11_NR_EP) - return instance; - } - return NULL; -} - -static int sta2x11_pdev_to_ep(struct pci_dev *pdev) -{ - struct sta2x11_instance *instance; - - instance =3D sta2x11_pdev_to_instance(pdev); - if (!instance) - return -1; - - return pdev->bus->number - instance->bus0; -} - -/* This is exported, as some devices need to access the MFD registers */ -struct sta2x11_instance *sta2x11_get_instance(struct pci_dev *pdev) -{ - return sta2x11_pdev_to_instance(pdev); -} -EXPORT_SYMBOL(sta2x11_get_instance); - -/* At setup time, we use our own ops if the device is a ConneXt one */ -static void sta2x11_setup_pdev(struct pci_dev *pdev) -{ - struct sta2x11_instance *instance =3D sta2x11_pdev_to_instance(pdev); - - if (!instance) /* either a sta2x11 bridge or another ST device */ - return; - - /* We must enable all devices as master, for audio DMA to work */ - pci_set_master(pdev); -} -DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_STMICRO, PCI_ANY_ID, sta2x11_setup_= pdev); - -/* - * At boot we must set up the mappings for the pcie-to-amba bridge. - * It involves device access, and the same happens at suspend/resume time - */ - -#define AHB_MAPB 0xCA4 -#define AHB_CRW(i) (AHB_MAPB + 0 + (i) * 0x10) -#define AHB_CRW_SZMASK 0xfffffc00UL -#define AHB_CRW_ENABLE (1 << 0) -#define AHB_CRW_WTYPE_MEM (2 << 1) -#define AHB_CRW_ROE (1UL << 3) /* Relax Order Ena */ -#define AHB_CRW_NSE (1UL << 4) /* No Snoop Enable */ -#define AHB_BASE(i) (AHB_MAPB + 4 + (i) * 0x10) -#define AHB_PEXLBASE(i) (AHB_MAPB + 8 + (i) * 0x10) -#define AHB_PEXHBASE(i) (AHB_MAPB + 12 + (i) * 0x10) - -/* At probe time, enable mapping for each endpoint, using the pdev */ -static void sta2x11_map_ep(struct pci_dev *pdev) -{ - struct sta2x11_instance *instance =3D sta2x11_pdev_to_instance(pdev); - struct device *dev =3D &pdev->dev; - u32 amba_base, max_amba_addr; - int i, ret; - - if (!instance) - return; - - pci_read_config_dword(pdev, AHB_BASE(0), &amba_base); - max_amba_addr =3D amba_base + STA2X11_AMBA_SIZE - 1; - - ret =3D dma_direct_set_offset(dev, 0, amba_base, STA2X11_AMBA_SIZE); - if (ret) - dev_err(dev, "sta2x11: could not set DMA offset\n"); - - dev->bus_dma_limit =3D max_amba_addr; - dma_set_mask_and_coherent(&pdev->dev, max_amba_addr); - - /* Configure AHB mapping */ - pci_write_config_dword(pdev, AHB_PEXLBASE(0), 0); - pci_write_config_dword(pdev, AHB_PEXHBASE(0), 0); - pci_write_config_dword(pdev, AHB_CRW(0), STA2X11_AMBA_SIZE | - AHB_CRW_WTYPE_MEM | AHB_CRW_ENABLE); - - /* Disable all the other windows */ - for (i =3D 1; i < STA2X11_NR_FUNCS; i++) - pci_write_config_dword(pdev, AHB_CRW(i), 0); - - dev_info(&pdev->dev, - "sta2x11: Map EP %i: AMBA address %#8x-%#8x\n", - sta2x11_pdev_to_ep(pdev), amba_base, max_amba_addr); -} -DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_STMICRO, PCI_ANY_ID, sta2x11_map_ep= ); - -#ifdef CONFIG_PM /* Some register values must be saved and restored */ - -static struct sta2x11_mapping *sta2x11_pdev_to_mapping(struct pci_dev *pde= v) -{ - struct sta2x11_instance *instance; - int ep; - - instance =3D sta2x11_pdev_to_instance(pdev); - if (!instance) - return NULL; - ep =3D sta2x11_pdev_to_ep(pdev); - return instance->map + ep; -} - -static void suspend_mapping(struct pci_dev *pdev) -{ - struct sta2x11_mapping *map =3D sta2x11_pdev_to_mapping(pdev); - int i; - - if (!map) - return; - - if (map->is_suspended) - return; - map->is_suspended =3D 1; - - /* Save all window configs */ - for (i =3D 0; i < STA2X11_NR_FUNCS; i++) { - struct sta2x11_ahb_regs *regs =3D map->regs + i; - - pci_read_config_dword(pdev, AHB_BASE(i), ®s->base); - pci_read_config_dword(pdev, AHB_PEXLBASE(i), ®s->pexlbase); - pci_read_config_dword(pdev, AHB_PEXHBASE(i), ®s->pexhbase); - pci_read_config_dword(pdev, AHB_CRW(i), ®s->crw); - } -} -DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_STMICRO, PCI_ANY_ID, suspend_mappi= ng); - -static void resume_mapping(struct pci_dev *pdev) -{ - struct sta2x11_mapping *map =3D sta2x11_pdev_to_mapping(pdev); - int i; - - if (!map) - return; - - - if (!map->is_suspended) - goto out; - map->is_suspended =3D 0; - - /* Restore all window configs */ - for (i =3D 0; i < STA2X11_NR_FUNCS; i++) { - struct sta2x11_ahb_regs *regs =3D map->regs + i; - - pci_write_config_dword(pdev, AHB_BASE(i), regs->base); - pci_write_config_dword(pdev, AHB_PEXLBASE(i), regs->pexlbase); - pci_write_config_dword(pdev, AHB_PEXHBASE(i), regs->pexhbase); - pci_write_config_dword(pdev, AHB_CRW(i), regs->crw); - } -out: - pci_set_master(pdev); /* Like at boot, enable master on all devices */ -} -DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_STMICRO, PCI_ANY_ID, resume_mapping= ); - -#endif /* CONFIG_PM */ --=20 2.39.5 From nobody Wed Dec 17 12:43:44 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B7DD825A659 for ; Wed, 26 Feb 2025 21:38:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740605880; cv=none; b=O8c0Jbx4z4+S+sWi6F8NirUpYRkSJAWJ+JGu7tjyDI3eihVNdI+sHwUZe2sEgcehch0xw2jSC7ZPCWgb9MmeSpcfOl6XYJDlqp0NvP09S5Pv8BGskrwax/sYLjk1bWaJyMvMDuY4TRUyQoUj9CUQvieP50fw99qbMxEKj0c1538= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740605880; c=relaxed/simple; bh=IOxQVnALRKR6nwmNlhLbcO8Dis1BaEtI2yIqJXyBP5w=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=d22EFgs+apX4KJ5mVahBzJIONo0HgblieA8vVdssUVBTL6UYh38fP72wJacNydmD1TKAZgs7aHpXSKkAOTu3xgUpmwg3rcDaksSeOImNBW9TP/GnEQhVzOfIpLMQLmF5moqh5R6YPcXYnBUWoOlZ4eLoggVBIIiLcVSZD18Hrms= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=K4W21VhZ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="K4W21VhZ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4FF84C4CEED; Wed, 26 Feb 2025 21:37:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1740605880; bh=IOxQVnALRKR6nwmNlhLbcO8Dis1BaEtI2yIqJXyBP5w=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=K4W21VhZgJrYaxE9alE/r5v6cKrWD3ezLnm/9XG+b/JWPbuh2K3TY7kHWArOmOHDO PivTHoOVgvG2yxddAR0LeVTY+xxROJFcSNoX77hymIDip58Gu8QpBE1pqabo9NA4gI a2gF7ss47BQT/4+NupWT2VgL9UuHhVncDGp++VaxoF87tGY4yhWVrnRXaqtDejIoxJ xHWaUe6SuPNtel33DgB3QQWz6KB5qNynOWK0PtilP3VtaZdzHn6QGyCA6QMlNx72R0 n39A9D9++Tao/W1NktnnhfiqhSjWoXMGxy/OUU7m4NTvHGNbYP0613MxNq036ntfBH rB59TBQd4E1ew== From: Arnd Bergmann To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Arnd Bergmann , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Linus Torvalds , Andy Shevchenko , Matthew Wilcox , "Maciej W. Rozycki" Subject: [PATCH v3 10/10] x86: only allow EISA for 32-bit Date: Wed, 26 Feb 2025 22:37:14 +0100 Message-Id: <20250226213714.4040853-11-arnd@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250226213714.4040853-1-arnd@kernel.org> References: <20250226213714.4040853-1-arnd@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Arnd Bergmann The CONFIG_EISA menu was cleaned up in 2018, but this inadvertently brought the option back on 64-bit machines: ISA remains guarded by a CONFIG_X86_32 check, but EISA no longer depends on ISA. The last Intel machines ith EISA support used a 82375EB PCI/EISA bridge from 1993 that could be paired with the 440FX chipset on early Pentium-II CPUs, long before the first x86-64 products. Fixes: 6630a8e50105 ("eisa: consolidate EISA Kconfig entry in drivers/eisa") Cc: "Maciej W. Rozycki" Signed-off-by: Arnd Bergmann --- arch/x86/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 14dd7b5abd5d..f84a9e5dda20 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -232,7 +232,7 @@ config X86 select HAVE_SAMPLE_FTRACE_DIRECT_MULTI if X86_64 select HAVE_EBPF_JIT select HAVE_EFFICIENT_UNALIGNED_ACCESS - select HAVE_EISA + select HAVE_EISA if X86_32 select HAVE_EXIT_THREAD select HAVE_GUP_FAST select HAVE_FENTRY if X86_64 || DYNAMIC_FTRACE --=20 2.39.5