From nobody Fri Dec 19 21:12:22 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8075B21B9CC for ; Wed, 26 Feb 2025 13:03:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740575039; cv=none; b=A7Dhm/dvkoKWPlYqN0TQBDuxiwQHUo7WDyA8UFTKeUYtoqsEYFBtPys4RivwxF1Y+pMV5mBrllv+tqMof/kyly9pUNubOnY/H/cAZaxybe+noAkcffbbBiHxxExbOzTpEuZG8DvbDA5gi2MgWKL4VKDb+mhzMIPY1W6lB4DtwHw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740575039; c=relaxed/simple; bh=8jiS+kPdQZP7EWPxn7Of1UXgpTQ62xuev1qCkeye9+0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=JplG0i8f7j6MaH3KLUDHotH9xqJSlzniMWFw3twa0la5661FPDIWgASnJ1UtgsMdWMfhynWAgaGIACTjFLkdRSThO3CtWIXUb3zCNjyDVnEfsGiXFJaSG7ivvUgs8J+GNETD6CyVh8+qirm3FDYxB4Hd0bzmIWYhAULxDaW9LQQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=WD4V6KQ3; arc=none smtp.client-ip=198.175.65.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="WD4V6KQ3" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1740575038; x=1772111038; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=8jiS+kPdQZP7EWPxn7Of1UXgpTQ62xuev1qCkeye9+0=; b=WD4V6KQ3kyWGM6cnCyLpCh7sjJY4oHtn/27WBchHJxPSKRi8ffPjdELj C0C+24eC5HI82UjPY/ZV0IT/n8vr5h2x+OKemaacv0Ig7PDVb/trGfGJm 6Md/y9pONLsjEd/trGCLmkk+TbUjjHXZiIZS64zApraqAcKlUW21ix8kb Sz4SeR15MCCYKwyLKbd87HtjNO2HZ4CGPgc+ZlYrPDhHCdY93RfS4ddCm Aqnp67R/RDt7JTF/4cqFt7I1DsoVw3rbYVSuYIWKOsmBI+IIUT+3+9vVd 5HQCAKzY2s6tI9BYM75KrDt47X6UsuGB7eSKN7ZZK6U5ID2IjYQ14bX2V A==; X-CSE-ConnectionGUID: awmYf1mJR+e3+gOxr0o4jQ== X-CSE-MsgGUID: bWQkbgcTQ8GBrMVDNBOaxw== X-IronPort-AV: E=McAfee;i="6700,10204,11357"; a="41341675" X-IronPort-AV: E=Sophos;i="6.13,317,1732608000"; d="scan'208";a="41341675" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Feb 2025 05:03:58 -0800 X-CSE-ConnectionGUID: kh+122C9SgecQqqNpusQEg== X-CSE-MsgGUID: A21xIJetS9CbUuTMCxUurQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,317,1732608000"; d="scan'208";a="121691034" Received: from sannilnx-dsk.jer.intel.com ([10.12.231.107]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Feb 2025 05:03:52 -0800 From: Alexander Usyskin To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Lucas De Marchi , =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , Rodrigo Vivi , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Jani Nikula , Joonas Lahtinen , Tvrtko Ursulin , Karthik Poosa Cc: Reuven Abliyev , Oren Weil , linux-mtd@lists.infradead.org, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, Alexander Usyskin Subject: [PATCH v5 11/11] drm/xe/nvm: add support for access mode Date: Wed, 26 Feb 2025 14:51:43 +0200 Message-ID: <20250226125143.3791515-12-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250226125143.3791515-1-alexander.usyskin@intel.com> References: <20250226125143.3791515-1-alexander.usyskin@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Check NVM access mode from GSC FW status registers and overwrite access status read from SPI descriptor, if needed. Reviewed-by: Rodrigo Vivi Signed-off-by: Alexander Usyskin --- drivers/gpu/drm/xe/regs/xe_gsc_regs.h | 4 ++++ drivers/gpu/drm/xe/xe_heci_gsc.c | 5 +---- drivers/gpu/drm/xe/xe_nvm.c | 32 ++++++++++++++++++++++++++- 3 files changed, 36 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/xe/regs/xe_gsc_regs.h b/drivers/gpu/drm/xe/reg= s/xe_gsc_regs.h index 7702364b65f1..9b66cc972a63 100644 --- a/drivers/gpu/drm/xe/regs/xe_gsc_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_gsc_regs.h @@ -16,6 +16,10 @@ #define MTL_GSC_HECI1_BASE 0x00116000 #define MTL_GSC_HECI2_BASE 0x00117000 =20 +#define DG1_GSC_HECI2_BASE 0x00259000 +#define PVC_GSC_HECI2_BASE 0x00285000 +#define DG2_GSC_HECI2_BASE 0x00374000 + #define HECI_H_CSR(base) XE_REG((base) + 0x4) #define HECI_H_CSR_IE REG_BIT(0) #define HECI_H_CSR_IS REG_BIT(1) diff --git a/drivers/gpu/drm/xe/xe_heci_gsc.c b/drivers/gpu/drm/xe/xe_heci_= gsc.c index 3ea325d3db99..266097a5b98b 100644 --- a/drivers/gpu/drm/xe/xe_heci_gsc.c +++ b/drivers/gpu/drm/xe/xe_heci_gsc.c @@ -11,15 +11,12 @@ #include "xe_device_types.h" #include "xe_drv.h" #include "xe_heci_gsc.h" +#include "regs/xe_gsc_regs.h" #include "xe_platform_types.h" #include "xe_survivability_mode.h" =20 #define GSC_BAR_LENGTH 0x00000FFC =20 -#define DG1_GSC_HECI2_BASE 0x259000 -#define PVC_GSC_HECI2_BASE 0x285000 -#define DG2_GSC_HECI2_BASE 0x374000 - static void heci_gsc_irq_mask(struct irq_data *d) { /* generic irq handling */ diff --git a/drivers/gpu/drm/xe/xe_nvm.c b/drivers/gpu/drm/xe/xe_nvm.c index 26de7d4472c8..08fe3bf04cf0 100644 --- a/drivers/gpu/drm/xe/xe_nvm.c +++ b/drivers/gpu/drm/xe/xe_nvm.c @@ -6,8 +6,11 @@ #include #include =20 +#include "xe_device.h" #include "xe_device_types.h" +#include "xe_mmio.h" #include "xe_nvm.h" +#include "regs/xe_gsc_regs.h" #include "xe_sriov.h" =20 #define GEN12_GUNIT_NVM_BASE 0x00102040 @@ -25,6 +28,33 @@ static void xe_nvm_release_dev(struct device *dev) { } =20 +static bool xe_nvm_writeable_override(struct xe_device *xe) +{ + struct xe_gt *gt =3D xe_root_mmio_gt(xe); + resource_size_t base; + bool writeable_override; + + if (xe->info.platform =3D=3D XE_BATTLEMAGE) { + base =3D DG2_GSC_HECI2_BASE; + } else if (xe->info.platform =3D=3D XE_PVC) { + base =3D PVC_GSC_HECI2_BASE; + } else if (xe->info.platform =3D=3D XE_DG2) { + base =3D DG2_GSC_HECI2_BASE; + } else if (xe->info.platform =3D=3D XE_DG1) { + base =3D DG1_GSC_HECI2_BASE; + } else { + drm_err(&xe->drm, "Unknown platform\n"); + return true; + } + + writeable_override =3D + !(xe_mmio_read32(>->mmio, HECI_FWSTS2(base)) & + HECI_FW_STATUS_2_NVM_ACCESS_MODE); + if (writeable_override) + drm_info(&xe->drm, "NVM access overridden by jumper\n"); + return writeable_override; +} + void xe_nvm_init(struct xe_device *xe) { struct pci_dev *pdev =3D to_pci_dev(xe->drm.dev); @@ -49,7 +79,7 @@ void xe_nvm_init(struct xe_device *xe) =20 nvm =3D xe->nvm; =20 - nvm->writeable_override =3D false; + nvm->writeable_override =3D xe_nvm_writeable_override(xe); nvm->bar.parent =3D &pdev->resource[0]; nvm->bar.start =3D GEN12_GUNIT_NVM_BASE + pdev->resource[0].start; nvm->bar.end =3D nvm->bar.start + GEN12_GUNIT_NVM_SIZE - 1; --=20 2.43.0