From nobody Tue Feb 10 00:02:43 2026 Received: from lelvem-ot02.ext.ti.com (lelvem-ot02.ext.ti.com [198.47.23.235]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DB9D521A429; Wed, 26 Feb 2025 12:43:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.235 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740573787; cv=none; b=jYdSGo3wlGAofgko7klvlM+pvL/klGq0qiPQw4L813F4cPRRyASlWAISZ/LvAq3gekGPaciPV9kMAc/LXybFEPNQiHWemi5tPZNbNRw27QQSUc7ror72hUjOjQ4Luw53BMxmU1yv/q4wqATAktW+mFCjNEwCFaJaiblv3+ib0fQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740573787; c=relaxed/simple; bh=j/ZRHVu/Jic01vLvIdq6javs16S/Alwf1UYgZQiw1Zk=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=b4p+/w/BF2grdmWC7ofHqgfpMsgSEuEHtZl0bB/cKqo5YJnDlKTujwIWGA5Z7v3sedtsCBCmnItfl6+4q0BKYjcVMvMffQGLttsiCNSSO2b3P17Y4fY53g15yYTsPheUmGYc+5AZvZA6EfxSC6QmfrSbBWeKFUsXW+T1zBCFO9A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=SKVX0r3M; arc=none smtp.client-ip=198.47.23.235 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="SKVX0r3M" Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelvem-ot02.ext.ti.com (8.15.2/8.15.2) with ESMTPS id 51QCh0MA2078710 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 26 Feb 2025 06:43:00 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1740573780; bh=T9VSMBrhriLT5QHSm3bHjmJYq/YAFXjWmMV0J0qZA4c=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=SKVX0r3MisqQCwcIdgyJdyEourwWHyh/c/q14RcpK1nKVw2maTiNxoeB+ywypLSGp 2XU7TrihleZKsXuUe80Fl7k+ZwIAIMWmxVgprSvHfaxJKo3NqxFn5qYWKeyi7+5DCg OF8NFeeOIlWFebopDQNJF3W7vKdRk3r3kQf4zISA= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 51QCh0W3026142 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 26 Feb 2025 06:43:00 -0600 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 26 Feb 2025 06:43:00 -0600 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 26 Feb 2025 06:43:00 -0600 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [10.24.72.113]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 51QCgkI3094589; Wed, 26 Feb 2025 06:42:57 -0600 From: Siddharth Vadapalli To: , , , , , CC: , , , , Subject: [PATCH v2 3/3] arm64: dts: ti: k3-j784s4-j742s2-evm: Add overlay to enable USB0 Type-A Date: Wed, 26 Feb 2025 18:12:45 +0530 Message-ID: <20250226124245.9856-4-s-vadapalli@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250226124245.9856-1-s-vadapalli@ti.com> References: <20250226124245.9856-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" The USB0 instance of the USB controller on both the J742S2 EVM and the J784S4 EVM supports a single USB interface at a time among the following: 1. USB3.1 Gen1 Type C interface 2. Two USB2.0 Type A interfaces via an on-board USB Hub. By default, the USB3.1 Gen1 Type C interface is supported on both of the EVMs. Enable the USB2.0 Type A interface by configuring the USB2.0_MUX_SEL mux. Additionally, set the Dual-Role Mode to Host since a Type-A interface is only associated with the Host Mode of operation. Signed-off-by: Siddharth Vadapalli --- v1: https://patchwork.kernel.org/project/linux-arm-kernel/patch/20250202093636.= 2699064-4-s-vadapalli@ti.com/ No changes since v1. Regards, Siddharth. arch/arm64/boot/dts/ti/Makefile | 7 +++++ .../ti/k3-j784s4-j742s2-evm-usb0-type-a.dtso | 29 +++++++++++++++++++ 2 files changed, 36 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-usb0-type-a= .dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makef= ile index dbeb5d7401f7..91fdb2dfe1be 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -129,6 +129,7 @@ dtb-$(CONFIG_ARCH_K3) +=3D k3-j784s4-evm-pcie0-pcie1-ep= .dtbo dtb-$(CONFIG_ARCH_K3) +=3D k3-j784s4-evm-quad-port-eth-exp1.dtbo dtb-$(CONFIG_ARCH_K3) +=3D k3-j784s4-evm-usxgmii-exp1-exp2.dtbo dtb-$(CONFIG_ARCH_K3) +=3D k3-j784s4-j742s2-evm-pcie-ntb.dtbo +dtb-$(CONFIG_ARCH_K3) +=3D k3-j784s4-j742s2-evm-usb0-type-a.dtbo =20 # Boards with J742S2 SoC dtb-$(CONFIG_ARCH_K3) +=3D k3-j742s2-evm.dtb @@ -215,6 +216,8 @@ k3-j721s2-evm-pcie1-ep-dtbs :=3D k3-j721s2-common-proc-= board.dtb \ k3-j721s2-evm-pcie1-ep.dtbo k3-j742s2-evm-pcie-ntb-dtbs :=3D k3-j742s2-evm.dtb \ k3-j784s4-j742s2-evm-pcie-ntb.dtbo +k3-j742s2-evm-usb0-type-a-dtbs :=3D k3-j742s2-evm.dtb \ + k3-j784s4-j742s2-evm-usb0-type-a.dtbo k3-j784s4-evm-pcie-ntb-dtbs :=3D k3-j784s4-evm.dtb \ k3-j784s4-j742s2-evm-pcie-ntb.dtbo k3-j784s4-evm-pcie0-pcie1-ep-dtbs :=3D k3-j784s4-evm.dtb \ @@ -223,6 +226,8 @@ k3-j784s4-evm-quad-port-eth-exp1-dtbs :=3D k3-j784s4-ev= m.dtb \ k3-j784s4-evm-quad-port-eth-exp1.dtbo k3-j784s4-evm-usxgmii-exp1-exp2-dtbs :=3D k3-j784s4-evm.dtb \ k3-j784s4-evm-usxgmii-exp1-exp2.dtbo +k3-j784s4-evm-usb0-type-a-dtbs :=3D k3-j784s4-evm.dtb \ + k3-j784s4-j742s2-evm-usb0-type-a.dtbo dtb- +=3D k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am625-beagleplay-csi2-tevi-ov5640.dtb \ k3-am625-sk-csi2-imx219.dtb \ @@ -253,9 +258,11 @@ dtb- +=3D k3-am625-beagleplay-csi2-ov5640.dtb \ k3-j721e-sk-csi2-dual-imx219.dtb \ k3-j721s2-evm-pcie1-ep.dtb \ k3-j742s2-evm-pcie-ntb.dtb \ + k3-j742s2-evm-usb0-type-a.dtb \ k3-j784s4-evm-pcie-ntb.dtb \ k3-j784s4-evm-pcie0-pcie1-ep.dtb \ k3-j784s4-evm-quad-port-eth-exp1.dtb \ + k3-j784s4-evm-usb0-type-a.dtb \ k3-j784s4-evm-usxgmii-exp1-exp2.dtb =20 # Enable support for device-tree overlays diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-usb0-type-a.dtso b= /arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-usb0-type-a.dtso new file mode 100644 index 000000000000..ba15d72d86d6 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-usb0-type-a.dtso @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * DT Overlay for enabling USB0 instance of USB on J784S4 and J742S2 EVMs = for + * Host Mode of operation with the Type-A Connector. + * + * J784S4 EVM Product Link: https://www.ti.com/tool/J784S4XEVM + * J742S2 EVM Product Link: https://www.ti.com/tool/J742S2XH01EVM + * + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&exp2 { + p12-hog { + /* P12 - USB2.0_MUX_SEL */ + gpio-hog; + gpios =3D <12 GPIO_ACTIVE_HIGH>; + output-high; + line-name =3D "USB2.0_MUX_SEL"; + }; +}; + +&usb0 { + dr_mode =3D "host"; +}; --=20 2.34.1