From nobody Fri Dec 19 04:03:17 2025 Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6E7D42153D1; Wed, 26 Feb 2025 12:43:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740573786; cv=none; b=Agk1l5+NE7dqgehixuAOuIfsFq1xpnH8rbnYw+NvS/vfR/PBOhHH0GZz24oNTDyPnwaM39HNCz3j3buolwp3QPfYzm8rs5PGWfruYpjFEP84/7tcT681KNKKK1dOd8qJapTpDDfJXNCr0HqxLk3g4QFWTpSe+xcxDa7H040JP/g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740573786; c=relaxed/simple; bh=Qbhck5mS6GaBXSveDh/psL3NZTL5zZOKulYq0ktGfOo=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=QTW2/hVIWJyjb7IAP0fjnCRJc7lq8k0EXc9PB6Ba5hIuJOj91QERPb93oObQDfKs7yPFKjpOpkbuI8k+SuppVDhSxVJaOkrWZcipSsJOIlzfLOk1o8DZOCoXlv4QBBSxd3AA2uusOyEY9VludKcAX7ojHJtoIDuT6mEs9aVdoFI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=h04EESzj; arc=none smtp.client-ip=198.47.23.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="h04EESzj" Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelvem-ot01.ext.ti.com (8.15.2/8.15.2) with ESMTPS id 51QCgr291545397 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Wed, 26 Feb 2025 06:42:53 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1740573773; bh=3/MzlDt4nccr9eA0LZJQ9BAeCHX8O6hwCYvepjAbJsE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=h04EESzjT6nkM5ceC6GMeCJJS7bFVk5oHKdbhdpDXyeaR15duQkpX4IeWjxmnqwxQ xsS8xXygothqGlagWejBY9XXPUKdp6hIRAqzAwCajhjNRVKVG2S4nk0wZprWeXsq69 LdZXcB2RRxa+ihHiCTBWcgHV5urwO1cV6nCJOAZg= Received: from DLEE115.ent.ti.com (dlee115.ent.ti.com [157.170.170.26]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTP id 51QCgrmW051671; Wed, 26 Feb 2025 06:42:53 -0600 Received: from DLEE109.ent.ti.com (157.170.170.41) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 26 Feb 2025 06:42:53 -0600 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 26 Feb 2025 06:42:53 -0600 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [10.24.72.113]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 51QCgkI1094589; Wed, 26 Feb 2025 06:42:50 -0600 From: Siddharth Vadapalli To: , , , , , CC: , , , , Subject: [PATCH v2 1/3] arm64: dts: ti: k3-j721e-evm: Add overlay for PCIe NTB functionality Date: Wed, 26 Feb 2025 18:12:43 +0530 Message-ID: <20250226124245.9856-2-s-vadapalli@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250226124245.9856-1-s-vadapalli@ti.com> References: <20250226124245.9856-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" PCIe NTB (Non-Transparent-Bridge) allows connecting the memory of multiple PCIe Hosts (Root-Complex). The number of such hosts is determined by the number of PCIe instances configured for NTB operation on the device which intends to enable NTB functionality. Add a device-tree overlay to configure PCIE0 and PCIE1 instances of PCIe on J721E EVM for NTB operation. This shall allow connecting the memory of two PCIe Hosts via PCIE0 and PCIE1 on J721E EVM. Signed-off-by: Siddharth Vadapalli --- v1: https://patchwork.kernel.org/project/linux-arm-kernel/patch/20250202093636.= 2699064-2-s-vadapalli@ti.com/ Changes since v1: - s/epf_bus/epf-bus since node names shouldn't contain underscores. Regards, Siddharth. arch/arm64/boot/dts/ti/Makefile | 4 + .../boot/dts/ti/k3-j721e-evm-pcie-ntb.dtso | 91 +++++++++++++++++++ 2 files changed, 95 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-j721e-evm-pcie-ntb.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makef= ile index 8a4bdf87e2d4..1097ab30f5a9 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -102,6 +102,7 @@ dtb-$(CONFIG_ARCH_K3) +=3D k3-j721e-beagleboneai64.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-j721e-common-proc-board-infotainment.dtbo dtb-$(CONFIG_ARCH_K3) +=3D k3-j721e-evm.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-j721e-evm-gesi-exp-board.dtbo +dtb-$(CONFIG_ARCH_K3) +=3D k3-j721e-evm-pcie-ntb.dtbo dtb-$(CONFIG_ARCH_K3) +=3D k3-j721e-evm-pcie0-ep.dtbo dtb-$(CONFIG_ARCH_K3) +=3D k3-j721e-evm-pcie1-ep.dtbo dtb-$(CONFIG_ARCH_K3) +=3D k3-j721e-sk.dtb @@ -201,6 +202,8 @@ k3-j7200-evm-pcie1-ep-dtbs :=3D k3-j7200-common-proc-bo= ard.dtb \ k3-j7200-evm-pcie1-ep.dtbo k3-j721e-common-proc-board-infotainment-dtbs :=3D k3-j721e-common-proc-boa= rd.dtb \ k3-j721e-common-proc-board-infotainment.dtbo +k3-j721e-evm-pcie-ntb-dtbs :=3D k3-j721e-common-proc-board.dtb \ + k3-j721e-evm-pcie-ntb.dtbo k3-j721e-evm-pcie0-ep-dtbs :=3D k3-j721e-common-proc-board.dtb \ k3-j721e-evm-pcie0-ep.dtbo k3-j721e-evm-pcie1-ep-dtbs :=3D k3-j721e-common-proc-board.dtb \ @@ -239,6 +242,7 @@ dtb- +=3D k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am69-sk-pcie0-ep.dtb \ k3-j7200-evm-pcie1-ep.dtb \ k3-j721e-common-proc-board-infotainment.dtb \ + k3-j721e-evm-pcie-ntb.dtb \ k3-j721e-evm-pcie0-ep.dtb \ k3-j721e-evm-pcie1-ep.dtb \ k3-j721e-sk-csi2-dual-imx219.dtb \ diff --git a/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie-ntb.dtso b/arch/arm64= /boot/dts/ti/k3-j721e-evm-pcie-ntb.dtso new file mode 100644 index 000000000000..9b6b3e153e91 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie-ntb.dtso @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * DT Overlay for enabling NTB functionality using PCIE0 and PCIE1 instanc= es of + * PCIe on the J7 common processor board. + * + * J7 Common Processor Board Product Link: https://www.ti.com/tool/J721EXC= PXEVM + * + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "k3-pinctrl.h" + +&{/} { + epf-bus { + compatible =3D "pci-epf-bus"; + + ntb { + compatible =3D "pci-epf-ntb"; + epcs =3D <&pcie0_ep>, <&pcie1_ep>; + epc-names =3D "primary", "secondary"; + vendor-id =3D /bits/ 16 <0x104c>; + device-id =3D /bits/ 16 <0xb00d>; + num-mws =3D <4>; + mws-size =3D <0x100000>, <0x100000>, <0x100000>, <0x100000>; + }; + }; +}; + +&pcie0_rc { + status =3D "disabled"; +}; + +&pcie1_rc { + status =3D "disabled"; +}; + +&cbass_main { + #address-cells =3D <2>; + #size-cells =3D <2>; + interrupt-parent =3D <&gic500>; + + pcie0_ep: pcie-ep@2900000 { + compatible =3D "ti,j721e-pcie-ep"; + reg =3D <0x00 0x02900000 0x00 0x1000>, + <0x00 0x02907000 0x00 0x400>, + <0x00 0x0d000000 0x00 0x00800000>, + <0x00 0x10000000 0x00 0x08000000>; + reg-names =3D "intd_cfg", "user_cfg", "reg", "mem"; + interrupt-names =3D "link_state"; + interrupts =3D ; + max-link-speed =3D <3>; + num-lanes =3D <1>; + power-domains =3D <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 239 1>; + clock-names =3D "fck"; + max-functions =3D /bits/ 8 <6>; + max-virtual-functions =3D /bits/ 8 <4 4 4 4 0 0>; + dma-coherent; + phys =3D <&serdes0_pcie_link>; + phy-names =3D "pcie-phy"; + ti,syscon-pcie-ctrl =3D <&scm_conf 0x4070>; + }; + + pcie1_ep: pcie-ep@2910000 { + compatible =3D "ti,j721e-pcie-ep"; + reg =3D <0x00 0x02910000 0x00 0x1000>, + <0x00 0x02917000 0x00 0x400>, + <0x00 0x0d800000 0x00 0x00800000>, + <0x00 0x18000000 0x00 0x08000000>; + reg-names =3D "intd_cfg", "user_cfg", "reg", "mem"; + interrupt-names =3D "link_state"; + interrupts =3D ; + max-link-speed =3D <3>; + num-lanes =3D <2>; + power-domains =3D <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 240 1>; + clock-names =3D "fck"; + max-functions =3D /bits/ 8 <6>; + max-virtual-functions =3D /bits/ 8 <4 4 4 4 0 0>; + dma-coherent; + phys =3D <&serdes1_pcie_link>; + phy-names =3D "pcie-phy"; + ti,syscon-pcie-ctrl =3D <&scm_conf 0x4074>; + }; +}; --=20 2.34.1 From nobody Fri Dec 19 04:03:17 2025 Received: from lelvem-ot02.ext.ti.com (lelvem-ot02.ext.ti.com [198.47.23.235]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 34F07215769; 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charset="utf-8" PCIe NTB (Non-Transparent-Bridge) allows connecting the memory of multiple PCIe Hosts (Root-Complex). The number of such hosts is determined by the number of PCIe instances configured for NTB operation on the device which intends to enable NTB functionality. Add a device-tree overlay to configure PCIE0 and PCIE1 instances of PCIe on either J784S4 EVM or J742S2 EVM for NTB operation. This shall allow connecting the memory of two PCIe Hosts via PCIE0 and PCIE1 on J784S4 EVM or J742S2 EVM respectively. Signed-off-by: Siddharth Vadapalli --- v1: https://patchwork.kernel.org/project/linux-arm-kernel/patch/20250202093636.= 2699064-3-s-vadapalli@ti.com/ Changes since v1: - s/epf_bus/epf-bus since node names shouldn't contain underscores. Regards, Siddharth. arch/arm64/boot/dts/ti/Makefile | 7 ++ .../dts/ti/k3-j784s4-j742s2-evm-pcie-ntb.dtso | 92 +++++++++++++++++++ 2 files changed, 99 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-pcie-ntb.dt= so diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makef= ile index 1097ab30f5a9..dbeb5d7401f7 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -128,6 +128,7 @@ dtb-$(CONFIG_ARCH_K3) +=3D k3-j784s4-evm.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-j784s4-evm-pcie0-pcie1-ep.dtbo dtb-$(CONFIG_ARCH_K3) +=3D k3-j784s4-evm-quad-port-eth-exp1.dtbo dtb-$(CONFIG_ARCH_K3) +=3D k3-j784s4-evm-usxgmii-exp1-exp2.dtbo +dtb-$(CONFIG_ARCH_K3) +=3D k3-j784s4-j742s2-evm-pcie-ntb.dtbo =20 # Boards with J742S2 SoC dtb-$(CONFIG_ARCH_K3) +=3D k3-j742s2-evm.dtb @@ -212,6 +213,10 @@ k3-j721e-sk-csi2-dual-imx219-dtbs :=3D k3-j721e-sk.dtb= \ k3-j721e-sk-csi2-dual-imx219.dtbo k3-j721s2-evm-pcie1-ep-dtbs :=3D k3-j721s2-common-proc-board.dtb \ k3-j721s2-evm-pcie1-ep.dtbo +k3-j742s2-evm-pcie-ntb-dtbs :=3D k3-j742s2-evm.dtb \ + k3-j784s4-j742s2-evm-pcie-ntb.dtbo +k3-j784s4-evm-pcie-ntb-dtbs :=3D k3-j784s4-evm.dtb \ + k3-j784s4-j742s2-evm-pcie-ntb.dtbo k3-j784s4-evm-pcie0-pcie1-ep-dtbs :=3D k3-j784s4-evm.dtb \ k3-j784s4-evm-pcie0-pcie1-ep.dtbo k3-j784s4-evm-quad-port-eth-exp1-dtbs :=3D k3-j784s4-evm.dtb \ @@ -247,6 +252,8 @@ dtb- +=3D k3-am625-beagleplay-csi2-ov5640.dtb \ k3-j721e-evm-pcie1-ep.dtb \ k3-j721e-sk-csi2-dual-imx219.dtb \ k3-j721s2-evm-pcie1-ep.dtb \ + k3-j742s2-evm-pcie-ntb.dtb \ + k3-j784s4-evm-pcie-ntb.dtb \ k3-j784s4-evm-pcie0-pcie1-ep.dtb \ k3-j784s4-evm-quad-port-eth-exp1.dtb \ k3-j784s4-evm-usxgmii-exp1-exp2.dtb diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-pcie-ntb.dtso b/ar= ch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-pcie-ntb.dtso new file mode 100644 index 000000000000..46cbddcf612e --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-pcie-ntb.dtso @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * DT Overlay for enabling NTB functionality using PCIE0 and PCIE1 instanc= es of + * PCIe on the J784S4 EVM and the J742S2 EVM. + * + * J784S4 EVM Product Link: https://www.ti.com/tool/J784S4XEVM + * J742S2 EVM Product Link: https://www.ti.com/tool/J742S2XH01EVM + * + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "k3-pinctrl.h" + +&{/} { + epf-bus { + compatible =3D "pci-epf-bus"; + + ntb { + compatible =3D "pci-epf-ntb"; + epcs =3D <&pcie0_ep>, <&pcie1_ep>; + epc-names =3D "primary", "secondary"; + vendor-id =3D /bits/ 16 <0x104c>; + device-id =3D /bits/ 16 <0xb012>; + num-mws =3D <4>; + mws-size =3D <0x100000>, <0x100000>, <0x100000>, <0x100000>; + }; + }; +}; + +&pcie0_rc { + status =3D "disabled"; +}; + +&pcie1_rc { + status =3D "disabled"; +}; + +&cbass_main { + #address-cells =3D <2>; + #size-cells =3D <2>; + interrupt-parent =3D <&gic500>; + + pcie0_ep: pcie-ep@2900000 { + compatible =3D "ti,j784s4-pcie-ep"; + reg =3D <0x00 0x02900000 0x00 0x1000>, + <0x00 0x02907000 0x00 0x400>, + <0x00 0x0d000000 0x00 0x00800000>, + <0x00 0x10000000 0x00 0x08000000>; + reg-names =3D "intd_cfg", "user_cfg", "reg", "mem"; + interrupt-names =3D "link_state"; + interrupts =3D ; + max-link-speed =3D <3>; + num-lanes =3D <4>; + power-domains =3D <&k3_pds 332 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 332 0>; + clock-names =3D "fck"; + max-functions =3D /bits/ 8 <6>; + max-virtual-functions =3D /bits/ 8 <4 4 4 4 0 0>; + dma-coherent; + phys =3D <&serdes1_pcie0_link>; + phy-names =3D "pcie-phy"; + ti,syscon-pcie-ctrl =3D <&pcie0_ctrl 0x0>; + }; + + pcie1_ep: pcie-ep@2910000 { + compatible =3D "ti,j784s4-pcie-ep"; + reg =3D <0x00 0x02910000 0x00 0x1000>, + <0x00 0x02917000 0x00 0x400>, + <0x00 0x0d800000 0x00 0x00800000>, + <0x00 0x18000000 0x00 0x08000000>; + reg-names =3D "intd_cfg", "user_cfg", "reg", "mem"; + interrupt-names =3D "link_state"; + interrupts =3D ; + max-link-speed =3D <3>; + num-lanes =3D <2>; + power-domains =3D <&k3_pds 333 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 333 0>; + clock-names =3D "fck"; + max-functions =3D /bits/ 8 <6>; + max-virtual-functions =3D /bits/ 8 <4 4 4 4 0 0>; + dma-coherent; + phys =3D <&serdes0_pcie1_link>; + phy-names =3D "pcie-phy"; + ti,syscon-pcie-ctrl =3D <&pcie1_ctrl 0x0>; + }; +}; --=20 2.34.1 From nobody Fri Dec 19 04:03:17 2025 Received: from lelvem-ot02.ext.ti.com (lelvem-ot02.ext.ti.com [198.47.23.235]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DB9D521A429; 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Wed, 26 Feb 2025 06:43:00 -0600 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 26 Feb 2025 06:43:00 -0600 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 26 Feb 2025 06:43:00 -0600 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [10.24.72.113]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 51QCgkI3094589; Wed, 26 Feb 2025 06:42:57 -0600 From: Siddharth Vadapalli To: , , , , , CC: , , , , Subject: [PATCH v2 3/3] arm64: dts: ti: k3-j784s4-j742s2-evm: Add overlay to enable USB0 Type-A Date: Wed, 26 Feb 2025 18:12:45 +0530 Message-ID: <20250226124245.9856-4-s-vadapalli@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250226124245.9856-1-s-vadapalli@ti.com> References: <20250226124245.9856-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" The USB0 instance of the USB controller on both the J742S2 EVM and the J784S4 EVM supports a single USB interface at a time among the following: 1. USB3.1 Gen1 Type C interface 2. Two USB2.0 Type A interfaces via an on-board USB Hub. By default, the USB3.1 Gen1 Type C interface is supported on both of the EVMs. Enable the USB2.0 Type A interface by configuring the USB2.0_MUX_SEL mux. Additionally, set the Dual-Role Mode to Host since a Type-A interface is only associated with the Host Mode of operation. Signed-off-by: Siddharth Vadapalli --- v1: https://patchwork.kernel.org/project/linux-arm-kernel/patch/20250202093636.= 2699064-4-s-vadapalli@ti.com/ No changes since v1. Regards, Siddharth. arch/arm64/boot/dts/ti/Makefile | 7 +++++ .../ti/k3-j784s4-j742s2-evm-usb0-type-a.dtso | 29 +++++++++++++++++++ 2 files changed, 36 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-usb0-type-a= .dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makef= ile index dbeb5d7401f7..91fdb2dfe1be 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -129,6 +129,7 @@ dtb-$(CONFIG_ARCH_K3) +=3D k3-j784s4-evm-pcie0-pcie1-ep= .dtbo dtb-$(CONFIG_ARCH_K3) +=3D k3-j784s4-evm-quad-port-eth-exp1.dtbo dtb-$(CONFIG_ARCH_K3) +=3D k3-j784s4-evm-usxgmii-exp1-exp2.dtbo dtb-$(CONFIG_ARCH_K3) +=3D k3-j784s4-j742s2-evm-pcie-ntb.dtbo +dtb-$(CONFIG_ARCH_K3) +=3D k3-j784s4-j742s2-evm-usb0-type-a.dtbo =20 # Boards with J742S2 SoC dtb-$(CONFIG_ARCH_K3) +=3D k3-j742s2-evm.dtb @@ -215,6 +216,8 @@ k3-j721s2-evm-pcie1-ep-dtbs :=3D k3-j721s2-common-proc-= board.dtb \ k3-j721s2-evm-pcie1-ep.dtbo k3-j742s2-evm-pcie-ntb-dtbs :=3D k3-j742s2-evm.dtb \ k3-j784s4-j742s2-evm-pcie-ntb.dtbo +k3-j742s2-evm-usb0-type-a-dtbs :=3D k3-j742s2-evm.dtb \ + k3-j784s4-j742s2-evm-usb0-type-a.dtbo k3-j784s4-evm-pcie-ntb-dtbs :=3D k3-j784s4-evm.dtb \ k3-j784s4-j742s2-evm-pcie-ntb.dtbo k3-j784s4-evm-pcie0-pcie1-ep-dtbs :=3D k3-j784s4-evm.dtb \ @@ -223,6 +226,8 @@ k3-j784s4-evm-quad-port-eth-exp1-dtbs :=3D k3-j784s4-ev= m.dtb \ k3-j784s4-evm-quad-port-eth-exp1.dtbo k3-j784s4-evm-usxgmii-exp1-exp2-dtbs :=3D k3-j784s4-evm.dtb \ k3-j784s4-evm-usxgmii-exp1-exp2.dtbo +k3-j784s4-evm-usb0-type-a-dtbs :=3D k3-j784s4-evm.dtb \ + k3-j784s4-j742s2-evm-usb0-type-a.dtbo dtb- +=3D k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am625-beagleplay-csi2-tevi-ov5640.dtb \ k3-am625-sk-csi2-imx219.dtb \ @@ -253,9 +258,11 @@ dtb- +=3D k3-am625-beagleplay-csi2-ov5640.dtb \ k3-j721e-sk-csi2-dual-imx219.dtb \ k3-j721s2-evm-pcie1-ep.dtb \ k3-j742s2-evm-pcie-ntb.dtb \ + k3-j742s2-evm-usb0-type-a.dtb \ k3-j784s4-evm-pcie-ntb.dtb \ k3-j784s4-evm-pcie0-pcie1-ep.dtb \ k3-j784s4-evm-quad-port-eth-exp1.dtb \ + k3-j784s4-evm-usb0-type-a.dtb \ k3-j784s4-evm-usxgmii-exp1-exp2.dtb =20 # Enable support for device-tree overlays diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-usb0-type-a.dtso b= /arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-usb0-type-a.dtso new file mode 100644 index 000000000000..ba15d72d86d6 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-usb0-type-a.dtso @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * DT Overlay for enabling USB0 instance of USB on J784S4 and J742S2 EVMs = for + * Host Mode of operation with the Type-A Connector. + * + * J784S4 EVM Product Link: https://www.ti.com/tool/J784S4XEVM + * J742S2 EVM Product Link: https://www.ti.com/tool/J742S2XH01EVM + * + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&exp2 { + p12-hog { + /* P12 - USB2.0_MUX_SEL */ + gpio-hog; + gpios =3D <12 GPIO_ACTIVE_HIGH>; + output-high; + line-name =3D "USB2.0_MUX_SEL"; + }; +}; + +&usb0 { + dr_mode =3D "host"; +}; --=20 2.34.1