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([188.163.112.51]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-abed205e53fsm299771266b.159.2025.02.26.02.56.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Feb 2025 02:56:39 -0800 (PST) From: Svyatoslav Ryhel To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Jonathan Hunter , Svyatoslav Ryhel Cc: devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 5/6] ARM: tegra124: Add DSI-A and DSI-B nodes Date: Wed, 26 Feb 2025 12:56:14 +0200 Message-ID: <20250226105615.61087-6-clamor95@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250226105615.61087-1-clamor95@gmail.com> References: <20250226105615.61087-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Bind DSI devices and MIPI calibration. Signed-off-by: Svyatoslav Ryhel --- arch/arm/boot/dts/nvidia/tegra124.dtsi | 40 ++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm/boot/dts/nvidia/tegra124.dtsi b/arch/arm/boot/dts/nvi= dia/tegra124.dtsi index 8f1fff373461..ec4f0e346b2b 100644 --- a/arch/arm/boot/dts/nvidia/tegra124.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra124.dtsi @@ -165,6 +165,22 @@ hdmi: hdmi@54280000 { status =3D "disabled"; }; =20 + dsia: dsi@54300000 { + compatible =3D "nvidia,tegra124-dsi"; + reg =3D <0x0 0x54300000 0x0 0x00040000>; + clocks =3D <&tegra_car TEGRA124_CLK_DSIA>, + <&tegra_car TEGRA124_CLK_DSIALP>, + <&tegra_car TEGRA124_CLK_PLL_D_OUT0>; + clock-names =3D "dsi", "lp", "parent"; + resets =3D <&tegra_car 48>; + reset-names =3D "dsi"; + nvidia,mipi-calibrate =3D <&mipi 0x060>; /* DSIA & DSIB pads */ + status =3D "disabled"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + vic@54340000 { compatible =3D "nvidia,tegra124-vic"; reg =3D <0x0 0x54340000 0x0 0x00040000>; @@ -177,6 +193,22 @@ vic@54340000 { iommus =3D <&mc TEGRA_SWGROUP_VIC>; }; =20 + dsib: dsi@54400000 { + compatible =3D "nvidia,tegra124-dsi"; + reg =3D <0x0 0x54400000 0x0 0x00040000>; + clocks =3D <&tegra_car TEGRA124_CLK_DSIB>, + <&tegra_car TEGRA124_CLK_DSIBLP>, + <&tegra_car TEGRA124_CLK_PLL_D_OUT0>; + clock-names =3D "dsi", "lp", "parent"; + resets =3D <&tegra_car 82>; + reset-names =3D "dsi"; + nvidia,mipi-calibrate =3D <&mipi 0x180>; /* DSIC & DSID pads */ + status =3D "disabled"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + sor@54540000 { compatible =3D "nvidia,tegra124-sor"; reg =3D <0x0 0x54540000 0x0 0x00040000>; @@ -938,6 +970,14 @@ throttle_heavy: heavy { }; }; =20 + mipi: mipi@700e3000 { + compatible =3D "nvidia,tegra124-mipi"; + reg =3D <0x0 0x700e3000 0x0 0x100>; + clocks =3D <&tegra_car TEGRA124_CLK_MIPI_CAL>; + clock-names =3D "mipi-cal"; + #nvidia,mipi-calibrate-cells =3D <1>; + }; + dfll: clock@70110000 { compatible =3D "nvidia,tegra124-dfll"; reg =3D <0 0x70110000 0 0x100>, /* DFLL control */ --=20 2.43.0