From nobody Fri Dec 19 07:16:40 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9245826F440; Wed, 26 Feb 2025 07:50:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740556223; cv=none; b=B9qixW3a50uFBTfRrLpdl2zPVvYjuDsqPAOZkqmeNJCcKAlRYjq+EqDVpVczLTgC2rBijZgI2dlS73/j5puzI7i9tl93IsKKye2POiboJV8ZzSaVFLtfyp0s26lNUETQwz4Wr8LT4E72oWm5Gl39FHXvvImJM7j1jZNXrU362ok= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740556223; c=relaxed/simple; bh=J2WrRdXsHM4g/4BW0LGzBua9ax0dXvOez2jZneAIugs=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=BuCP2dNgTdNGiORKhOigLeeG5YbhSvqWg/HFEdFzJgy0PFa6mTBr4TPh89kK5MtOD2x0a1LxkHhtJoFMSXaBi90oID00vF9B/VyN5Qx2y/qgmQePGRdvvl0r92+6yDhqGCVkoNrT9J5FlXiL9Sm4Fxfg/Is9+9jl8ltfgdrLPJI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Om2U0ici; arc=none smtp.client-ip=192.198.163.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Om2U0ici" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1740556222; x=1772092222; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=J2WrRdXsHM4g/4BW0LGzBua9ax0dXvOez2jZneAIugs=; b=Om2U0icihYjlx4zTBjsu0+EZuP/oZjUr+A34XAFWt/lez5pv/+cimMqF 4qBX8p+D3Pk/8xsRx9R0U2YkmIMV6MDoyLMLeWovbrQdwyfwvGp+3+zAo GEe5lrQUkyOYZNdMidNjhphcTBGoaBTisMJDQq391WcBD1zACgMgod4Cu SYuSzSp90FAzcIzH2nF/EJDa3pLKPPZeA+ZWC2q4sg9NRrOjWYKLAouOd v6NlD9Doq1AC0o7vv8uG0AY6/RJcCqwJu4uYt9zk2MxKtZkvKmrlj58x3 5CjYTHaFDxJjMtTbxKyr1c9PsMe2twqpQFFpTR8P0dgDMHe+AnFsi2A8e w==; X-CSE-ConnectionGUID: jvSocf2ASAeOkp4ZebXGRA== X-CSE-MsgGUID: DMbbzdk2Sz2WQMvn91K9Kw== X-IronPort-AV: E=McAfee;i="6700,10204,11356"; a="45305126" X-IronPort-AV: E=Sophos;i="6.13,316,1732608000"; d="scan'208";a="45305126" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Feb 2025 23:50:20 -0800 X-CSE-ConnectionGUID: QfjVcDevS3id+luAHduEVg== X-CSE-MsgGUID: k29dyh/ITGCV0Y+PbmRcEg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="120743019" Received: from yongliang-ubuntu20-ilbpg12.png.intel.com ([10.88.227.39]) by fmviesa003.fm.intel.com with ESMTP; 25 Feb 2025 23:50:13 -0800 From: Choong Yong Liang To: Simon Horman , Jose Abreu , Jose Abreu , David E Box , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H . Peter Anvin" , Rajneesh Bhardwaj , David E Box , Andrew Lunn , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , Jiawen Wu , Mengyuan Lou , Heiner Kallweit , Russell King , Hans de Goede , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= , Richard Cochran , Serge Semin Cc: x86@kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, platform-driver-x86@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org Subject: [PATCH net-next v8 3/6] arch: x86: add IPC mailbox accessor function and add SoC register access Date: Wed, 26 Feb 2025 15:48:34 +0800 Message-Id: <20250226074837.1679988-4-yong.liang.choong@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250226074837.1679988-1-yong.liang.choong@linux.intel.com> References: <20250226074837.1679988-1-yong.liang.choong@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: "David E. Box" - Exports intel_pmc_ipc() for host access to the PMC IPC mailbox - Enables the host to access specific SoC registers through the PMC firmware using IPC commands. This access method is necessary for registers that are not available through direct Memory-Mapped I/O (MMIO), which is used for other accessible parts of the PMC. Signed-off-by: David E. Box Signed-off-by: Chao Qin Signed-off-by: Choong Yong Liang --- MAINTAINERS | 1 + .../linux/platform_data/x86/intel_pmc_ipc.h | 94 +++++++++++++++++++ 2 files changed, 95 insertions(+) create mode 100644 include/linux/platform_data/x86/intel_pmc_ipc.h diff --git a/MAINTAINERS b/MAINTAINERS index 8019d5a97546..aff084824b89 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11864,6 +11864,7 @@ L: platform-driver-x86@vger.kernel.org S: Maintained F: Documentation/ABI/testing/sysfs-platform-intel-pmc F: drivers/platform/x86/intel/pmc/ +F: linux/platform_data/x86/intel_pmc_ipc.h =20 INTEL PMIC GPIO DRIVERS M: Andy Shevchenko diff --git a/include/linux/platform_data/x86/intel_pmc_ipc.h b/include/linu= x/platform_data/x86/intel_pmc_ipc.h new file mode 100644 index 000000000000..6e603a8c075f --- /dev/null +++ b/include/linux/platform_data/x86/intel_pmc_ipc.h @@ -0,0 +1,94 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Intel Core SoC Power Management Controller Header File + * + * Copyright (c) 2025, Intel Corporation. + * All Rights Reserved. + * + */ +#ifndef INTEL_PMC_IPC_H +#define INTEL_PMC_IPC_H +#include + +#define IPC_SOC_REGISTER_ACCESS 0xAA +#define IPC_SOC_SUB_CMD_READ 0x00 +#define IPC_SOC_SUB_CMD_WRITE 0x01 +#define PMC_IPCS_PARAM_COUNT 7 +#define VALID_IPC_RESPONSE 5 + +struct pmc_ipc_cmd { + u32 cmd; + u32 sub_cmd; + u32 size; + u32 wbuf[4]; +}; + +struct pmc_ipc_rbuf { + u32 buf[4]; +}; + +/** + * intel_pmc_ipc() - PMC IPC Mailbox accessor + * @ipc_cmd: Prepared input command to send + * @rbuf: Allocated array for returned IPC data + * + * Return: 0 on success. Non-zero on mailbox error + */ +static inline int intel_pmc_ipc(struct pmc_ipc_cmd *ipc_cmd, struct pmc_ip= c_rbuf *rbuf) +{ + struct acpi_buffer buffer =3D { ACPI_ALLOCATE_BUFFER, NULL }; + union acpi_object params[PMC_IPCS_PARAM_COUNT] =3D { + {.type =3D ACPI_TYPE_INTEGER,}, + {.type =3D ACPI_TYPE_INTEGER,}, + {.type =3D ACPI_TYPE_INTEGER,}, + {.type =3D ACPI_TYPE_INTEGER,}, + {.type =3D ACPI_TYPE_INTEGER,}, + {.type =3D ACPI_TYPE_INTEGER,}, + {.type =3D ACPI_TYPE_INTEGER,}, + }; + struct acpi_object_list arg_list =3D { PMC_IPCS_PARAM_COUNT, params }; + union acpi_object *obj; + int status; + + if (!ipc_cmd || !rbuf) + return -EINVAL; + + /* + * 0: IPC Command + * 1: IPC Sub Command + * 2: Size + * 3-6: Write Buffer for offset + */ + params[0].integer.value =3D ipc_cmd->cmd; + params[1].integer.value =3D ipc_cmd->sub_cmd; + params[2].integer.value =3D ipc_cmd->size; + params[3].integer.value =3D ipc_cmd->wbuf[0]; + params[4].integer.value =3D ipc_cmd->wbuf[1]; + params[5].integer.value =3D ipc_cmd->wbuf[2]; + params[6].integer.value =3D ipc_cmd->wbuf[3]; + + status =3D acpi_evaluate_object(NULL, "\\IPCS", &arg_list, &buffer); + if (ACPI_FAILURE(status)) + return -ENODEV; + + obj =3D buffer.pointer; + + if (obj && obj->type =3D=3D ACPI_TYPE_PACKAGE && + obj->package.count =3D=3D VALID_IPC_RESPONSE) { + const union acpi_object *objs =3D obj->package.elements; + + if ((u8)objs[0].integer.value !=3D 0) + return -EINVAL; + + rbuf->buf[0] =3D objs[1].integer.value; + rbuf->buf[1] =3D objs[2].integer.value; + rbuf->buf[2] =3D objs[3].integer.value; + rbuf->buf[3] =3D objs[4].integer.value; + } else { + return -EINVAL; + } + + return 0; +} + +#endif /* INTEL_PMC_IPC_H */ --=20 2.34.1