From nobody Sun Feb 8 21:16:52 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BB53219DF53 for ; Wed, 26 Feb 2025 06:16:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740550562; cv=none; b=fF8R6ptCVDNarPho2B4pSIKw/AkHx7Qic1rSaXVQHbPmJbmiGRaERQHuKaoooU4N8ND+LJK9N33StZqO2huPsIoie78BkLyI74pqycz1HMLv/3qEVwsYwbbcKdMh11wbebBlQPCRCt9qv5K7BvhC102bQNiQatUVH37SJjv8zwQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740550562; c=relaxed/simple; bh=+wmqNzsPb9JNb7hDRUOSQbXWp2AYZYjt9EsKtcDB9mg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=adjBbzY5Hr+VzT+WW8OALo3up61RbZYSyRv5jDz49xcUGGf7BhK/0tM2FjPDLM9VryMIIf76lzrjAGOqGMjQtye3moDDSUQsJMTUfDtj4wGajwDgy7VTrvhLPDeJsoSFg9Jk6bqBSncJSJhj9VJ53p4qiz3PCOJKIHF8ISVcNaU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=lAwU6wZd; arc=none smtp.client-ip=192.198.163.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="lAwU6wZd" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1740550561; x=1772086561; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+wmqNzsPb9JNb7hDRUOSQbXWp2AYZYjt9EsKtcDB9mg=; b=lAwU6wZdojB3z+Foa5jxvDXV39H64M1ykXSzjBoSLnRHvRiUrtM1fu2Y Z5vS/S0xC9Hvw6Nrg2UQtWGQhdvxL3P9B7pu6R+c4dEFHF1qA3uCucAyh LY2Jn897M2VB661ageL/Nu4iRfJYdsEBpcRRaPlD1IBncVmhRHcKqDQ3y pwrRugYYA2Bymqd7NZ0of16dQg9PfEozAuMZXFzKZXL8GxDjNR5VHVWxH UQWaU1HvcepmCxPhgwunkMIIznPhHEpFdDlvYy3LkZJuryGIFZTLucMnM kj5qHCM8YZMK5v4HYCN9aig7g+tpkSQuG3B8ZdH0FatzIwRezdUJriT99 A==; X-CSE-ConnectionGUID: dnwwHLymRMmkVvVsL4uwRA== X-CSE-MsgGUID: 0t3s7q+SSKSg9mq+vAb5+A== X-IronPort-AV: E=McAfee;i="6700,10204,11356"; a="41636473" X-IronPort-AV: E=Sophos;i="6.13,316,1732608000"; d="scan'208";a="41636473" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Feb 2025 22:16:01 -0800 X-CSE-ConnectionGUID: kRI8l5sJQL6q9HKMpfY+qA== X-CSE-MsgGUID: U3FvgqJcSYWr37upsTpAdQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,316,1732608000"; d="scan'208";a="147434825" Received: from jraag-z790m-itx-wifi.iind.intel.com ([10.190.239.23]) by orviesa002.jf.intel.com with ESMTP; 25 Feb 2025 22:15:58 -0800 From: Raag Jadav To: lee@kernel.org, giometti@enneenne.com, gregkh@linuxfoundation.org, andriy.shevchenko@linux.intel.com, raymond.tan@intel.com Cc: linux-kernel@vger.kernel.org, Raag Jadav Subject: [PATCH v1 1/4] pps: generators: tio: split pps_gen_tio.h Date: Wed, 26 Feb 2025 11:45:24 +0530 Message-Id: <20250226061527.3031250-2-raag.jadav@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250226061527.3031250-1-raag.jadav@intel.com> References: <20250226061527.3031250-1-raag.jadav@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Split macros and structure definition to header file for better maintainability. Signed-off-by: Raag Jadav Acked-by: Rodolfo Giometti Reviewed-by: Andy Shevchenko --- drivers/pps/generators/pps_gen_tio.c | 30 +------------------ drivers/pps/generators/pps_gen_tio.h | 45 ++++++++++++++++++++++++++++ 2 files changed, 46 insertions(+), 29 deletions(-) create mode 100644 drivers/pps/generators/pps_gen_tio.h diff --git a/drivers/pps/generators/pps_gen_tio.c b/drivers/pps/generators/= pps_gen_tio.c index 6c46b46c66cd..7f2aab1219af 100644 --- a/drivers/pps/generators/pps_gen_tio.c +++ b/drivers/pps/generators/pps_gen_tio.c @@ -5,8 +5,6 @@ * Copyright (C) 2024 Intel Corporation */ =20 -#include -#include #include #include #include @@ -21,33 +19,7 @@ =20 #include =20 -#define TIOCTL 0x00 -#define TIOCOMPV 0x10 -#define TIOEC 0x30 - -/* Control Register */ -#define TIOCTL_EN BIT(0) -#define TIOCTL_DIR BIT(1) -#define TIOCTL_EP GENMASK(3, 2) -#define TIOCTL_EP_RISING_EDGE FIELD_PREP(TIOCTL_EP, 0) -#define TIOCTL_EP_FALLING_EDGE FIELD_PREP(TIOCTL_EP, 1) -#define TIOCTL_EP_TOGGLE_EDGE FIELD_PREP(TIOCTL_EP, 2) - -/* Safety time to set hrtimer early */ -#define SAFE_TIME_NS (10 * NSEC_PER_MSEC) - -#define MAGIC_CONST (NSEC_PER_SEC - SAFE_TIME_NS) -#define ART_HW_DELAY_CYCLES 2 - -struct pps_tio { - struct pps_gen_source_info gen_info; - struct pps_gen_device *pps_gen; - struct hrtimer timer; - void __iomem *base; - u32 prev_count; - spinlock_t lock; - struct device *dev; -}; +#include "pps_gen_tio.h" =20 static inline u32 pps_tio_read(u32 offset, struct pps_tio *tio) { diff --git a/drivers/pps/generators/pps_gen_tio.h b/drivers/pps/generators/= pps_gen_tio.h new file mode 100644 index 000000000000..78d4d7c25221 --- /dev/null +++ b/drivers/pps/generators/pps_gen_tio.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Intel PPS signal Generator Driver + * + * Copyright (C) 2025 Intel Corporation + */ + +#ifndef _PPS_GEN_TIO_H_ +#define _PPS_GEN_TIO_H_ + +#include +#include +#include +#include +#include + +#define TIOCTL 0x00 +#define TIOCOMPV 0x10 +#define TIOEC 0x30 + +/* Control Register */ +#define TIOCTL_EN BIT(0) +#define TIOCTL_DIR BIT(1) +#define TIOCTL_EP GENMASK(3, 2) +#define TIOCTL_EP_RISING_EDGE FIELD_PREP(TIOCTL_EP, 0) +#define TIOCTL_EP_FALLING_EDGE FIELD_PREP(TIOCTL_EP, 1) +#define TIOCTL_EP_TOGGLE_EDGE FIELD_PREP(TIOCTL_EP, 2) + +/* Safety time to set hrtimer early */ +#define SAFE_TIME_NS (10 * NSEC_PER_MSEC) + +#define MAGIC_CONST (NSEC_PER_SEC - SAFE_TIME_NS) +#define ART_HW_DELAY_CYCLES 2 + +struct pps_tio { + struct pps_gen_source_info gen_info; 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25 Feb 2025 22:16:00 -0800 From: Raag Jadav To: lee@kernel.org, giometti@enneenne.com, gregkh@linuxfoundation.org, andriy.shevchenko@linux.intel.com, raymond.tan@intel.com Cc: linux-kernel@vger.kernel.org, Raag Jadav Subject: [PATCH v1 2/4] pps: generators: tio: move to match_data() model Date: Wed, 26 Feb 2025 11:45:25 +0530 Message-Id: <20250226061527.3031250-3-raag.jadav@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250226061527.3031250-1-raag.jadav@intel.com> References: <20250226061527.3031250-1-raag.jadav@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use device_get_match_data() which allows configuring platform specific data like number of pins and MMIO registers for TIO. Signed-off-by: Raag Jadav Acked-by: Rodolfo Giometti Reviewed-by: Andy Shevchenko --- drivers/pps/generators/pps_gen_tio.c | 33 ++++++++++++++++++++-------- drivers/pps/generators/pps_gen_tio.h | 19 +++++++++++++--- 2 files changed, 40 insertions(+), 12 deletions(-) diff --git a/drivers/pps/generators/pps_gen_tio.c b/drivers/pps/generators/= pps_gen_tio.c index 7f2aab1219af..89b08301d21e 100644 --- a/drivers/pps/generators/pps_gen_tio.c +++ b/drivers/pps/generators/pps_gen_tio.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include =20 @@ -21,6 +22,14 @@ =20 #include "pps_gen_tio.h" =20 +static const struct pps_tio_data pmc_data =3D { + .regs =3D { + .ctl =3D TIOCTL_PMC, + .compv =3D TIOCOMPV_PMC, + .ec =3D TIOEC_PMC, + }, +}; + static inline u32 pps_tio_read(u32 offset, struct pps_tio *tio) { return readl(tio->base + offset); @@ -28,7 +37,7 @@ static inline u32 pps_tio_read(u32 offset, struct pps_tio= *tio) =20 static inline void pps_ctl_write(u32 value, struct pps_tio *tio) { - writel(value, tio->base + TIOCTL); + writel(value, tio->base + tio->regs.ctl); } =20 /* @@ -37,7 +46,7 @@ static inline void pps_ctl_write(u32 value, struct pps_ti= o *tio) */ static inline void pps_compv_write(u64 value, struct pps_tio *tio) { - hi_lo_writeq(value, tio->base + TIOCOMPV); + hi_lo_writeq(value, tio->base + tio->regs.compv); } =20 static inline ktime_t first_event(struct pps_tio *tio) @@ -49,7 +58,7 @@ static u32 pps_tio_disable(struct pps_tio *tio) { u32 ctrl; =20 - ctrl =3D pps_tio_read(TIOCTL, tio); + ctrl =3D pps_tio_read(tio->regs.ctl, tio); pps_compv_write(0, tio); =20 ctrl &=3D ~TIOCTL_EN; @@ -63,7 +72,7 @@ static void pps_tio_enable(struct pps_tio *tio) { u32 ctrl; =20 - ctrl =3D pps_tio_read(TIOCTL, tio); + ctrl =3D pps_tio_read(tio->regs.ctl, tio); ctrl |=3D TIOCTL_EN; pps_ctl_write(ctrl, tio); tio->pps_gen->enabled =3D true; @@ -112,7 +121,7 @@ static enum hrtimer_restart hrtimer_callback(struct hrt= imer *timer) * Check if any event is missed. * If an event is missed, TIO will be disabled. */ - event_count =3D pps_tio_read(TIOEC, tio); + event_count =3D pps_tio_read(tio->regs.ec, tio); if (tio->prev_count && tio->prev_count =3D=3D event_count) goto err; tio->prev_count =3D event_count; @@ -172,6 +181,7 @@ static int pps_tio_get_time(struct pps_gen_device *pps_= gen, static int pps_gen_tio_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; + const struct pps_tio_data *data; struct pps_tio *tio; =20 if (!(cpu_feature_enabled(X86_FEATURE_TSC_KNOWN_FREQ) && @@ -184,6 +194,11 @@ static int pps_gen_tio_probe(struct platform_device *p= dev) if (!tio) return -ENOMEM; =20 + data =3D device_get_match_data(dev); + if (!data) + return -ENODEV; + + tio->regs =3D data->regs; tio->gen_info.use_system_clock =3D true; tio->gen_info.enable =3D pps_tio_gen_enable; tio->gen_info.get_time =3D pps_tio_get_time; @@ -217,10 +232,10 @@ static void pps_gen_tio_remove(struct platform_device= *pdev) } =20 static const struct acpi_device_id intel_pmc_tio_acpi_match[] =3D { - { "INTC1021" }, - { "INTC1022" }, - { "INTC1023" }, - { "INTC1024" }, + { "INTC1021", (kernel_ulong_t)&pmc_data }, + { "INTC1022", (kernel_ulong_t)&pmc_data }, + { "INTC1023", (kernel_ulong_t)&pmc_data }, + { "INTC1024", (kernel_ulong_t)&pmc_data }, {} }; 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charset="utf-8" Add initial support for Intel Elkhart Lake PSE TIO controller. Signed-off-by: Raag Jadav Acked-by: Rodolfo Giometti Reviewed-by: Andy Shevchenko --- drivers/pps/generators/pps_gen_tio.c | 17 ++++++++++++++++- drivers/pps/generators/pps_gen_tio.h | 5 +++++ 2 files changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/pps/generators/pps_gen_tio.c b/drivers/pps/generators/= pps_gen_tio.c index 89b08301d21e..8339d8c8f8bb 100644 --- a/drivers/pps/generators/pps_gen_tio.c +++ b/drivers/pps/generators/pps_gen_tio.c @@ -22,6 +22,14 @@ =20 #include "pps_gen_tio.h" =20 +static const struct pps_tio_data ehl_pse_data =3D { + .regs =3D { + .ctl =3D TIOCTL_PSE, + .compv =3D TIOCOMPV_PSE, + .ec =3D TIOEC_PSE, + }, +}; + static const struct pps_tio_data pmc_data =3D { .regs =3D { .ctl =3D TIOCTL_PMC, @@ -240,9 +248,16 @@ static const struct acpi_device_id intel_pmc_tio_acpi_= match[] =3D { }; MODULE_DEVICE_TABLE(acpi, intel_pmc_tio_acpi_match); =20 +static const struct platform_device_id pps_gen_tio_ids[] =3D { + { "pps-gen-tio", (kernel_ulong_t)&ehl_pse_data }, + { } +}; +MODULE_DEVICE_TABLE(platform, pps_gen_tio_ids); + static struct platform_driver pps_gen_tio_driver =3D { .probe =3D pps_gen_tio_probe, .remove =3D pps_gen_tio_remove, + .id_table =3D pps_gen_tio_ids, .driver =3D { .name =3D "intel-pps-gen-tio", .acpi_match_table =3D intel_pmc_tio_acpi_match, @@ -255,5 +270,5 @@ MODULE_AUTHOR("Lakshmi Sowjanya D "); MODULE_AUTHOR("Pandith N "); MODULE_AUTHOR("Thejesh Reddy T R "); MODULE_AUTHOR("Subramanian Mohan "); -MODULE_DESCRIPTION("Intel PMC Time-Aware IO Generator Driver"); +MODULE_DESCRIPTION("Intel Time-Aware IO Generator Driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/pps/generators/pps_gen_tio.h b/drivers/pps/generators/= pps_gen_tio.h index e652f976e455..bbf5b994e7ff 100644 --- a/drivers/pps/generators/pps_gen_tio.h +++ b/drivers/pps/generators/pps_gen_tio.h @@ -14,6 +14,11 @@ #include #include =20 +/* EHL PSE Registers */ +#define TIOCTL_PSE 0x00 +#define TIOCOMPV_PSE 0x04 +#define TIOEC_PSE 0x24 + /* PMC Registers */ #define TIOCTL_PMC 0x00 #define TIOCOMPV_PMC 0x10 --=20 2.34.1 From nobody Sun Feb 8 21:16:52 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 44F04269806 for ; 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a="41636487" X-IronPort-AV: E=Sophos;i="6.13,316,1732608000"; d="scan'208";a="41636487" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Feb 2025 22:16:08 -0800 X-CSE-ConnectionGUID: O/swzXeCSAqZ5z6LVTOOQg== X-CSE-MsgGUID: qpvMoH1jSjuGSiF8Pp4DvA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,316,1732608000"; d="scan'208";a="147434834" Received: from jraag-z790m-itx-wifi.iind.intel.com ([10.190.239.23]) by orviesa002.jf.intel.com with ESMTP; 25 Feb 2025 22:16:05 -0800 From: Raag Jadav To: lee@kernel.org, giometti@enneenne.com, gregkh@linuxfoundation.org, andriy.shevchenko@linux.intel.com, raymond.tan@intel.com Cc: linux-kernel@vger.kernel.org, Raag Jadav Subject: [PATCH v1 4/4] mfd: intel-ehl: Introduce Intel Elkhart Lake PSE GPIO and TIO Date: Wed, 26 Feb 2025 11:45:27 +0530 Message-Id: <20250226061527.3031250-5-raag.jadav@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250226061527.3031250-1-raag.jadav@intel.com> References: <20250226061527.3031250-1-raag.jadav@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Intel Elkhart Lake Programmable Service Engine (PSE) includes two PCI devices that expose two different capabilities of GPIO and Timed I/O as a single PCI function through shared MMIO. Signed-off-by: Raag Jadav Reviewed-by: Andy Shevchenko --- MAINTAINERS | 5 ++ drivers/mfd/Kconfig | 9 ++++ drivers/mfd/Makefile | 1 + drivers/mfd/intel-ehl-gpio.c | 95 ++++++++++++++++++++++++++++++++++++ 4 files changed, 110 insertions(+) create mode 100644 drivers/mfd/intel-ehl-gpio.c diff --git a/MAINTAINERS b/MAINTAINERS index d4280facbe51..7e50a6892878 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11643,6 +11643,11 @@ F: drivers/gpio/gpio-sodaville.c F: drivers/gpio/gpio-tangier.c F: drivers/gpio/gpio-tangier.h =20 +INTEL GPIO MFD DRIVER +M: Raag Jadav +S: Supported +F: drivers/mfd/intel-ehl-gpio.c + INTEL GVT-g DRIVERS (Intel GPU Virtualization) M: Zhenyu Wang M: Zhi Wang diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 6b0682af6e32..8ba3db736a8f 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -609,6 +609,15 @@ config MFD_INTEL_QUARK_I2C_GPIO their respective IO driver. The GPIO exports a total amount of 8 interrupt-capable GPIOs. =20 +config MFD_INTEL_EHL_PSE_GPIO + tristate "Intel Elkhart Lake PSE GPIO MFD" + depends on PCI && (X86 || COMPILE_TEST) + select MFD_CORE + help + This MFD provides support for GPIO and TIO that exist on Intel + Elkhart Lake PSE as a single PCI device. It splits the two I/O + devices to their respective I/O drivers. + config LPC_ICH tristate "Intel ICH LPC" depends on PCI diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index 9220eaf7cf12..bf7245fb6824 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -197,6 +197,7 @@ obj-$(CONFIG_PMIC_ADP5520) +=3D adp5520.o obj-$(CONFIG_MFD_ADP5585) +=3D adp5585.o obj-$(CONFIG_MFD_KEMPLD) +=3D kempld-core.o obj-$(CONFIG_MFD_INTEL_QUARK_I2C_GPIO) +=3D intel_quark_i2c_gpio.o +obj-$(CONFIG_MFD_INTEL_EHL_PSE_GPIO) +=3D intel-ehl-gpio.o obj-$(CONFIG_LPC_SCH) +=3D lpc_sch.o obj-$(CONFIG_LPC_ICH) +=3D lpc_ich.o obj-$(CONFIG_MFD_RDC321X) +=3D rdc321x-southbridge.o diff --git a/drivers/mfd/intel-ehl-gpio.c b/drivers/mfd/intel-ehl-gpio.c new file mode 100644 index 000000000000..039c74c64848 --- /dev/null +++ b/drivers/mfd/intel-ehl-gpio.c @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Intel Multi-Functional driver for Elkhart Lake - Programmable + * Service Engine (PSE) GPIO & TIO + * + * Copyright (c) 2025 Intel Corporation + * + * Intel Elkhart Lake PSE includes two PCI devices that expose two + * different capabilities of GPIO and Timed I/O as a single PCI + * function through shared MMIO. + */ + +#include +#include +#include +#include +#include +#include +#include + +#define PSE_GPIO_OFFSET 0x0000 +#define PSE_GPIO_SIZE 0x0134 + +#define PSE_TIO_OFFSET 0x1000 +#define PSE_TIO_SIZE 0x06B0 + +static struct resource ehl_pse_gpio_resources[] =3D { + DEFINE_RES_MEM(PSE_GPIO_OFFSET, PSE_GPIO_SIZE), + DEFINE_RES_IRQ(0), +}; + +static struct resource ehl_pse_tio_resources[] =3D { + DEFINE_RES_MEM(PSE_TIO_OFFSET, PSE_TIO_SIZE), + DEFINE_RES_IRQ(1), +}; + +static struct mfd_cell ehl_pse_gpio_devs[] =3D { + { + .name =3D "gpio-elkhartlake", + .num_resources =3D ARRAY_SIZE(ehl_pse_gpio_resources), + .resources =3D ehl_pse_gpio_resources, + .ignore_resource_conflicts =3D true, + }, + { + .name =3D "pps-gen-tio", + .num_resources =3D ARRAY_SIZE(ehl_pse_tio_resources), + .resources =3D ehl_pse_tio_resources, + .ignore_resource_conflicts =3D true, + }, +}; + +static int ehl_pse_gpio_probe(struct pci_dev *pci, const struct pci_device= _id *id) +{ + int ret; + + ret =3D pcim_enable_device(pci); + if (ret) + return ret; + + pci_set_master(pci); + + ret =3D pci_alloc_irq_vectors(pci, 2, 2, PCI_IRQ_ALL_TYPES); + if (ret < 0) + return ret; + + return mfd_add_devices(&pci->dev, PLATFORM_DEVID_AUTO, ehl_pse_gpio_devs, + ARRAY_SIZE(ehl_pse_gpio_devs), &pci->resource[0], + pci_irq_vector(pci, 0), NULL); +} + +static void ehl_pse_gpio_remove(struct pci_dev *pdev) +{ + mfd_remove_devices(&pdev->dev); + pci_free_irq_vectors(pdev); +} + +static const struct pci_device_id ehl_pse_gpio_ids[] =3D { + { PCI_VDEVICE(INTEL, 0x4b88) }, + { PCI_VDEVICE(INTEL, 0x4b89) }, + {} +}; +MODULE_DEVICE_TABLE(pci, ehl_pse_gpio_ids); + +static struct pci_driver ehl_pse_gpio_driver =3D { + .probe =3D ehl_pse_gpio_probe, + .remove =3D ehl_pse_gpio_remove, + .id_table =3D ehl_pse_gpio_ids, + .name =3D "ehl_pse_gpio", +}; +module_pci_driver(ehl_pse_gpio_driver); + +MODULE_AUTHOR("Raymond Tan "); +MODULE_AUTHOR("Raag Jadav "); +MODULE_DESCRIPTION("Intel MFD for Elkhart Lake PSE GPIO & TIO"); +MODULE_LICENSE("GPL"); --=20 2.34.1