From nobody Fri Dec 19 04:04:59 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DC5CE26BDA3; Wed, 26 Feb 2025 04:15:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740543304; cv=none; b=V31kCYpD03CvpDt4z/0sqZ9jlXTCf1J4PqbD4g9tGFO5M92h/Rl93E1Lg6LCG+PBJiCX1cF0A7UIpiO+KRf6GesVglvgO1kbPTkb1jEM7JemNYI7enJMPkkVQVJx3C4j80+0PW3d2ZsePBNSc2I0bvRPaEALzwaQVX5uLsL+tZY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740543304; c=relaxed/simple; bh=8ZzmsjtWLz2Ib3s6u/sHI6jUHeEUNHtK30Gt9wBNlPo=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=WMMfvu68SnaoHZkJnzaN+CZ22RDhQ2Ga4Wuf2OzRFSLNunOR+4QfK6lr9U7pdgpfJfftLr9bllP3BQ+fzCBZ3iqIESXqnAgSTVk7vXtA9WTtl4vahsplitwL701Wlai3AIiFifk+W2V8RzgCciv9u9SfGeuRqfM3/8J7070soM8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=GfaiHWDt; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="GfaiHWDt" Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 51PMcft1000780; Wed, 26 Feb 2025 04:14:50 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= L4yuKIyeTLs4ef1WFib+KL4Rb5A7xpdSToFgPoRRraI=; b=GfaiHWDtfIAWZkhO FmdlXgx+C9I4OG7yuXZoCpAPRNUgfwaLpyhP+Azohv/Ng8d/sVVsaGKKQtHs7XB/ b2R56DnWDklNI7RXoWe15uTjgPbo119dJAVWQOuR3nCSklKYGKYgWDhhGa//77fn j4JfKab5ZKzkmY2QQ9qk8W/B9b4SzMYkcsLMpen4jN/yvn0bc89EwTEsBeshI6wQ w2F9mmW9beQSpgGL+TK8gck+Rd6y2rRMbqdLWiKyjRriei0/zJXbrKOYdaDR65d0 k7zZ6JMa6D5iD0CbTOtreIH/e9e5fj0At4dYqelHR6OpPlZC3e/XtcajV0wjqdQ2 XApMBw== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 451pu98nfm-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 26 Feb 2025 04:14:49 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 51Q4EnBk007221 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 26 Feb 2025 04:14:49 GMT Received: from jiegan-gv.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 25 Feb 2025 20:14:43 -0800 From: Jie Gan To: Suzuki K Poulose , Mike Leach , James Clark , "Alexander Shishkin" , Maxime Coquelin , Alexandre Torgue , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio CC: Tingwei Zhang , Jinlong Mao , , , , , , Subject: [PATCH v14 08/10] dt-bindings: arm: Add Coresight TMC Control Unit hardware Date: Wed, 26 Feb 2025 12:13:40 +0800 Message-ID: <20250226041342.53933-9-quic_jiegan@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250226041342.53933-1-quic_jiegan@quicinc.com> References: <20250226041342.53933-1-quic_jiegan@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 9zIr254IIulvzPX3ruTpnwHYvT5aBdfY X-Proofpoint-ORIG-GUID: 9zIr254IIulvzPX3ruTpnwHYvT5aBdfY X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-25_08,2025-02-25_03,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 phishscore=0 adultscore=2 spamscore=0 impostorscore=0 lowpriorityscore=0 bulkscore=0 mlxlogscore=999 malwarescore=0 suspectscore=0 clxscore=1015 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2502100000 definitions=main-2502260030 Content-Type: text/plain; charset="utf-8" Add binding file to specify how to define a Coresight TMC Control Unit devi= ce in device tree. It is responsible for controlling the data filter function based on the sou= rce device's Trace ID for TMC ETR device. The trace data with that Trace id can= get into ETR's buffer while other trace data gets ignored. Reviewed-by: Rob Herring (Arm) Signed-off-by: Jie Gan --- .../bindings/arm/qcom,coresight-ctcu.yaml | 84 +++++++++++++++++++ 1 file changed, 84 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/qcom,coresight-ct= cu.yaml diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml= b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml new file mode 100644 index 000000000000..843b52eaf872 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/qcom,coresight-ctcu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: CoreSight TMC Control Unit + +maintainers: + - Yuanfang Zhang + - Mao Jinlong + - Jie Gan + +description: | + The Trace Memory Controller(TMC) is used for Embedded Trace Buffer(ETB), + Embedded Trace FIFO(ETF) and Embedded Trace Router(ETR) configurations. + The configuration mode (ETB, ETF, ETR) is discovered at boot time when + the device is probed. + + The Coresight TMC Control unit controls various Coresight behaviors. + It works as a helper device when connected to TMC ETR device. + It is responsible for controlling the data filter function based on + the source device's Trace ID for TMC ETR device. The trace data with + that Trace id can get into ETR's buffer while other trace data gets + ignored. + +properties: + compatible: + enum: + - qcom,sa8775p-ctcu + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: apb + + in-ports: + $ref: /schemas/graph.yaml#/properties/ports + + patternProperties: + '^port(@[0-1])?$': + description: Input connections from CoreSight Trace bus + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + - reg + - in-ports + +additionalProperties: false + +examples: + - | + ctcu@1001000 { + compatible =3D "qcom,sa8775p-ctcu"; + reg =3D <0x1001000 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb"; + + in-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + ctcu_in_port0: endpoint { + remote-endpoint =3D <&etr0_out_port>; + }; + }; + + port@1 { + reg =3D <1>; + ctcu_in_port1: endpoint { + remote-endpoint =3D <&etr1_out_port>; + }; + }; + }; + }; --=20 2.34.1