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charset="utf-8" Use devm_clk_bulk_get_all() to simple clock handle codes. No function changes. Signed-off-by: Richard Zhu --- drivers/pci/controller/dwc/pci-imx6.c | 76 ++++++--------------------- 1 file changed, 15 insertions(+), 61 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller= /dwc/pci-imx6.c index 90ace941090f..35bfd46225c9 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -109,7 +109,6 @@ enum imx_pcie_variants { =20 #define imx_check_flag(pci, val) (pci->drvdata->flags & val) =20 -#define IMX_PCIE_MAX_CLKS 6 #define IMX_PCIE_MAX_INSTANCES 2 =20 struct imx_pcie; @@ -120,9 +119,6 @@ struct imx_pcie_drvdata { u32 flags; int dbi_length; const char *gpr; - const char * const *clk_names; - const u32 clks_cnt; - const u32 clks_optional_cnt; const u32 ltssm_off; const u32 ltssm_mask; const u32 mode_off[IMX_PCIE_MAX_INSTANCES]; @@ -137,7 +133,8 @@ struct imx_pcie_drvdata { struct imx_pcie { struct dw_pcie *pci; struct gpio_desc *reset_gpiod; - struct clk_bulk_data clks[IMX_PCIE_MAX_CLKS]; + struct clk_bulk_data *clks; + int num_clks; struct regmap *iomuxc_gpr; u16 msi_ctrl; u32 controller_id; @@ -470,13 +467,14 @@ static int imx_setup_phy_mpll(struct imx_pcie *imx_pc= ie) int mult, div; u16 val; int i; + struct clk_bulk_data *clks =3D imx_pcie->clks; =20 if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_IMX_PHY)) return 0; =20 - for (i =3D 0; i < imx_pcie->drvdata->clks_cnt; i++) - if (strncmp(imx_pcie->clks[i].id, "pcie_phy", 8) =3D=3D 0) - phy_rate =3D clk_get_rate(imx_pcie->clks[i].clk); + for (i =3D 0; i < imx_pcie->num_clks; i++) + if (strncmp(clks[i].id, "pcie_phy", 8) =3D=3D 0) + phy_rate =3D clk_get_rate(clks[i].clk); =20 switch (phy_rate) { case 125000000: @@ -668,7 +666,7 @@ static int imx_pcie_clk_enable(struct imx_pcie *imx_pci= e) struct device *dev =3D pci->dev; int ret; =20 - ret =3D clk_bulk_prepare_enable(imx_pcie->drvdata->clks_cnt, imx_pcie->cl= ks); + ret =3D clk_bulk_prepare_enable(imx_pcie->num_clks, imx_pcie->clks); if (ret) return ret; =20 @@ -685,7 +683,7 @@ static int imx_pcie_clk_enable(struct imx_pcie *imx_pci= e) return 0; =20 err_ref_clk: - clk_bulk_disable_unprepare(imx_pcie->drvdata->clks_cnt, imx_pcie->clks); + clk_bulk_disable_unprepare(imx_pcie->num_clks, imx_pcie->clks); =20 return ret; } @@ -694,7 +692,7 @@ static void imx_pcie_clk_disable(struct imx_pcie *imx_p= cie) { if (imx_pcie->drvdata->enable_ref_clk) imx_pcie->drvdata->enable_ref_clk(imx_pcie, false); - clk_bulk_disable_unprepare(imx_pcie->drvdata->clks_cnt, imx_pcie->clks); + clk_bulk_disable_unprepare(imx_pcie->num_clks, imx_pcie->clks); } =20 static int imx6sx_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert) @@ -1476,7 +1474,7 @@ static int imx_pcie_probe(struct platform_device *pde= v) struct device_node *np; struct resource *dbi_base; struct device_node *node =3D dev->of_node; - int i, ret, req_cnt; + int ret; u16 val; =20 imx_pcie =3D devm_kzalloc(dev, sizeof(*imx_pcie), GFP_KERNEL); @@ -1526,20 +1524,12 @@ static int imx_pcie_probe(struct platform_device *p= dev) "unable to get reset gpio\n"); gpiod_set_consumer_name(imx_pcie->reset_gpiod, "PCIe reset"); =20 - if (imx_pcie->drvdata->clks_cnt >=3D IMX_PCIE_MAX_CLKS) - return dev_err_probe(dev, -ENOMEM, "clks_cnt is too big\n"); - - for (i =3D 0; i < imx_pcie->drvdata->clks_cnt; i++) - imx_pcie->clks[i].id =3D imx_pcie->drvdata->clk_names[i]; - /* Fetch clocks */ - req_cnt =3D imx_pcie->drvdata->clks_cnt - imx_pcie->drvdata->clks_optiona= l_cnt; - ret =3D devm_clk_bulk_get(dev, req_cnt, imx_pcie->clks); - if (ret) - return ret; - imx_pcie->clks[req_cnt].clk =3D devm_clk_get_optional(dev, "ref"); - if (IS_ERR(imx_pcie->clks[req_cnt].clk)) - return PTR_ERR(imx_pcie->clks[req_cnt].clk); + imx_pcie->num_clks =3D devm_clk_bulk_get_all(dev, &imx_pcie->clks); + if (imx_pcie->num_clks < 0) { + dev_err(dev, "failed to get clocks\n"); + return imx_pcie->num_clks; + } =20 if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_PHYDRV)) { imx_pcie->phy =3D devm_phy_get(dev, "pcie-phy"); @@ -1675,13 +1665,6 @@ static void imx_pcie_shutdown(struct platform_device= *pdev) imx_pcie_assert_core_reset(imx_pcie); } =20 -static const char * const imx6q_clks[] =3D {"pcie_bus", "pcie", "pcie_phy"= }; -static const char * const imx8mm_clks[] =3D {"pcie_bus", "pcie", "pcie_aux= "}; -static const char * const imx8mq_clks[] =3D {"pcie_bus", "pcie", "pcie_phy= ", "pcie_aux"}; -static const char * const imx6sx_clks[] =3D {"pcie_bus", "pcie", "pcie_phy= ", "pcie_inbound_axi"}; -static const char * const imx8q_clks[] =3D {"mstr", "slv", "dbi"}; -static const char * const imx95_clks[] =3D {"pcie_bus", "pcie", "pcie_phy"= , "pcie_aux", "ref"}; - static const struct imx_pcie_drvdata drvdata[] =3D { [IMX6Q] =3D { .variant =3D IMX6Q, @@ -1691,8 +1674,6 @@ static const struct imx_pcie_drvdata drvdata[] =3D { IMX_PCIE_FLAG_SUPPORTS_SUSPEND, .dbi_length =3D 0x200, .gpr =3D "fsl,imx6q-iomuxc-gpr", - .clk_names =3D imx6q_clks, - .clks_cnt =3D ARRAY_SIZE(imx6q_clks), .ltssm_off =3D IOMUXC_GPR12, .ltssm_mask =3D IMX6Q_GPR12_PCIE_CTL_2, .mode_off[0] =3D IOMUXC_GPR12, @@ -1707,8 +1688,6 @@ static const struct imx_pcie_drvdata drvdata[] =3D { IMX_PCIE_FLAG_IMX_SPEED_CHANGE | IMX_PCIE_FLAG_SUPPORTS_SUSPEND, .gpr =3D "fsl,imx6q-iomuxc-gpr", - .clk_names =3D imx6sx_clks, - .clks_cnt =3D ARRAY_SIZE(imx6sx_clks), .ltssm_off =3D IOMUXC_GPR12, .ltssm_mask =3D IMX6Q_GPR12_PCIE_CTL_2, .mode_off[0] =3D IOMUXC_GPR12, @@ -1725,8 +1704,6 @@ static const struct imx_pcie_drvdata drvdata[] =3D { IMX_PCIE_FLAG_SUPPORTS_SUSPEND, .dbi_length =3D 0x200, .gpr =3D "fsl,imx6q-iomuxc-gpr", - .clk_names =3D imx6q_clks, - .clks_cnt =3D ARRAY_SIZE(imx6q_clks), .ltssm_off =3D IOMUXC_GPR12, .ltssm_mask =3D IMX6Q_GPR12_PCIE_CTL_2, .mode_off[0] =3D IOMUXC_GPR12, @@ -1742,8 +1719,6 @@ static const struct imx_pcie_drvdata drvdata[] =3D { IMX_PCIE_FLAG_HAS_APP_RESET | IMX_PCIE_FLAG_HAS_PHY_RESET, .gpr =3D "fsl,imx7d-iomuxc-gpr", - .clk_names =3D imx6q_clks, - .clks_cnt =3D ARRAY_SIZE(imx6q_clks), .mode_off[0] =3D IOMUXC_GPR12, .mode_mask[0] =3D IMX6Q_GPR12_DEVICE_TYPE, .enable_ref_clk =3D imx7d_pcie_enable_ref_clk, @@ -1755,8 +1730,6 @@ static const struct imx_pcie_drvdata drvdata[] =3D { IMX_PCIE_FLAG_HAS_PHY_RESET | IMX_PCIE_FLAG_SUPPORTS_SUSPEND, .gpr =3D "fsl,imx8mq-iomuxc-gpr", - .clk_names =3D imx8mq_clks, - .clks_cnt =3D ARRAY_SIZE(imx8mq_clks), .mode_off[0] =3D IOMUXC_GPR12, .mode_mask[0] =3D IMX6Q_GPR12_DEVICE_TYPE, .mode_off[1] =3D IOMUXC_GPR12, @@ -1770,8 +1743,6 @@ static const struct imx_pcie_drvdata drvdata[] =3D { IMX_PCIE_FLAG_HAS_PHYDRV | IMX_PCIE_FLAG_HAS_APP_RESET, .gpr =3D "fsl,imx8mm-iomuxc-gpr", - .clk_names =3D imx8mm_clks, - .clks_cnt =3D ARRAY_SIZE(imx8mm_clks), .mode_off[0] =3D IOMUXC_GPR12, .mode_mask[0] =3D IMX6Q_GPR12_DEVICE_TYPE, .enable_ref_clk =3D imx8mm_pcie_enable_ref_clk, @@ -1782,8 +1753,6 @@ static const struct imx_pcie_drvdata drvdata[] =3D { IMX_PCIE_FLAG_HAS_PHYDRV | IMX_PCIE_FLAG_HAS_APP_RESET, .gpr =3D "fsl,imx8mp-iomuxc-gpr", - .clk_names =3D imx8mm_clks, - .clks_cnt =3D ARRAY_SIZE(imx8mm_clks), .mode_off[0] =3D IOMUXC_GPR12, .mode_mask[0] =3D IMX6Q_GPR12_DEVICE_TYPE, .enable_ref_clk =3D imx8mm_pcie_enable_ref_clk, @@ -1793,17 +1762,12 @@ static const struct imx_pcie_drvdata drvdata[] =3D { .flags =3D IMX_PCIE_FLAG_HAS_PHYDRV | IMX_PCIE_FLAG_CPU_ADDR_FIXUP | IMX_PCIE_FLAG_SUPPORTS_SUSPEND, - .clk_names =3D imx8q_clks, - .clks_cnt =3D ARRAY_SIZE(imx8q_clks), }, [IMX95] =3D { .variant =3D IMX95, .flags =3D IMX_PCIE_FLAG_HAS_SERDES | IMX_PCIE_FLAG_HAS_LUT | IMX_PCIE_FLAG_SUPPORTS_SUSPEND, - .clk_names =3D imx95_clks, - .clks_cnt =3D ARRAY_SIZE(imx95_clks), - .clks_optional_cnt =3D 1, .ltssm_off =3D IMX95_PE0_GEN_CTRL_3, .ltssm_mask =3D IMX95_PCIE_LTSSM_EN, .mode_off[0] =3D IMX95_PE0_GEN_CTRL_1, @@ -1816,8 +1780,6 @@ static const struct imx_pcie_drvdata drvdata[] =3D { IMX_PCIE_FLAG_HAS_PHY_RESET, .mode =3D DW_PCIE_EP_TYPE, .gpr =3D "fsl,imx8mq-iomuxc-gpr", - .clk_names =3D imx8mq_clks, - .clks_cnt =3D ARRAY_SIZE(imx8mq_clks), .mode_off[0] =3D IOMUXC_GPR12, .mode_mask[0] =3D IMX6Q_GPR12_DEVICE_TYPE, .mode_off[1] =3D IOMUXC_GPR12, @@ -1832,8 +1794,6 @@ static const struct imx_pcie_drvdata drvdata[] =3D { IMX_PCIE_FLAG_HAS_PHYDRV, .mode =3D DW_PCIE_EP_TYPE, .gpr =3D "fsl,imx8mm-iomuxc-gpr", - .clk_names =3D imx8mm_clks, - .clks_cnt =3D ARRAY_SIZE(imx8mm_clks), .mode_off[0] =3D IOMUXC_GPR12, .mode_mask[0] =3D IMX6Q_GPR12_DEVICE_TYPE, .epc_features =3D &imx8m_pcie_epc_features, @@ -1845,8 +1805,6 @@ static const struct imx_pcie_drvdata drvdata[] =3D { IMX_PCIE_FLAG_HAS_PHYDRV, .mode =3D DW_PCIE_EP_TYPE, .gpr =3D "fsl,imx8mp-iomuxc-gpr", - .clk_names =3D imx8mm_clks, - .clks_cnt =3D ARRAY_SIZE(imx8mm_clks), .mode_off[0] =3D IOMUXC_GPR12, .mode_mask[0] =3D IMX6Q_GPR12_DEVICE_TYPE, .epc_features =3D &imx8m_pcie_epc_features, @@ -1857,15 +1815,11 @@ static const struct imx_pcie_drvdata drvdata[] =3D { .flags =3D IMX_PCIE_FLAG_HAS_PHYDRV, .mode =3D DW_PCIE_EP_TYPE, .epc_features =3D &imx8q_pcie_epc_features, - .clk_names =3D imx8q_clks, - .clks_cnt =3D ARRAY_SIZE(imx8q_clks), }, [IMX95_EP] =3D { .variant =3D IMX95_EP, .flags =3D IMX_PCIE_FLAG_HAS_SERDES | IMX_PCIE_FLAG_SUPPORT_64BIT, - .clk_names =3D imx8mq_clks, - .clks_cnt =3D ARRAY_SIZE(imx8mq_clks), .ltssm_off =3D IMX95_PE0_GEN_CTRL_3, .ltssm_mask =3D IMX95_PCIE_LTSSM_EN, .mode_off[0] =3D IMX95_PE0_GEN_CTRL_1, --=20 2.37.1