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Wed, 26 Feb 2025 12:25:11 -0800 (PST) From: Atish Patra Date: Wed, 26 Feb 2025 12:25:03 -0800 Subject: [PATCH 1/4] RISC-V: KVM: Disable the kernel perf counter during configure Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250226-kvm_pmu_improve-v1-1-74c058c2bf6d@rivosinc.com> References: <20250226-kvm_pmu_improve-v1-0-74c058c2bf6d@rivosinc.com> In-Reply-To: <20250226-kvm_pmu_improve-v1-0-74c058c2bf6d@rivosinc.com> To: Anup Patel , Atish Patra , Paul Walmsley , Palmer Dabbelt , Andrew Jones , Paolo Bonzini , Shuah Khan Cc: kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, Atish Patra X-Mailer: b4 0.15-dev-13183 The perf event should be marked disabled during the creation as it is not ready to be scheduled until there is SBI PMU start call or config matching is called with auto start. Otherwise, event add/start gets called during perf_event_create_kernel_counter function. It will be enabled and scheduled to run via perf_event_enable during either the above mentioned scenario. Fixes: 0cb74b65d2e5 ("RISC-V: KVM: Implement perf support without sampling") Signed-off-by: Atish Patra Reviewed-by: Andrew Jones --- arch/riscv/kvm/vcpu_pmu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/kvm/vcpu_pmu.c b/arch/riscv/kvm/vcpu_pmu.c index 2707a51b082c..78ac3216a54d 100644 --- a/arch/riscv/kvm/vcpu_pmu.c +++ b/arch/riscv/kvm/vcpu_pmu.c @@ -666,6 +666,7 @@ int kvm_riscv_vcpu_pmu_ctr_cfg_match(struct kvm_vcpu *v= cpu, unsigned long ctr_ba .type =3D etype, .size =3D sizeof(struct perf_event_attr), .pinned =3D true, + .disabled =3D true, /* * It should never reach here if the platform doesn't support the sscofp= mf * extension as mode filtering won't work without it. --=20 2.43.0 From nobody Mon Feb 9 11:44:16 2026 Received: from mail-pl1-f180.google.com (mail-pl1-f180.google.com [209.85.214.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2FC972745E for ; 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Wed, 26 Feb 2025 12:25:12 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7347a7f7de2sm4100963b3a.106.2025.02.26.12.25.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Feb 2025 12:25:12 -0800 (PST) From: Atish Patra Date: Wed, 26 Feb 2025 12:25:04 -0800 Subject: [PATCH 2/4] KVM: riscv: selftests: Do not start the counter in the overflow handler Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250226-kvm_pmu_improve-v1-2-74c058c2bf6d@rivosinc.com> References: <20250226-kvm_pmu_improve-v1-0-74c058c2bf6d@rivosinc.com> In-Reply-To: <20250226-kvm_pmu_improve-v1-0-74c058c2bf6d@rivosinc.com> To: Anup Patel , Atish Patra , Paul Walmsley , Palmer Dabbelt , Andrew Jones , Paolo Bonzini , Shuah Khan Cc: kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, Atish Patra X-Mailer: b4 0.15-dev-13183 There is no need to start the counter in the overflow handler as we intend to trigger precise number of LCOFI interrupts through these tests. The overflow irq handler has already stopped the counter. As a result, the stop call from the test function may return already supported error which is fine as well. Signed-off-by: Atish Patra Reviewed-by: Andrew Jones --- tools/testing/selftests/kvm/riscv/sbi_pmu_test.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c b/tools/testi= ng/selftests/kvm/riscv/sbi_pmu_test.c index f45c0ecc902d..284bc80193bd 100644 --- a/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c +++ b/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c @@ -118,8 +118,8 @@ static void stop_counter(unsigned long counter, unsigne= d long stop_flags) =20 ret =3D sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_STOP, counter, 1, stop= _flags, 0, 0, 0); - __GUEST_ASSERT(ret.error =3D=3D 0, "Unable to stop counter %ld error %ld\= n", - counter, ret.error); + __GUEST_ASSERT(ret.error =3D=3D 0 || ret.error =3D=3D SBI_ERR_ALREADY_STO= PPED, + "Unable to stop counter %ld error %ld\n", counter, ret.error); } =20 static void guest_illegal_exception_handler(struct ex_regs *regs) @@ -137,7 +137,6 @@ static void guest_irq_handler(struct ex_regs *regs) unsigned int irq_num =3D regs->cause & ~CAUSE_IRQ_FLAG; struct riscv_pmu_snapshot_data *snapshot_data =3D snapshot_gva; unsigned long overflown_mask; - unsigned long counter_val =3D 0; =20 /* Validate that we are in the correct irq handler */ GUEST_ASSERT_EQ(irq_num, IRQ_PMU_OVF); @@ -151,10 +150,6 @@ static void guest_irq_handler(struct ex_regs *regs) GUEST_ASSERT(overflown_mask & 0x01); =20 WRITE_ONCE(vcpu_shared_irq_count, vcpu_shared_irq_count+1); - - counter_val =3D READ_ONCE(snapshot_data->ctr_values[0]); - /* Now start the counter to mimick the real driver behavior */ - start_counter(counter_in_use, SBI_PMU_START_FLAG_SET_INIT_VALUE, counter_= val); } =20 static unsigned long get_counter_index(unsigned long cbase, unsigned long = cmask, --=20 2.43.0 From nobody Mon Feb 9 11:44:16 2026 Received: from mail-pl1-f179.google.com (mail-pl1-f179.google.com [209.85.214.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 49021257AFC for ; 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Wed, 26 Feb 2025 12:25:13 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7347a7f7de2sm4100963b3a.106.2025.02.26.12.25.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Feb 2025 12:25:13 -0800 (PST) From: Atish Patra Date: Wed, 26 Feb 2025 12:25:05 -0800 Subject: [PATCH 3/4] KVM: riscv: selftests: Change command line option Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250226-kvm_pmu_improve-v1-3-74c058c2bf6d@rivosinc.com> References: <20250226-kvm_pmu_improve-v1-0-74c058c2bf6d@rivosinc.com> In-Reply-To: <20250226-kvm_pmu_improve-v1-0-74c058c2bf6d@rivosinc.com> To: Anup Patel , Atish Patra , Paul Walmsley , Palmer Dabbelt , Andrew Jones , Paolo Bonzini , Shuah Khan Cc: kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, Atish Patra X-Mailer: b4 0.15-dev-13183 The PMU test commandline option takes an argument to disable a certain test. The initial assumption behind this was a common use case is just to run all the test most of the time. However, running a single test seems more useful instead. Especially, the overflow test has been helpful to validate PMU virtualizaiton interrupt changes. Switching the command line option to run a single test instead of disabling a single test also allows to provide additional test specific arguments to the test. The default without any options remains unchanged which continues to run all the tests. Signed-off-by: Atish Patra Reviewed-by: Andrew Jones --- tools/testing/selftests/kvm/riscv/sbi_pmu_test.c | 40 +++++++++++++++-----= ---- 1 file changed, 26 insertions(+), 14 deletions(-) diff --git a/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c b/tools/testi= ng/selftests/kvm/riscv/sbi_pmu_test.c index 284bc80193bd..533b76d0de82 100644 --- a/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c +++ b/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c @@ -39,7 +39,11 @@ static bool illegal_handler_invoked; #define SBI_PMU_TEST_SNAPSHOT BIT(2) #define SBI_PMU_TEST_OVERFLOW BIT(3) =20 -static int disabled_tests; +struct test_args { + int disabled_tests; +}; + +static struct test_args targs; =20 unsigned long pmu_csr_read_num(int csr_num) { @@ -604,7 +608,11 @@ static void test_vm_events_overflow(void *guest_code) vcpu_init_vector_tables(vcpu); /* Initialize guest timer frequency. */ timer_freq =3D vcpu_get_reg(vcpu, RISCV_TIMER_REG(frequency)); + + /* Export the shared variables to the guest */ sync_global_to_guest(vm, timer_freq); + sync_global_to_guest(vm, vcpu_shared_irq_count); + sync_global_to_guest(vm, targs); =20 run_vcpu(vcpu); =20 @@ -613,28 +621,30 @@ static void test_vm_events_overflow(void *guest_code) =20 static void test_print_help(char *name) { - pr_info("Usage: %s [-h] [-d ]\n", name); - pr_info("\t-d: Test to disable. Available tests are 'basic', 'events', 's= napshot', 'overflow'\n"); + pr_info("Usage: %s [-h] [-t ]\n", name); + pr_info("\t-t: Test to run (default all). Available tests are 'basic', 'e= vents', 'snapshot', 'overflow'\n"); pr_info("\t-h: print this help screen\n"); } =20 static bool parse_args(int argc, char *argv[]) { int opt; - - while ((opt =3D getopt(argc, argv, "hd:")) !=3D -1) { + int temp_disabled_tests =3D SBI_PMU_TEST_BASIC | SBI_PMU_TEST_EVENTS | SB= I_PMU_TEST_SNAPSHOT | + SBI_PMU_TEST_OVERFLOW; + while ((opt =3D getopt(argc, argv, "h:t:n:")) !=3D -1) { switch (opt) { - case 'd': + case 't': if (!strncmp("basic", optarg, 5)) - disabled_tests |=3D SBI_PMU_TEST_BASIC; + temp_disabled_tests &=3D ~SBI_PMU_TEST_BASIC; else if (!strncmp("events", optarg, 6)) - disabled_tests |=3D SBI_PMU_TEST_EVENTS; + temp_disabled_tests &=3D ~SBI_PMU_TEST_EVENTS; else if (!strncmp("snapshot", optarg, 8)) - disabled_tests |=3D SBI_PMU_TEST_SNAPSHOT; + temp_disabled_tests &=3D ~SBI_PMU_TEST_SNAPSHOT; else if (!strncmp("overflow", optarg, 8)) - disabled_tests |=3D SBI_PMU_TEST_OVERFLOW; + temp_disabled_tests &=3D ~SBI_PMU_TEST_OVERFLOW; else goto done; + targs.disabled_tests =3D temp_disabled_tests; break; case 'h': default: @@ -650,25 +660,27 @@ static bool parse_args(int argc, char *argv[]) =20 int main(int argc, char *argv[]) { + targs.disabled_tests =3D 0; + if (!parse_args(argc, argv)) exit(KSFT_SKIP); =20 - if (!(disabled_tests & SBI_PMU_TEST_BASIC)) { + if (!(targs.disabled_tests & SBI_PMU_TEST_BASIC)) { test_vm_basic_test(test_pmu_basic_sanity); pr_info("SBI PMU basic test : PASS\n"); } =20 - if (!(disabled_tests & SBI_PMU_TEST_EVENTS)) { + if (!(targs.disabled_tests & SBI_PMU_TEST_EVENTS)) { test_vm_events_test(test_pmu_events); pr_info("SBI PMU event verification test : PASS\n"); } =20 - if (!(disabled_tests & SBI_PMU_TEST_SNAPSHOT)) { + if (!(targs.disabled_tests & SBI_PMU_TEST_SNAPSHOT)) { test_vm_events_snapshot_test(test_pmu_events_snaphost); pr_info("SBI PMU event verification with snapshot test : PASS\n"); } =20 - if (!(disabled_tests & SBI_PMU_TEST_OVERFLOW)) { + if (!(targs.disabled_tests & SBI_PMU_TEST_OVERFLOW)) { test_vm_events_overflow(test_pmu_events_overflow); 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Wed, 26 Feb 2025 12:25:14 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7347a7f7de2sm4100963b3a.106.2025.02.26.12.25.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Feb 2025 12:25:14 -0800 (PST) From: Atish Patra Date: Wed, 26 Feb 2025 12:25:06 -0800 Subject: [PATCH 4/4] KVM: riscv: selftests: Allow number of interrupts to be configurable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250226-kvm_pmu_improve-v1-4-74c058c2bf6d@rivosinc.com> References: <20250226-kvm_pmu_improve-v1-0-74c058c2bf6d@rivosinc.com> In-Reply-To: <20250226-kvm_pmu_improve-v1-0-74c058c2bf6d@rivosinc.com> To: Anup Patel , Atish Patra , Paul Walmsley , Palmer Dabbelt , Andrew Jones , Paolo Bonzini , Shuah Khan Cc: kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, Atish Patra X-Mailer: b4 0.15-dev-13183 It is helpful to vary the number of the LCOFI interrupts generated by the overflow test. Allow additional argument for overflow test to accommodate that. It can be easily cross-validated with /proc/interrupts output in the host. Signed-off-by: Atish Patra --- tools/testing/selftests/kvm/riscv/sbi_pmu_test.c | 36 ++++++++++++++++++++= ---- 1 file changed, 30 insertions(+), 6 deletions(-) diff --git a/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c b/tools/testi= ng/selftests/kvm/riscv/sbi_pmu_test.c index 533b76d0de82..7c273a1adb17 100644 --- a/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c +++ b/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c @@ -39,8 +39,10 @@ static bool illegal_handler_invoked; #define SBI_PMU_TEST_SNAPSHOT BIT(2) #define SBI_PMU_TEST_OVERFLOW BIT(3) =20 +#define SBI_PMU_OVERFLOW_IRQNUM_DEFAULT 5 struct test_args { int disabled_tests; + int overflow_irqnum; }; =20 static struct test_args targs; @@ -478,7 +480,7 @@ static void test_pmu_events_snaphost(void) =20 static void test_pmu_events_overflow(void) { - int num_counters =3D 0; + int num_counters =3D 0, i =3D 0; =20 /* Verify presence of SBI PMU and minimum requrired SBI version */ verify_sbi_requirement_assert(); @@ -495,11 +497,15 @@ static void test_pmu_events_overflow(void) * Qemu supports overflow for cycle/instruction. * This test may fail on any platform that do not support overflow for th= ese two events. */ - test_pmu_event_overflow(SBI_PMU_HW_CPU_CYCLES); - GUEST_ASSERT_EQ(vcpu_shared_irq_count, 1); + for (i =3D 0; i < targs.overflow_irqnum; i++) + test_pmu_event_overflow(SBI_PMU_HW_CPU_CYCLES); + GUEST_ASSERT_EQ(vcpu_shared_irq_count, targs.overflow_irqnum); + + vcpu_shared_irq_count =3D 0; =20 - test_pmu_event_overflow(SBI_PMU_HW_INSTRUCTIONS); - GUEST_ASSERT_EQ(vcpu_shared_irq_count, 2); + for (i =3D 0; i < targs.overflow_irqnum; i++) + test_pmu_event_overflow(SBI_PMU_HW_INSTRUCTIONS); + GUEST_ASSERT_EQ(vcpu_shared_irq_count, targs.overflow_irqnum); =20 GUEST_DONE(); } @@ -621,8 +627,11 @@ static void test_vm_events_overflow(void *guest_code) =20 static void test_print_help(char *name) { - pr_info("Usage: %s [-h] [-t ]\n", name); + pr_info("Usage: %s [-h] [-t ] [-n ]\n", + name); pr_info("\t-t: Test to run (default all). Available tests are 'basic', 'e= vents', 'snapshot', 'overflow'\n"); + pr_info("\t-n: Number of LCOFI interrupt to trigger for each event in ove= rflow test (default: %d)\n", + SBI_PMU_OVERFLOW_IRQNUM_DEFAULT); pr_info("\t-h: print this help screen\n"); } =20 @@ -631,6 +640,8 @@ static bool parse_args(int argc, char *argv[]) int opt; int temp_disabled_tests =3D SBI_PMU_TEST_BASIC | SBI_PMU_TEST_EVENTS | SB= I_PMU_TEST_SNAPSHOT | SBI_PMU_TEST_OVERFLOW; + int overflow_interrupts =3D -1; + while ((opt =3D getopt(argc, argv, "h:t:n:")) !=3D -1) { switch (opt) { case 't': @@ -646,12 +657,24 @@ static bool parse_args(int argc, char *argv[]) goto done; targs.disabled_tests =3D temp_disabled_tests; break; + case 'n': + overflow_interrupts =3D atoi_positive("Number of LCOFI", optarg); + break; case 'h': default: goto done; } } =20 + if (overflow_interrupts > 0) { + if (targs.disabled_tests & SBI_PMU_TEST_OVERFLOW) { + pr_info("-n option is only available for overflow test\n"); + goto done; + } else { + targs.overflow_irqnum =3D overflow_interrupts; + } + } + return true; done: test_print_help(argv[0]); @@ -661,6 +684,7 @@ static bool parse_args(int argc, char *argv[]) int main(int argc, char *argv[]) { targs.disabled_tests =3D 0; + targs.overflow_irqnum =3D SBI_PMU_OVERFLOW_IRQNUM_DEFAULT; =20 if (!parse_args(argc, argv)) exit(KSFT_SKIP); --=20 2.43.0