From nobody Thu Dec 18 20:33:03 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CD2A6197A7F; Wed, 26 Feb 2025 05:48:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740548893; cv=none; b=b/jSYCS08KgqwTpxY5MxNGPH8JfBs2LBlnXhlmt9ETw6pWBup1CjlSfWUggBdhjcyidb9GuEVfjmbtsN2IiTthWmhuK3kWTiTdRqLb73g3pN4JqqaxgItUsy8Rj1Sy8v6Q6F0tEAedk6fsOF+4QZvXGRNObBSQozRF4O2meo6DM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740548893; c=relaxed/simple; bh=gFcgMIS9ztIZn6S2K6MNHWlWfjjJX8W7NeJumA0V9vc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ROcsY+90iFrIEN3irfj5dcI0JVs5Ks8E5KkIgaNrB86kb/3u433y3p19CYAgNPij19O/GRhFG/HEgbEzXBCPmGE/56YSSvE+qS9xRHM3REQEg4+RaK/hr4a1q9MrRzzF0TG1ZI/Wf2mypyPh8JSfz93B9UDijGNIT6aLVCLzZf4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=uJ/8z1Oe; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="uJ/8z1Oe" Received: by smtp.kernel.org (Postfix) with ESMTPS id 69FECC4CEEA; Wed, 26 Feb 2025 05:48:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1740548893; bh=gFcgMIS9ztIZn6S2K6MNHWlWfjjJX8W7NeJumA0V9vc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=uJ/8z1OekqM6+Ovqkn/Xl23EUSQPr0gaRGLiARhL+4bXxwMRVgpQ9s4wT4HNFET8e yhCKuCZJJIcKfApT2vcZDp7WdCsh/JFzDNqU/nPS38MHfP3Dv75EFfdShIVrGDstIm wzMO+ETl/HgSPVS0O+720dzLcPVFacFD+E6fa2b7lyH1IwACNfiIY4ken+NqZv++S5 ABz7FUFQwoMpHCjg6xapTQmJzA7oxeXJ/ukMNH94sSqbek8o4RFQ5VnwfB8bXUfD99 Q9IKk7DAKQWCW82TyLpeBhwEzD6YAZU0vJVIiNOORQeoFabY0+EE90ncW7kjGoh3RS F6OQ7j1Yd5R8Q== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 53BF9C19776; Wed, 26 Feb 2025 05:48:13 +0000 (UTC) From: Xianwei Zhao via B4 Relay Date: Wed, 26 Feb 2025 13:47:53 +0800 Subject: [PATCH v2 2/4] irqchip: Add support for Amlogic A4 and A5 SoCs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250226-irqchip-gpio-a4-a5-v2-2-c55b1050cb55@amlogic.com> References: <20250226-irqchip-gpio-a4-a5-v2-0-c55b1050cb55@amlogic.com> In-Reply-To: <20250226-irqchip-gpio-a4-a5-v2-0-c55b1050cb55@amlogic.com> To: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Heiner Kallweit Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, Xianwei Zhao X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1740548891; l=5268; i=xianwei.zhao@amlogic.com; s=20231208; h=from:subject:message-id; bh=ShCEtX+584NPfGq4QXGBKe8uO5ZA7smL2hEHYLb1QYg=; b=s2CUePXilok0VUMnzCNHy4hsYxfXpUAeCrQXm6Cs95dLuJtLcuLdFRTJymXc80r/6Sv+e15rg JEAEh5EEiMHAoaFI/qBA6Um0C0aRnO0IF8pmNBTykdySJ8zj4QyP/K2 X-Developer-Key: i=xianwei.zhao@amlogic.com; a=ed25519; pk=o4fDH8ZXL6xQg5h17eNzRljf6pwZHWWjqcOSsj3dW24= X-Endpoint-Received: by B4 Relay for xianwei.zhao@amlogic.com/20231208 with auth_id=107 X-Original-From: Xianwei Zhao Reply-To: xianwei.zhao@amlogic.com From: Xianwei Zhao The Amlogic A4 SoCs support 12 GPIO IRQ lines and 2 AO GPIO IRQ lines, A5 SoCs support 12 GPIO IRQ lines, details are as below. A4 IRQ Number: - 72:55 18 pins on bank T - 54:32 23 pins on bank X - 31:16 16 pins on bank D - 15:14 2 pins on bank E - 13:0 14 pins on bank B A4 AO IRQ Number: - 7 1 pin on bank TESTN - 6:0 7 pins on bank AO A5 IRQ Number: - 98 1 pin on bank TESTN - 97:82 16 pins on bank Z - 81:62 20 pins on bank X - 61:48 14 pins on bank T - 47:32 16 pins on bank D - 31:27 5 pins on bank H - 26:25 2 pins on bank E - 24:14 11 pins on bank C - 13:0 14 pins on bank B Signed-off-by: Xianwei Zhao --- drivers/irqchip/irq-meson-gpio.c | 42 +++++++++++++++++++++++++++++++++++-= ---- 1 file changed, 37 insertions(+), 5 deletions(-) diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-g= pio.c index cd789fa51519..f1cf0c228ca4 100644 --- a/drivers/irqchip/irq-meson-gpio.c +++ b/drivers/irqchip/irq-meson-gpio.c @@ -26,8 +26,6 @@ =20 /* use for A1 like chips */ #define REG_PIN_A1_SEL 0x04 -/* Used for s4 chips */ -#define REG_EDGE_POL_S4 0x1c =20 /* * Note: The S905X3 datasheet reports that BOTH_EDGE is controlled by @@ -57,6 +55,8 @@ static int meson8_gpio_irq_set_type(struct meson_gpio_irq= _controller *ctl, unsigned int type, u32 *channel_hwirq); static int meson_s4_gpio_irq_set_type(struct meson_gpio_irq_controller *ct= l, unsigned int type, u32 *channel_hwirq); +static int meson_ao_gpio_irq_set_type(struct meson_gpio_irq_controller *ct= l, + unsigned int type, u32 *channel_hwirq); =20 struct irq_ctl_ops { void (*gpio_irq_sel_pin)(struct meson_gpio_irq_controller *ctl, @@ -72,6 +72,7 @@ struct meson_gpio_irq_params { bool support_edge_both; unsigned int edge_both_offset; unsigned int edge_single_offset; + unsigned int edge_pol_reg; unsigned int pol_low_offset; unsigned int pin_sel_mask; struct irq_ctl_ops ops; @@ -105,6 +106,18 @@ struct meson_gpio_irq_params { .pin_sel_mask =3D 0x7f, \ .nr_channels =3D 8, \ =20 +#define INIT_MESON_A4_AO_COMMON_DATA(irqs) \ + INIT_MESON_COMMON(irqs, meson_a1_gpio_irq_init, \ + meson_a1_gpio_irq_sel_pin, \ + meson_s4_gpio_irq_set_type) \ + .support_edge_both =3D true, \ + .edge_both_offset =3D 0, \ + .edge_single_offset =3D 12, \ + .edge_pol_reg =3D 0x8, \ + .pol_low_offset =3D 0, \ + .pin_sel_mask =3D 0xff, \ + .nr_channels =3D 2, \ + #define INIT_MESON_S4_COMMON_DATA(irqs) \ INIT_MESON_COMMON(irqs, meson_a1_gpio_irq_init, \ meson_a1_gpio_irq_sel_pin, \ @@ -112,6 +125,7 @@ struct meson_gpio_irq_params { .support_edge_both =3D true, \ .edge_both_offset =3D 0, \ .edge_single_offset =3D 12, \ + .edge_pol_reg =3D 0x1c, \ .pol_low_offset =3D 0, \ .pin_sel_mask =3D 0xff, \ .nr_channels =3D 12, \ @@ -146,6 +160,18 @@ static const struct meson_gpio_irq_params a1_params = =3D { INIT_MESON_A1_COMMON_DATA(62) }; =20 +static const struct meson_gpio_irq_params a4_params =3D { + INIT_MESON_S4_COMMON_DATA(81) +}; + +static const struct meson_gpio_irq_params a4_ao_params =3D { + INIT_MESON_A4_AO_COMMON_DATA(8) +}; + +static const struct meson_gpio_irq_params a5_params =3D { + INIT_MESON_S4_COMMON_DATA(99) +}; + static const struct meson_gpio_irq_params s4_params =3D { INIT_MESON_S4_COMMON_DATA(82) }; @@ -168,6 +194,9 @@ static const struct of_device_id meson_irq_gpio_matches= [] __maybe_unused =3D { { .compatible =3D "amlogic,meson-sm1-gpio-intc", .data =3D &sm1_params }, { .compatible =3D "amlogic,meson-a1-gpio-intc", .data =3D &a1_params }, { .compatible =3D "amlogic,meson-s4-gpio-intc", .data =3D &s4_params }, + { .compatible =3D "amlogic,a4-gpio-ao-intc", .data =3D &a4_ao_params }, + { .compatible =3D "amlogic,a4-gpio-intc", .data =3D &a4_params }, + { .compatible =3D "amlogic,a5-gpio-intc", .data =3D &a5_params }, { .compatible =3D "amlogic,c3-gpio-intc", .data =3D &c3_params }, { .compatible =3D "amlogic,t7-gpio-intc", .data =3D &t7_params }, { } @@ -358,16 +387,19 @@ static int meson_s4_gpio_irq_set_type(struct meson_gp= io_irq_controller *ctl, { u32 val =3D 0; unsigned int idx; + const struct meson_gpio_irq_params *params; + + params =3D ctl->params; =20 idx =3D meson_gpio_irq_get_channel_idx(ctl, channel_hwirq); =20 type &=3D IRQ_TYPE_SENSE_MASK; =20 - meson_gpio_irq_update_bits(ctl, REG_EDGE_POL_S4, BIT(idx), 0); + meson_gpio_irq_update_bits(ctl, params->edge_pol_reg, BIT(idx), 0); =20 if (type =3D=3D IRQ_TYPE_EDGE_BOTH) { val |=3D BIT(ctl->params->edge_both_offset + idx); - meson_gpio_irq_update_bits(ctl, REG_EDGE_POL_S4, + meson_gpio_irq_update_bits(ctl, params->edge_pol_reg, BIT(ctl->params->edge_both_offset + idx), val); return 0; } @@ -378,7 +410,7 @@ static int meson_s4_gpio_irq_set_type(struct meson_gpio= _irq_controller *ctl, if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) val |=3D BIT(ctl->params->edge_single_offset + idx); =20 - meson_gpio_irq_update_bits(ctl, REG_EDGE_POL, + meson_gpio_irq_update_bits(ctl, params->edge_pol_reg, BIT(idx) | BIT(12 + idx), val); return 0; }; --=20 2.37.1