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Tue, 25 Feb 2025 12:18:37 +0000 (GMT) Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTP id 51PCIYYg004545; Tue, 25 Feb 2025 12:18:34 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 44y7nkx1yc-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 25 Feb 2025 12:18:34 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 51PCIYAQ004513; Tue, 25 Feb 2025 12:18:34 GMT Received: from hu-devc-hyd-u22-c.qualcomm.com (hu-amakhija-hyd.qualcomm.com [10.213.99.91]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 51PCIYbf004501 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 25 Feb 2025 12:18:34 +0000 Received: by hu-devc-hyd-u22-c.qualcomm.com (Postfix, from userid 4090850) id A315A58B; Tue, 25 Feb 2025 17:48:32 +0530 (+0530) From: Ayushi Makhija To: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ayushi Makhija , robdclark@gmail.com, dmitry.baryshkov@linaro.org, sean@poorly.run, marijn.suijten@somainline.org, andersson@kernel.org, robh@kernel.org, robh+dt@kernel.org, krzk+dt@kernel.org, konradybcio@kernel.org, conor+dt@kernel.org, andrzej.hajda@intel.com, neil.armstrong@linaro.org, rfoss@kernel.org, Laurent.pinchart@ideasonboard.com, jonas@kwiboo.se, jernej.skrabec@gmail.com, quic_abhinavk@quicinc.com, quic_rajeevny@quicinc.com, quic_vproddut@quicinc.com, quic_jesszhan@quicinc.com Subject: [PATCH 07/11] arm64: dts: qcom: sa8775p-ride: add anx7625 DSI to DP bridge nodes Date: Tue, 25 Feb 2025 17:48:20 +0530 Message-Id: <20250225121824.3869719-8-quic_amakhija@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250225121824.3869719-1-quic_amakhija@quicinc.com> References: <20250225121824.3869719-1-quic_amakhija@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: _SL81gX0XeJnKqcA5a3whcdoQQugG1TX X-Proofpoint-GUID: _SL81gX0XeJnKqcA5a3whcdoQQugG1TX X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-25_04,2025-02-25_03,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 bulkscore=0 impostorscore=0 spamscore=0 mlxlogscore=999 lowpriorityscore=0 mlxscore=0 adultscore=0 malwarescore=0 clxscore=1015 phishscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2502100000 definitions=main-2502250086 Content-Type: text/plain; charset="utf-8" Add anx7625 DSI to DP bridge device nodes. Signed-off-by: Ayushi Makhija --- arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi | 136 ++++++++++++++++++++- 1 file changed, 135 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi b/arch/arm64/boot/d= ts/qcom/sa8775p-ride.dtsi index 175f8b1e3b2d..151f66512303 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi @@ -517,9 +517,128 @@ &i2c11 { =20 &i2c18 { clock-frequency =3D <400000>; - pinctrl-0 =3D <&qup_i2c18_default>; + pinctrl-0 =3D <&qup_i2c18_default>, + <&io_expander_intr_active>, + <&io_expander_reset_active>; pinctrl-names =3D "default"; + status =3D "okay"; + + io_expander: gpio@74 { + compatible =3D "ti,tca9539"; + reg =3D <0x74>; + interrupt-parent =3D <&tlmm>; + interrupts =3D <98 IRQ_TYPE_EDGE_BOTH>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + + pinctrl-0 =3D <&dsi0_int_pin>, + <&dsi0_cbl_det_pin>, + <&dsi1_int_pin>, + <&dsi1_cbl_det_pin>; + pinctrl-names =3D "default"; + + dsi0_int_pin: gpio2_cfg { + pins =3D "gpio2"; + input-enable; + bias-disable; + }; + + dsi0_cbl_det_pin: gpio3_cfg { + pins =3D "gpio3"; + bias-pull-down; + }; + + dsi1_int_pin: gpio10_cfg { + pins =3D "gpio10"; + input-enable; + bias-disable; + }; + + dsi1_cbl_det_pin: gpio11_cfg { + pins =3D "gpio11"; + bias-pull-down; + }; + }; + + i2c-mux@70 { + compatible =3D "nxp,pca9543"; + #address-cells =3D <1>; + + #size-cells =3D <0>; + reg =3D <0x70>; + + i2c@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + anx_bridge_1: anx7625@58 { + compatible =3D "analogix,anx7625"; + reg =3D <0x58>; + interrupt-parent =3D <&io_expander>; + interrupts =3D <2 IRQ_TYPE_EDGE_FALLING>; + enable-gpios =3D <&io_expander 1 0>; + reset-gpios =3D <&io_expander 0 0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + dsi2dp_bridge_1_in: port@0 { + reg =3D <0>; + + anx7625_1_in: endpoint { + remote-endpoint =3D <&mdss0_dsi0_out>; + }; + }; + + dsi2dp_bridge_1_out: port@1 { + reg =3D <1>; + + anx7625_1_out: endpoint { }; + }; + }; + }; + }; + + i2c@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + anx_bridge_2: anx7625@58 { + compatible =3D "analogix,anx7625"; + reg =3D <0x58>; + interrupt-parent =3D <&io_expander>; + interrupts =3D <10 IRQ_TYPE_EDGE_FALLING>; + enable-gpios =3D <&io_expander 9 0>; + reset-gpios =3D <&io_expander 8 0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + dsi2dp_bridge_2_in: port@0 { + reg =3D <0>; + + anx7625_2_in: endpoint { + remote-endpoint =3D <&mdss0_dsi1_out>; + }; + }; + + dsi2dp_bridge_2_out: port@1 { + reg =3D <1>; + + anx7625_2_out: endpoint { }; + }; + }; + }; + }; + }; + }; =20 &mdss0 { @@ -714,6 +833,21 @@ ethernet0_mdio: ethernet0-mdio-pins { }; }; =20 + io_expander_intr_active: io-expander-intr-active-state { + pins =3D "gpio98"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + io_expander_reset_active: io-expander-reset-active-state { + pins =3D "gpio97"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + output-high; + }; + qup_uart10_default: qup-uart10-state { pins =3D "gpio46", "gpio47"; function =3D "qup1_se3"; --=20 2.34.1