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Tue, 25 Feb 2025 01:05:20 -0800 (PST) From: Neil Armstrong Date: Tue, 25 Feb 2025 10:05:12 +0100 Subject: [PATCH 4/4] media: platform: qcom/iris: add sm8650 support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250225-topic-sm8x50-iris-v10-v1-4-128ef05d9665@linaro.org> References: <20250225-topic-sm8x50-iris-v10-v1-0-128ef05d9665@linaro.org> In-Reply-To: <20250225-topic-sm8x50-iris-v10-v1-0-128ef05d9665@linaro.org> To: Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel Cc: linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=10895; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=v00FvgOpYb+n3FGLO6d0TWMNJxGJTCgKGQ6XpRBKpZQ=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBnvYfM2Pkodfx6ekVFlWwGC6OZlaJQwd1Zg59AtaMQ ll0ke2GJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZ72HzAAKCRB33NvayMhJ0fBPD/ 0ex0MrvnJ4VSu61N+p3fbe5XoMW7FsUtGQlHerBoFYV8dyvkXHnCZ2+ZaVec//9iZVqr9MpWFWxm1v jVGnzgby4nvCV4+oyMkt7P7lkRq9twRscWd9yk2OBrmGSsE7XXjpElGq1xUx9GJFuetiO5wfrn6e6z yhT9daI5GNFgV5Tgl8mwgDDqeH54iGELuw4VjEzJQwFsDW9MXVUUSdBeLhp77kCHOA+Ms1Pm8p8mQn AVf9v531WrAX2RuwVVd/IUOWRrE+g4OkGYdj9GzR39agzDkub9NnUbPV6vQLfgXyTDmJJJ8NuRie6i fMeGkFccjwbdrxwbHVU3kLQcmcYHgSfGd3Tn3ouAkNvUiws+S932ncBGB93O4nitGwN7JwLy/FM4Yv hBGx/S4W/qKccEm4YznMmOMochU57GmpWTlSGDVS5KKDTsjH9BHsFCovNCa/aaumrGKBYhUgPbWlTv hx7WoNhSxrbg/LTFTZBWCKOJJsYcDeq4XRtUcBeCEt1I3pbiI05spvY78B8on2PUPAmo0ml5XOfc5k 0rHcuWDcZoqNS6Gon7K0pa202zm6ThDhJ1Ql8MFOSviFH31j7UhhLjKbCIhfeDOKy3IyD3OOSqMBxD QaASEjQBc9otjwMmnuayINzAqi6vNWQBC+EshgWVc/YLsPz0wMyh55Qz7SCQ== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Add support for the SM8650 platform by re-using the SM8550 definitions and using the vpu33 ops. The SM8650/vpu33 requires more reset lines, but the H.284 decoder capabilities are identical. Signed-off-by: Neil Armstrong --- drivers/media/platform/qcom/iris/Makefile | 1 + .../platform/qcom/iris/iris_platform_common.h | 1 + .../platform/qcom/iris/iris_platform_sm8650.c | 266 +++++++++++++++++= ++++ drivers/media/platform/qcom/iris/iris_probe.c | 4 + 4 files changed, 272 insertions(+) diff --git a/drivers/media/platform/qcom/iris/Makefile b/drivers/media/plat= form/qcom/iris/Makefile index 6b64c9988505afd9707c704449d60bb53209229f..4caba81a95b806b9fa4937d9c79= 73031dea43d0e 100644 --- a/drivers/media/platform/qcom/iris/Makefile +++ b/drivers/media/platform/qcom/iris/Makefile @@ -11,6 +11,7 @@ qcom-iris-objs +=3D \ iris_hfi_gen2_response.o \ iris_hfi_queue.o \ iris_platform_sm8550.o \ + iris_platform_sm8650.o \ iris_power.o \ iris_probe.o \ iris_resources.o \ diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/driv= ers/media/platform/qcom/iris/iris_platform_common.h index f6b15d2805fb2004699709bb12cd7ce9b052180c..75e266a6b718acb8518079c2125= dfb30435cbf2b 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -35,6 +35,7 @@ enum pipe_type { =20 extern struct iris_platform_data sm8250_data; extern struct iris_platform_data sm8550_data; +extern struct iris_platform_data sm8650_data; =20 enum platform_clk_type { IRIS_AXI_CLK, diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8650.c b/driv= ers/media/platform/qcom/iris/iris_platform_sm8650.c new file mode 100644 index 0000000000000000000000000000000000000000..823e349dead2606129e52d6d2d6= 74cb2550eaf17 --- /dev/null +++ b/drivers/media/platform/qcom/iris/iris_platform_sm8650.c @@ -0,0 +1,266 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights res= erved. + */ + +#include "iris_core.h" +#include "iris_ctrls.h" +#include "iris_hfi_gen2.h" +#include "iris_hfi_gen2_defines.h" +#include "iris_platform_common.h" +#include "iris_vpu_common.h" + +#define VIDEO_ARCH_LX 1 + +static struct platform_inst_fw_cap inst_fw_cap_sm8650[] =3D { + { + .cap_id =3D PROFILE, + .min =3D V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE, + .max =3D V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE) | + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE) | + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_MAIN) | + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_HIGH) | + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH), + .value =3D V4L2_MPEG_VIDEO_H264_PROFILE_HIGH, + .hfi_id =3D HFI_PROP_PROFILE, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_u32_enum, + }, + { + .cap_id =3D LEVEL, + .min =3D V4L2_MPEG_VIDEO_H264_LEVEL_1_0, + .max =3D V4L2_MPEG_VIDEO_H264_LEVEL_6_2, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1B) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_3) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_6_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_6_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_6_2), + .value =3D V4L2_MPEG_VIDEO_H264_LEVEL_6_1, + .hfi_id =3D HFI_PROP_LEVEL, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_u32_enum, + }, + { + .cap_id =3D INPUT_BUF_HOST_MAX_COUNT, + .min =3D DEFAULT_MAX_HOST_BUF_COUNT, + .max =3D DEFAULT_MAX_HOST_BURST_BUF_COUNT, + .step_or_mask =3D 1, + .value =3D DEFAULT_MAX_HOST_BUF_COUNT, + .hfi_id =3D HFI_PROP_BUFFER_HOST_MAX_COUNT, + .flags =3D CAP_FLAG_INPUT_PORT, + .set =3D iris_set_u32, + }, + { + .cap_id =3D STAGE, + .min =3D STAGE_1, + .max =3D STAGE_2, + .step_or_mask =3D 1, + .value =3D STAGE_2, + .hfi_id =3D HFI_PROP_STAGE, + .set =3D iris_set_stage, + }, + { + .cap_id =3D PIPE, + .min =3D PIPE_1, + .max =3D PIPE_4, + .step_or_mask =3D 1, + .value =3D PIPE_4, + .hfi_id =3D HFI_PROP_PIPE, + .set =3D iris_set_pipe, + }, + { + .cap_id =3D POC, + .min =3D 0, + .max =3D 2, + .step_or_mask =3D 1, + .value =3D 1, + .hfi_id =3D HFI_PROP_PIC_ORDER_CNT_TYPE, + }, + { + .cap_id =3D CODED_FRAMES, + .min =3D CODED_FRAMES_PROGRESSIVE, + .max =3D CODED_FRAMES_PROGRESSIVE, + .step_or_mask =3D 0, + .value =3D CODED_FRAMES_PROGRESSIVE, + .hfi_id =3D HFI_PROP_CODED_FRAMES, + }, + { + .cap_id =3D BIT_DEPTH, + .min =3D BIT_DEPTH_8, + .max =3D BIT_DEPTH_8, + .step_or_mask =3D 1, + .value =3D BIT_DEPTH_8, + .hfi_id =3D HFI_PROP_LUMA_CHROMA_BIT_DEPTH, + }, + { + .cap_id =3D RAP_FRAME, + .min =3D 0, + .max =3D 1, + .step_or_mask =3D 1, + .value =3D 1, + .hfi_id =3D HFI_PROP_DEC_START_FROM_RAP_FRAME, + .flags =3D CAP_FLAG_INPUT_PORT, + .set =3D iris_set_u32, + }, +}; + +static struct platform_inst_caps platform_inst_cap_sm8650 =3D { + .min_frame_width =3D 96, + .max_frame_width =3D 8192, + .min_frame_height =3D 96, + .max_frame_height =3D 8192, + .max_mbpf =3D (8192 * 4352) / 256, + .mb_cycles_vpp =3D 200, + .mb_cycles_fw =3D 489583, + .mb_cycles_fw_vpp =3D 66234, + .num_comv =3D 0, +}; + +static void iris_set_sm8650_preset_registers(struct iris_core *core) +{ + writel(0x0, core->reg_base + 0xB0088); +} + +static const struct icc_info sm8650_icc_table[] =3D { + { "cpu-cfg", 1000, 1000 }, + { "video-mem", 1000, 15000000 }, +}; + +static const char * const sm8650_clk_reset_table[] =3D { "bus", "xo", "cor= e" }; + +static const struct bw_info sm8650_bw_table_dec[] =3D { + { ((4096 * 2160) / 256) * 60, 1608000 }, + { ((4096 * 2160) / 256) * 30, 826000 }, + { ((1920 * 1080) / 256) * 60, 567000 }, + { ((1920 * 1080) / 256) * 30, 294000 }, +}; + +static const char * const sm8650_pmdomain_table[] =3D { "venus", "vcodec0"= }; + +static const char * const sm8650_opp_pd_table[] =3D { "mxc", "mmcx" }; + +static const struct platform_clk_data sm8650_clk_table[] =3D { + {IRIS_AXI_CLK, "iface" }, + {IRIS_CTRL_CLK, "core" }, + {IRIS_HW_CLK, "vcodec0_core" }, +}; + +static struct ubwc_config_data ubwc_config_sm8650 =3D { + .max_channels =3D 8, + .mal_length =3D 32, + .highest_bank_bit =3D 16, + .bank_swzl_level =3D 0, + .bank_swz2_level =3D 1, + .bank_swz3_level =3D 1, + .bank_spreading =3D 1, +}; + +static struct tz_cp_config tz_cp_config_sm8650 =3D { + .cp_start =3D 0, + .cp_size =3D 0x25800000, + .cp_nonpixel_start =3D 0x01000000, + .cp_nonpixel_size =3D 0x24800000, +}; + +static const u32 sm8650_vdec_input_config_params[] =3D { + HFI_PROP_BITSTREAM_RESOLUTION, + HFI_PROP_CROP_OFFSETS, + HFI_PROP_CODED_FRAMES, + HFI_PROP_BUFFER_FW_MIN_OUTPUT_COUNT, + HFI_PROP_PIC_ORDER_CNT_TYPE, + HFI_PROP_PROFILE, + HFI_PROP_LEVEL, + HFI_PROP_SIGNAL_COLOR_INFO, +}; + +static const u32 sm8650_vdec_output_config_params[] =3D { + HFI_PROP_COLOR_FORMAT, + HFI_PROP_LINEAR_STRIDE_SCANLINE, +}; + +static const u32 sm8650_vdec_subscribe_input_properties[] =3D { + HFI_PROP_NO_OUTPUT, +}; + +static const u32 sm8650_vdec_subscribe_output_properties[] =3D { + HFI_PROP_PICTURE_TYPE, + HFI_PROP_CABAC_SESSION, +}; + +static const u32 sm8650_dec_ip_int_buf_tbl[] =3D { + BUF_BIN, + BUF_COMV, + BUF_NON_COMV, + BUF_LINE, +}; + +static const u32 sm8650_dec_op_int_buf_tbl[] =3D { + BUF_DPB, +}; + +struct iris_platform_data sm8650_data =3D { + .get_instance =3D iris_hfi_gen2_get_instance, + .init_hfi_command_ops =3D iris_hfi_gen2_command_ops_init, + .init_hfi_response_ops =3D iris_hfi_gen2_response_ops_init, + .vpu_ops =3D &iris_vpu33_ops, + .set_preset_registers =3D iris_set_sm8650_preset_registers, + .icc_tbl =3D sm8650_icc_table, + .icc_tbl_size =3D ARRAY_SIZE(sm8650_icc_table), + .clk_rst_tbl =3D sm8650_clk_reset_table, + .clk_rst_tbl_size =3D ARRAY_SIZE(sm8650_clk_reset_table), + .bw_tbl_dec =3D sm8650_bw_table_dec, + .bw_tbl_dec_size =3D ARRAY_SIZE(sm8650_bw_table_dec), + .pmdomain_tbl =3D sm8650_pmdomain_table, + .pmdomain_tbl_size =3D ARRAY_SIZE(sm8650_pmdomain_table), + .opp_pd_tbl =3D sm8650_opp_pd_table, + .opp_pd_tbl_size =3D ARRAY_SIZE(sm8650_opp_pd_table), + .clk_tbl =3D sm8650_clk_table, + .clk_tbl_size =3D ARRAY_SIZE(sm8650_clk_table), + /* Upper bound of DMA address range */ + .dma_mask =3D 0xe0000000 - 1, + .fwname =3D "qcom/vpu/vpu33_p4.mbn", + .pas_id =3D IRIS_PAS_ID, + .inst_caps =3D &platform_inst_cap_sm8650, + .inst_fw_caps =3D inst_fw_cap_sm8650, + .inst_fw_caps_size =3D ARRAY_SIZE(inst_fw_cap_sm8650), + .tz_cp_config_data =3D &tz_cp_config_sm8650, + .core_arch =3D VIDEO_ARCH_LX, + .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, + .ubwc_config =3D &ubwc_config_sm8650, + .num_vpp_pipe =3D 4, + .max_session_count =3D 16, + .max_core_mbpf =3D ((8192 * 4352) / 256) * 2, + .input_config_params =3D + sm8650_vdec_input_config_params, + .input_config_params_size =3D + ARRAY_SIZE(sm8650_vdec_input_config_params), + .output_config_params =3D + sm8650_vdec_output_config_params, + .output_config_params_size =3D + ARRAY_SIZE(sm8650_vdec_output_config_params), + .dec_input_prop =3D sm8650_vdec_subscribe_input_properties, + .dec_input_prop_size =3D ARRAY_SIZE(sm8650_vdec_subscribe_input_propertie= s), + .dec_output_prop =3D sm8650_vdec_subscribe_output_properties, + .dec_output_prop_size =3D ARRAY_SIZE(sm8650_vdec_subscribe_output_propert= ies), + + .dec_ip_int_buf_tbl =3D sm8650_dec_ip_int_buf_tbl, + .dec_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8650_dec_ip_int_buf_tbl), + .dec_op_int_buf_tbl =3D sm8650_dec_op_int_buf_tbl, + .dec_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8650_dec_op_int_buf_tbl), +}; diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/= platform/qcom/iris/iris_probe.c index aca442dcc153830e6252d1dca87afb38c0b9eb8f..8e6cc1dc529608696e81f2764e9= 0ea3864030125 100644 --- a/drivers/media/platform/qcom/iris/iris_probe.c +++ b/drivers/media/platform/qcom/iris/iris_probe.c @@ -330,6 +330,10 @@ static const struct of_device_id iris_dt_match[] =3D { .data =3D &sm8250_data, }, #endif + { + .compatible =3D "qcom,sm8650-iris", + .data =3D &sm8650_data, + }, { }, }; MODULE_DEVICE_TABLE(of, iris_dt_match); --=20 2.34.1