From nobody Mon Feb 9 23:57:45 2026 Received: from smtp-bc0a.mail.infomaniak.ch (smtp-bc0a.mail.infomaniak.ch [45.157.188.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A86D5267B73 for ; Tue, 25 Feb 2025 11:53:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.157.188.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740484438; cv=none; b=Ci1PAwaEMYPz2/FIL0hFVGdvuab80gGA2+n1nc7sfWYkaTwtX+xsUNqgiSCZxG2l+NCvmU8EsEoRpCyAH7NQBbvy37VjT/NAb9WP6qSL60JtJCfN5D4PzAaR3MpoObrkS8+n76vkq6UcmWfAXVpZsI3awD+rJiP0AAhdpewCfsM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740484438; c=relaxed/simple; bh=QJHAbSlXMItehxt6Q/gk7ZMR6FhGrF/LO/R6H6FIe8U=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=OAE/fuNiz8fUaBnFaEFrDYhCLghgIxOKzTqvrdFZAxcVfXqEGOGo3AlICHl8DIYxRzYcwdBkYIfnmkJRxym5lDw4Yaf0LuMnHS1xhC7kTHDmuLgkMT+/ahZCypB2L1ISecrZj3e4h+VMrt7YDVhrnDkLwzo/rm7QzHBCmxHepbs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=0leil.net; spf=pass smtp.mailfrom=0leil.net; arc=none smtp.client-ip=45.157.188.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=0leil.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=0leil.net Received: from smtp-3-0000.mail.infomaniak.ch (unknown [IPv6:2001:1600:4:17::246b]) by smtp-3-3000.mail.infomaniak.ch (Postfix) with ESMTPS id 4Z2GGN1zmGzPp2; Tue, 25 Feb 2025 12:53:48 +0100 (CET) Received: from unknown by smtp-3-0000.mail.infomaniak.ch (Postfix) with ESMTPA id 4Z2GGM4bc9zCcj; Tue, 25 Feb 2025 12:53:47 +0100 (CET) From: Quentin Schulz Date: Tue, 25 Feb 2025 12:53:29 +0100 Subject: [PATCH v3 1/2] arm64: dts: rockchip: fix pinmux of UART0 for PX30 Ringneck on Haikou Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250225-ringneck-dtbos-v3-1-853a9a6dd597@cherry.de> References: <20250225-ringneck-dtbos-v3-0-853a9a6dd597@cherry.de> In-Reply-To: <20250225-ringneck-dtbos-v3-0-853a9a6dd597@cherry.de> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Quentin Schulz , Farouk Bouabid Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Quentin Schulz , stable@vger.kernel.org X-Mailer: b4 0.14.2 X-Infomaniak-Routing: alpha From: Quentin Schulz UART0 pinmux by default configures GPIO0_B5 in its UART RTS function for UART0. However, by default on Haikou, it is used as GPIO as UART RTS for UART5. Therefore, let's update UART0 pinmux to not configure the pin in that mode, a later commit will make UART5 request the GPIO pinmux. Fixes: c484cf93f61b ("arm64: dts: rockchip: add PX30-=C2=B5Q7 (Ringneck) So= M with Haikou baseboard") Cc: stable@vger.kernel.org Signed-off-by: Quentin Schulz --- arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts b/arch/a= rm64/boot/dts/rockchip/px30-ringneck-haikou.dts index eb9470a00e549fc107603be216a5f714914e7a2c..9a568f3d0a9916dff22222c59e5= e0c94ce226858 100644 --- a/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts +++ b/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts @@ -222,6 +222,7 @@ &u2phy_otg { }; =20 &uart0 { + pinctrl-0 =3D <&uart0_xfer>; status =3D "okay"; }; =20 --=20 2.48.1