From nobody Thu Dec 18 08:27:59 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AA6FD1C84BA for ; Mon, 24 Feb 2025 05:16:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740374188; cv=none; b=W9ji+Ydtp2weyIhjG2BKrJdUXaDHnsv1ahVTqiUfnrGPewlYlHgxIwjR9sCHcgrJrVg7joh0T1/lXmsn8yk+tDMM7bImEPmd/4u/tvFyjgLR30Nn3qeAor7nzmVacD7A4EGIB9jxgSAPT45h18Ap9wewX3kgCZ6X4tFJu1/3VX8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740374188; c=relaxed/simple; bh=IUNYGyLwNXt2mshtCg4MZHI5Zet/iC0sXDLsWw3WF8U=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=XebWJqIP67k+UiVckxn2KJhvd8hq2jc7j+2Y5ZVFxTL4E/c9JY0OADWknaElsgRfEU95nqa7mzw4IkdcmePD3UkUjIxIklsnyOXxtDvtyHg+kvmduKTjel7MRShul9xR9I6k57o0qiMnYfyljIN/pEWtRM9Mavwbm9WajoBcPB0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=NUIRGrUS; arc=none smtp.client-ip=192.198.163.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="NUIRGrUS" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1740374187; x=1771910187; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=IUNYGyLwNXt2mshtCg4MZHI5Zet/iC0sXDLsWw3WF8U=; b=NUIRGrUSmhKv5kjMDnPLnB838vUlk29YKFFHDbH46SJICbEa5TL+jImi CkTMe2K4rh/vnS++CWcHeAXccejnM9MXhzE7C2ZEMGYmFbSrqBs/M1FA8 j3XYfZodIx4xrG/251nknx6bZCwJX0bPkjPfwUVsI5BGqrEe/wFuFtCHH G8MgO/o9mHYQhYh7VDJEiGHbQSoz+SMdPrqmNuwD6Hgb1/nLc3y1TT3HC n2hB02/0wlLia6G5NCHVcuU8w6/Aro9EWzDf/YsJK6Bxp0oC00XaCj7ea R5GPyrgFZ+6Wivzq3Sy2TQtT6f8lyDH9NcBpCKiHJB/yii22a5H0gefuJ w==; X-CSE-ConnectionGUID: Ljs88IvxRmyIFPUZrGqO0w== X-CSE-MsgGUID: yMh1zIP8QAKd+nDvHIUaHA== X-IronPort-AV: E=McAfee;i="6700,10204,11354"; a="45024190" X-IronPort-AV: E=Sophos;i="6.13,309,1732608000"; d="scan'208";a="45024190" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Feb 2025 21:16:27 -0800 X-CSE-ConnectionGUID: 1hGc3zjVTVeU63cMX2FZEg== X-CSE-MsgGUID: CBBIbH5WTe+cGlHSBiY7Ig== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,309,1732608000"; d="scan'208";a="116143380" Received: from allen-box.sh.intel.com ([10.239.159.52]) by fmviesa008.fm.intel.com with ESMTP; 23 Feb 2025 21:16:23 -0800 From: Lu Baolu To: Joerg Roedel , Will Deacon , Robin Murphy , Jason Gunthorpe , Kevin Tian Cc: Dave Jiang , Vinod Koul , Fenghua Yu , Zhangfei Gao , Zhou Wang , iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Jason Gunthorpe , Lu Baolu Subject: [PATCH v2 02/12] iommu/vt-d: Check if SVA is supported when attaching the SVA domain Date: Mon, 24 Feb 2025 13:16:16 +0800 Message-ID: <20250224051627.2956304-3-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250224051627.2956304-1-baolu.lu@linux.intel.com> References: <20250224051627.2956304-1-baolu.lu@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jason Gunthorpe Attach of a SVA domain should fail if SVA is not supported, move the check for SVA support out of IOMMU_DEV_FEAT_SVA and into attach. Also check when allocating a SVA domain to match other drivers. Signed-off-by: Jason Gunthorpe Signed-off-by: Lu Baolu Reviewed-by: Kevin Tian Reviewed-by: Yi Liu --- drivers/iommu/intel/iommu.c | 37 +------------------------------ drivers/iommu/intel/svm.c | 43 +++++++++++++++++++++++++++++++++++++ 2 files changed, 44 insertions(+), 36 deletions(-) diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index cc46098f875b..a4048de66378 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -3851,41 +3851,6 @@ static struct iommu_group *intel_iommu_device_group(= struct device *dev) return generic_device_group(dev); } =20 -static int intel_iommu_enable_sva(struct device *dev) -{ - struct device_domain_info *info =3D dev_iommu_priv_get(dev); - struct intel_iommu *iommu; - - if (!info || dmar_disabled) - return -EINVAL; - - iommu =3D info->iommu; - if (!iommu) - return -EINVAL; - - if (!(iommu->flags & VTD_FLAG_SVM_CAPABLE)) - return -ENODEV; - - if (!info->pasid_enabled || !info->ats_enabled) - return -EINVAL; - - /* - * Devices having device-specific I/O fault handling should not - * support PCI/PRI. The IOMMU side has no means to check the - * capability of device-specific IOPF. Therefore, IOMMU can only - * default that if the device driver enables SVA on a non-PRI - * device, it will handle IOPF in its own way. - */ - if (!info->pri_supported) - return 0; - - /* Devices supporting PRI should have it enabled. */ - if (!info->pri_enabled) - return -EINVAL; - - return 0; -} - static int context_flip_pri(struct device_domain_info *info, bool enable) { struct intel_iommu *iommu =3D info->iommu; @@ -4006,7 +3971,7 @@ intel_iommu_dev_enable_feat(struct device *dev, enum = iommu_dev_features feat) return intel_iommu_enable_iopf(dev); =20 case IOMMU_DEV_FEAT_SVA: - return intel_iommu_enable_sva(dev); + return 0; =20 default: return -ENODEV; diff --git a/drivers/iommu/intel/svm.c b/drivers/iommu/intel/svm.c index f5569347591f..ba93123cb4eb 100644 --- a/drivers/iommu/intel/svm.c +++ b/drivers/iommu/intel/svm.c @@ -110,6 +110,41 @@ static const struct mmu_notifier_ops intel_mmuops =3D { .free_notifier =3D intel_mm_free_notifier, }; =20 +static int intel_iommu_sva_supported(struct device *dev) +{ + struct device_domain_info *info =3D dev_iommu_priv_get(dev); + struct intel_iommu *iommu; + + if (!info || dmar_disabled) + return -EINVAL; + + iommu =3D info->iommu; + if (!iommu) + return -EINVAL; + + if (!(iommu->flags & VTD_FLAG_SVM_CAPABLE)) + return -ENODEV; + + if (!info->pasid_enabled || !info->ats_enabled) + return -EINVAL; + + /* + * Devices having device-specific I/O fault handling should not + * support PCI/PRI. The IOMMU side has no means to check the + * capability of device-specific IOPF. Therefore, IOMMU can only + * default that if the device driver enables SVA on a non-PRI + * device, it will handle IOPF in its own way. + */ + if (!info->pri_supported) + return 0; + + /* Devices supporting PRI should have it enabled. */ + if (!info->pri_enabled) + return -EINVAL; + + return 0; +} + static int intel_svm_set_dev_pasid(struct iommu_domain *domain, struct device *dev, ioasid_t pasid, struct iommu_domain *old) @@ -121,6 +156,10 @@ static int intel_svm_set_dev_pasid(struct iommu_domain= *domain, unsigned long sflags; int ret =3D 0; =20 + ret =3D intel_iommu_sva_supported(dev); + if (ret) + return ret; + dev_pasid =3D domain_add_dev_pasid(domain, dev, pasid); if (IS_ERR(dev_pasid)) return PTR_ERR(dev_pasid); @@ -161,6 +200,10 @@ struct iommu_domain *intel_svm_domain_alloc(struct dev= ice *dev, struct dmar_domain *domain; int ret; =20 + ret =3D intel_iommu_sva_supported(dev); + if (ret) + return ERR_PTR(ret); + domain =3D kzalloc(sizeof(*domain), GFP_KERNEL); if (!domain) return ERR_PTR(-ENOMEM); --=20 2.43.0