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Lin" , Nancy Lin , Singo Chang , "Yongqiang Niu" , Xiandong Wang , Sirius Wang , Xavier Chang , Fei Shao , Chen-yu Tsai , Pin-yen Lin , , , , Subject: [PATCH] mailbox: mtk-cmdq: Refine GCE_GCTL_VALUE setting Date: Mon, 24 Feb 2025 13:01:07 +0800 Message-ID: <20250224050812.3537569-1-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.45.2 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Content-Type: text/plain; charset="utf-8" Add cmdq_gctl_value_toggle() to configure GCE_CTRL_BY_SW and GCE_DDR_EN together in same the GCE_GCTL_VALUE register. Move this function into cmdq_runtime_resume() and cmdq_runtime_suspend() to ensure it can be called when the GCE clock is enabled. Fixes: 7abd037aa581 ("mailbox: mtk-cmdq: add gce ddr enable support flow") Signed-off-by: Jason-JH Lin --- drivers/mailbox/mtk-cmdq-mailbox.c | 41 +++++++++++++----------------- 1 file changed, 17 insertions(+), 24 deletions(-) diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-= mailbox.c index d186865b8dce..be17697d7785 100644 --- a/drivers/mailbox/mtk-cmdq-mailbox.c +++ b/drivers/mailbox/mtk-cmdq-mailbox.c @@ -92,16 +92,17 @@ struct gce_plat { u32 gce_num; }; =20 -static void cmdq_sw_ddr_enable(struct cmdq *cmdq, bool enable) +static void cmdq_gctl_value_toggle(struct cmdq *cmdq, bool ddr_enable) { - WARN_ON(clk_bulk_enable(cmdq->pdata->gce_num, cmdq->clocks)); + u32 val =3D (cmdq->pdata->control_by_sw) ? GCE_CTRL_BY_SW : 0; =20 - if (enable) - writel(GCE_DDR_EN | GCE_CTRL_BY_SW, cmdq->base + GCE_GCTL_VALUE); - else - writel(GCE_CTRL_BY_SW, cmdq->base + GCE_GCTL_VALUE); + if (!cmdq->pdata->control_by_sw && !cmdq->pdata->sw_ddr_en) + return; =20 - clk_bulk_disable(cmdq->pdata->gce_num, cmdq->clocks); + if (cmdq->pdata->sw_ddr_en && ddr_enable) + val |=3D GCE_DDR_EN; + + writel(val, cmdq->base + GCE_GCTL_VALUE); } =20 u8 cmdq_get_shift_pa(struct mbox_chan *chan) @@ -140,16 +141,10 @@ static void cmdq_thread_resume(struct cmdq_thread *th= read) static void cmdq_init(struct cmdq *cmdq) { int i; - u32 gctl_regval =3D 0; =20 WARN_ON(clk_bulk_enable(cmdq->pdata->gce_num, cmdq->clocks)); - if (cmdq->pdata->control_by_sw) - gctl_regval =3D GCE_CTRL_BY_SW; - if (cmdq->pdata->sw_ddr_en) - gctl_regval |=3D GCE_DDR_EN; =20 - if (gctl_regval) - writel(gctl_regval, cmdq->base + GCE_GCTL_VALUE); + cmdq_gctl_value_toggle(cmdq, true); =20 writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base + CMDQ_THR_SLOT_CYCLES); for (i =3D 0; i <=3D CMDQ_MAX_EVENT; i++) @@ -315,14 +310,21 @@ static irqreturn_t cmdq_irq_handler(int irq, void *de= v) static int cmdq_runtime_resume(struct device *dev) { struct cmdq *cmdq =3D dev_get_drvdata(dev); + int ret; =20 - return clk_bulk_enable(cmdq->pdata->gce_num, cmdq->clocks); + ret =3D clk_bulk_enable(cmdq->pdata->gce_num, cmdq->clocks); + if (ret) + return ret; + + cmdq_gctl_value_toggle(cmdq, true); + return 0; } =20 static int cmdq_runtime_suspend(struct device *dev) { struct cmdq *cmdq =3D dev_get_drvdata(dev); =20 + cmdq_gctl_value_toggle(cmdq, false); clk_bulk_disable(cmdq->pdata->gce_num, cmdq->clocks); return 0; } @@ -347,9 +349,6 @@ static int cmdq_suspend(struct device *dev) if (task_running) dev_warn(dev, "exist running task(s) in suspend\n"); =20 - if (cmdq->pdata->sw_ddr_en) - cmdq_sw_ddr_enable(cmdq, false); - return pm_runtime_force_suspend(dev); } =20 @@ -360,9 +359,6 @@ static int cmdq_resume(struct device *dev) WARN_ON(pm_runtime_force_resume(dev)); cmdq->suspended =3D false; =20 - if (cmdq->pdata->sw_ddr_en) - cmdq_sw_ddr_enable(cmdq, true); - return 0; } =20 @@ -370,9 +366,6 @@ static void cmdq_remove(struct platform_device *pdev) { struct cmdq *cmdq =3D platform_get_drvdata(pdev); =20 - if (cmdq->pdata->sw_ddr_en) - cmdq_sw_ddr_enable(cmdq, false); - if (!IS_ENABLED(CONFIG_PM)) cmdq_runtime_suspend(&pdev->dev); =20 --=20 2.43.0