From nobody Thu Dec 18 22:16:20 2025 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.5]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 83F5D204C2A; Sun, 23 Feb 2025 11:31:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.5 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740310284; cv=none; b=Sif1XywHCn+NbeGZhDozvulaO6+CpQwqWC6xvnHaZ35mm+6kgrDSQlJNxJLA6mfZbuuzEWExahmdDqabGZfjAnotoRDd5C9Prc92jbU287/S+irY63wLQxc/uUuyyid79N6/0o13V49Ocv63IU87bSfFAuIGeTye8ebR5VUX3PU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740310284; c=relaxed/simple; bh=28V2fffS9bFBXBhBjk9uctuX0OAj8daq42zXpEqlN2w=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=GA+4D3FWFfcuKrYpdqeVyGgEYrcqGKO74GyYXv3FpnGiheMj3PPmmoSKBT24o9gnSU4oFYXtAF9QEYtGeJvpN56bALwS0mO5X+9wlndmJuWy1CAmJhbwzd6CPrUIrL5wLeI747RIza9YD4wWtRf6yoJK2b55fPs5zYguNSIFelc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=XjfdQZnQ; arc=none smtp.client-ip=220.197.31.5 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="XjfdQZnQ" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:Subject:Date:Message-ID:MIME-Version; bh=8O6s/ Or5PgZ3nOkE6KkXcdydvMMnOex78q09+RFYlpQ=; b=XjfdQZnQ+ARx0XvTY3oli 5aGXA+hog0p6hWeG4bfsPlcyFn49VZxWe3IiW8GDDRdnloGrGkYpxFyYHIH80w/7 UEGOBNaoMiT/Wu0d0uXeaWnbvtI5LuiTmFGA6KlBctVwFotPrvIYo6Nlwq10sCDO VRuKHEdSYNHtDVECjewi48= Received: from ProDesk.. (unknown []) by gzsmtp4 (Coremail) with SMTP id PygvCgBHWqbdBrtnleHpAg--.47651S6; Sun, 23 Feb 2025 19:30:47 +0800 (CST) From: Andy Yan To: heiko@sntech.de Cc: hjc@rock-chips.com, mripard@kernel.org, cristian.ciocaltea@collabora.com, neil.armstrong@linaro.org, yubing.zhang@rock-chips.com, krzk+dt@kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, robh@kernel.org, sebastian.reichel@collabora.com, Andy Yan Subject: [PATCH 4/6] arm64: dts: rockchip: Add DP0 for rk3588 Date: Sun, 23 Feb 2025 19:30:27 +0800 Message-ID: <20250223113036.74252-5-andyshrk@163.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250223113036.74252-1-andyshrk@163.com> References: <20250223113036.74252-1-andyshrk@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: PygvCgBHWqbdBrtnleHpAg--.47651S6 X-Coremail-Antispam: 1Uf129KBjvJXoW7Cry8Kr1kXFW8tFyUGry3urg_yoW8XFW7p3 ZrCrZ3XrW8uF42q39xKr1ktrZYy3Z5CFZYkrn7Gryjkr1Sqr9FkrySgrn3A34DXr47ZwsF vFs3try0kF4qyaUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x07UXYFZUUUUU= X-CM-SenderInfo: 5dqg52xkunqiywtou0bp/xtbBkBD8Xme7AH88NgAFsO Content-Type: text/plain; charset="utf-8" From: Andy Yan The DP0 is compliant with the DisplayPort Specification Version 1.4, and share the USBDP combo PHY0 with USB 3.1 HOST0 controller. Signed-off-by: Andy Yan --- arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boo= t/dts/rockchip/rk3588-base.dtsi index 4989fcd5e592..0aa8026fce95 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -1371,6 +1371,36 @@ i2s9_8ch: i2s@fddfc000 { status =3D "disabled"; }; =20 + dp0: dp@fde50000 { + compatible =3D "rockchip,rk3588-dp"; + reg =3D <0x0 0xfde50000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&cru PCLK_DP0>, <&cru CLK_AUX16M_0>, + <&cru CLK_DP0>, <&cru MCLK_I2S4_8CH_TX>, + <&cru MCLK_SPDIF2_DP0>; + clock-names =3D "apb", "aux", "hdcp", "i2s", "spdif"; + assigned-clocks =3D <&cru CLK_AUX16M_0>; + assigned-clock-rates =3D <16000000>; + resets =3D <&cru SRST_DP0>; + phys =3D <&usbdp_phy0 PHY_TYPE_DP>; + power-domains =3D <&power RK3588_PD_VO0>; + #sound-dai-cells =3D <0>; + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + dp0_in: port@0 { + reg =3D <0>; + }; + + dp0_out: port@1 { + reg =3D <1>; + }; + }; + }; + hdmi0: hdmi@fde80000 { compatible =3D "rockchip,rk3588-dw-hdmi-qp"; reg =3D <0x0 0xfde80000 0x0 0x20000>; --=20 2.34.1