From nobody Wed Dec 17 03:06:30 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5AA652AF04 for ; Sun, 23 Feb 2025 11:02:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740308550; cv=none; b=GEaADeqHb5FV6un63LtYdAFHgUD0xYmSqwAhJn/jbHov/ks3oTQfcNLAl67KH2ZHb/lj3zdGrHYPRwf7UYLdjcX0xEB8pCKiTs9VP9lIxEmOVz655+XwV6D6ZBQ5X7CpmadqMMz2yToKcN8WS2WtQoboq9MYuPylf4gb1HvooPY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740308550; c=relaxed/simple; bh=iDVPebVtBVKbo8sc+q34EtLBvJPNOV2/Slk4+XhkzX8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=tW8VvJR2maVXWKPhHCrv9H0wDxGIiRjBxiyiUY/CEIkKN/q7ITKY4EEcUS677KfQevMkgR3r2GS2TlWeI7jeCg6FuR+MVqz+/uT25FzfKCP0yT0fIReT6V/YLy4BTSWMOQdx9hTRhXkfC9Xhhp2ClP0lLp6beIeQ0Mhz6CDksn8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=UNLIRCnZ; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="UNLIRCnZ" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1740308546; bh=iDVPebVtBVKbo8sc+q34EtLBvJPNOV2/Slk4+XhkzX8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=UNLIRCnZE8hgxhYXKyAQjyTSlO+RfL4o+6ITdDttmQ5fAiS3Zi6S8AWvmEKjLGQJX aMZxziRR/0n0B6HGeoT4odzS5kPNMm561J/iO9WhpcyShAGIuyHBMxQLM+sN1iVDHM /gCbGPuvoh81BZCFwzNANYj4mD9iJvHwysUV0D/tx9uI0pnfgK2SwKRJhcT7L+GvfG VuFhhclQ90amZqoxE2s2vOBqciP/OGr7pDtDvOGqzF4sl2q3cRcm2a5SaG4ODcOzDw UchEeQFWQfCmAbfNVIMiCGE/m76ysdxu/mdrsrU1qqAzS/DUghsFYLdbKr65NP5s30 G74ZoTjf8yIpw== Received: from localhost (unknown [188.27.58.83]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with UTF8SMTPSA id 6105D17E087E; Sun, 23 Feb 2025 12:02:26 +0100 (CET) From: Cristian Ciocaltea Date: Sun, 23 Feb 2025 13:02:08 +0200 Subject: [PATCH v3 1/8] phy: Add HDMI configuration options Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250223-phy-sam-hdptx-bpc-v3-1-66a5c8e68327@collabora.com> References: <20250223-phy-sam-hdptx-bpc-v3-0-66a5c8e68327@collabora.com> In-Reply-To: <20250223-phy-sam-hdptx-bpc-v3-0-66a5c8e68327@collabora.com> To: Vinod Koul , Kishon Vijay Abraham I , Heiko Stuebner Cc: Algea Cao , Sandor Yu , Dmitry Baryshkov , Maxime Ripard , kernel@collabora.com, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.14.2 From: Sandor Yu Allow HDMI PHYs to be configured through the generic functions through a custom structure added to the generic union. The parameters added here are based on HDMI PHY implementation practices. The current set of parameters should cover the potential users. Signed-off-by: Sandor Yu Reviewed-by: Dmitry Baryshkov Reviewed-by: Maxime Ripard Acked-by: Vinod Koul Link: https://lore.kernel.org/r/d1cff6c03ec3732d2244022029245ab2d954d997.17= 34340233.git.Sandor.yu@nxp.com Signed-off-by: Cristian Ciocaltea --- include/linux/phy/phy-hdmi.h | 19 +++++++++++++++++++ include/linux/phy/phy.h | 7 ++++++- 2 files changed, 25 insertions(+), 1 deletion(-) diff --git a/include/linux/phy/phy-hdmi.h b/include/linux/phy/phy-hdmi.h new file mode 100644 index 0000000000000000000000000000000000000000..6a696922bc7f29af63d88646701= b2c0fcee5c885 --- /dev/null +++ b/include/linux/phy/phy-hdmi.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2022,2024 NXP + */ + +#ifndef __PHY_HDMI_H_ +#define __PHY_HDMI_H_ + +/** + * struct phy_configure_opts_hdmi - HDMI configuration set + * @tmds_char_rate: HDMI TMDS Character Rate in Hertz. + * + * This structure is used to represent the configuration state of a HDMI p= hy. + */ +struct phy_configure_opts_hdmi { + unsigned long long tmds_char_rate; +}; + +#endif /* __PHY_HDMI_H_ */ diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h index 03cd5bae92d3f189d739c453fe4c160dd2a5063e..4ac486b101fe4023b8f2a84e907= e65a0ff0a5ede 100644 --- a/include/linux/phy/phy.h +++ b/include/linux/phy/phy.h @@ -17,6 +17,7 @@ #include =20 #include +#include #include #include =20 @@ -42,7 +43,8 @@ enum phy_mode { PHY_MODE_MIPI_DPHY, PHY_MODE_SATA, PHY_MODE_LVDS, - PHY_MODE_DP + PHY_MODE_DP, + PHY_MODE_HDMI, }; =20 enum phy_media { @@ -60,11 +62,14 @@ enum phy_media { * the DisplayPort protocol. * @lvds: Configuration set applicable for phys supporting * the LVDS phy mode. + * @hdmi: Configuration set applicable for phys supporting + * the HDMI phy mode. */ union phy_configure_opts { struct phy_configure_opts_mipi_dphy mipi_dphy; struct phy_configure_opts_dp dp; struct phy_configure_opts_lvds lvds; + struct phy_configure_opts_hdmi hdmi; }; =20 /** --=20 2.48.1 From nobody Wed Dec 17 03:06:30 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 140BF1632DD for ; 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Sun, 23 Feb 2025 12:02:27 +0100 (CET) From: Cristian Ciocaltea Date: Sun, 23 Feb 2025 13:02:09 +0200 Subject: [PATCH v3 2/8] phy: hdmi: Add color depth configuration Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250223-phy-sam-hdptx-bpc-v3-2-66a5c8e68327@collabora.com> References: <20250223-phy-sam-hdptx-bpc-v3-0-66a5c8e68327@collabora.com> In-Reply-To: <20250223-phy-sam-hdptx-bpc-v3-0-66a5c8e68327@collabora.com> To: Vinod Koul , Kishon Vijay Abraham I , Heiko Stuebner Cc: Algea Cao , Sandor Yu , Dmitry Baryshkov , Maxime Ripard , kernel@collabora.com, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.14.2 Extend the HDMI configuration options to allow managing bits per color channel. This is required by some PHY drivers such as rockchip-samsung-hdptx. Signed-off-by: Cristian Ciocaltea --- include/linux/phy/phy-hdmi.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/linux/phy/phy-hdmi.h b/include/linux/phy/phy-hdmi.h index 6a696922bc7f29af63d88646701b2c0fcee5c885..f0ec963c6e84f1b7728acafc824= dff191c6b873d 100644 --- a/include/linux/phy/phy-hdmi.h +++ b/include/linux/phy/phy-hdmi.h @@ -9,11 +9,13 @@ /** * struct phy_configure_opts_hdmi - HDMI configuration set * @tmds_char_rate: HDMI TMDS Character Rate in Hertz. + * @bpc: Bits per color channel. * * This structure is used to represent the configuration state of a HDMI p= hy. */ struct phy_configure_opts_hdmi { unsigned long long tmds_char_rate; + unsigned int bpc; }; =20 #endif /* __PHY_HDMI_H_ */ --=20 2.48.1 From nobody Wed Dec 17 03:06:30 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 071552040AF for ; Sun, 23 Feb 2025 11:02:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740308551; cv=none; b=ihejaN8BK/ZpY7crRN023pWX0yLbbxrNHvhd6CbNG0Pb24YWyJpriLNTsMON+qCPIuF3J7O2ikXrAYj4JGkh/6QZhcB7MAxBTkHrBdJ4EF7qUQVJacJKFML6Ei2YF/vEtGpKobiGQZsn2oLwQagGnyV6ZGlNWh4oMXLIgRrTuZM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740308551; c=relaxed/simple; bh=JVO6B5huh7eGDo+k3A1fG3SKCxGyB11XeWKMxuuZ+rw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ZbhZsm8HUsPzV8xvGEWwl1vcWByAc4qQd2Vph0FWX/S+vi9gkildlcNP08xocOzg2gKNVPCIrw/fYS9QatAxglCYoUZXoRBBE5QWdWxbqiHDEDp8uKO/L5corqtKbLVustTyQiAZzfg1CTYmOrFszpSvgOdJoVwXhQrDo4lJ9MI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=cpDS2JUc; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="cpDS2JUc" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1740308548; bh=JVO6B5huh7eGDo+k3A1fG3SKCxGyB11XeWKMxuuZ+rw=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=cpDS2JUc+MmlgrsPFOokKGjIpsyFpA+XzBTpm+0RU0zK7viHx3hhDXPSVrYJ3evkP 0a10fO3kiwrQGRnOpsY4S9RJnzNHL0fDVqeqLu/Wbg2VAgHJ1+Qu6behCnKhz8+Y7Q +9zlbwaNW3oTNmRGe6rWMIcIGomarbwN0cnN58Hnfqog3oA6gvq4H1b9JAoOEOR9zF VniuSQZHn2FBXIxroj13mOlOzjySWhQDbu9cBT09NqXOrccvWuDtfbUWPk+DIhEmxC W4xelZKRqcBrhzYYwqo3aNl7bfiQdP5tCqPxwxVn/fwJPc5ze2wEN3uszdnkekiJqX FgnjPqhox7ubg== Received: from localhost (unknown [188.27.58.83]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with UTF8SMTPSA id 2A60A17E0DD1; Sun, 23 Feb 2025 12:02:28 +0100 (CET) From: Cristian Ciocaltea Date: Sun, 23 Feb 2025 13:02:10 +0200 Subject: [PATCH v3 3/8] phy: rockchip: samsung-hdptx: Fix clock ratio setup Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250223-phy-sam-hdptx-bpc-v3-3-66a5c8e68327@collabora.com> References: <20250223-phy-sam-hdptx-bpc-v3-0-66a5c8e68327@collabora.com> In-Reply-To: <20250223-phy-sam-hdptx-bpc-v3-0-66a5c8e68327@collabora.com> To: Vinod Koul , Kishon Vijay Abraham I , Heiko Stuebner Cc: Algea Cao , Sandor Yu , Dmitry Baryshkov , Maxime Ripard , kernel@collabora.com, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.14.2 The switch from 1/10 to 1/40 clock ratio must happen when exceeding the 340 MHz rate limit of HDMI 1.4, i.e. when entering the HDMI 2.0 domain, and not before. While at it, introduce a define for this rate limit constant. Fixes: 553be2830c5f ("phy: rockchip: Add Samsung HDMI/eDP Combo PHY driver") Signed-off-by: Cristian Ciocaltea --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/ph= y/rockchip/phy-rockchip-samsung-hdptx.c index f88369864c50e4563834ccbb26f1f9f440e99271..cf2c3a46604cb9d8c26fe5ec834= 6904e0b62848f 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -320,6 +320,7 @@ #define LN3_TX_SER_RATE_SEL_HBR2_MASK BIT(3) #define LN3_TX_SER_RATE_SEL_HBR3_MASK BIT(2) =20 +#define HDMI14_MAX_RATE 340000000 #define HDMI20_MAX_RATE 600000000 =20 enum dp_link_rate { @@ -1072,7 +1073,7 @@ static int rk_hdptx_ropll_tmds_mode_config(struct rk_= hdptx_phy *hdptx, =20 regmap_write(hdptx->regmap, LNTOP_REG(0200), 0x06); =20 - if (rate >=3D 3400000) { + if (rate > HDMI14_MAX_RATE / 100) { /* For 1/40 bitrate clk */ rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lntop_highbr_seq); } else { --=20 2.48.1 From nobody Wed Dec 17 03:06:30 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B3DCA205E0F for ; Sun, 23 Feb 2025 11:02:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740308553; cv=none; b=aYNV1ZD70d9E1yDQwR4eU6khFs5Y/YeQVyT/hfzcfPgtvUifFfQIawquEb547xYpCtN13PQiH8+dLClrU7nth+Zyxs8WL4fY56IBEpbnbVJxDN51DeIB0QIGJsdvZzLVK+zq8PhfiBAc9TxGTR+rgcbBUpJhI3uwDRTDQMUbo/4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740308553; c=relaxed/simple; bh=XP3rwzkTa1mXnGdnUHFUWqLPHJxazgMc4cL1Dqwrxk8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=iuLUbsKpVlzAhS+tVbgROSUgQwRTCgynhFy8CvfU0XHeHETUHZxKbZIwz1NiQFOD7Zy6tQU1yAQsGnjZMdFkIoJsD07LBZzCTW5bvb8LzjNXeZ0SnNF+ntMOd+SfDHGvB6zwmwfZ7NUS9OdcBVDeJOvbhHtpNBQhUeOC+ApnpsU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=dSfwBE8g; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="dSfwBE8g" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1740308549; bh=XP3rwzkTa1mXnGdnUHFUWqLPHJxazgMc4cL1Dqwrxk8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=dSfwBE8gRMyKyiTvnE+U9pT26OuqKF6ct5ERrWfIZIXSEHtZXLFWB8C+J4NYrApdI 5vEcMIrxGyVkIE6Pf1aGJ5svcLAqHwkndamru3xOQooolXdADaMmZIKc+jw6pd47n9 eXOh4qU4Uy5HfrNp5hwJJpy4YFLz2yhkUzLRaBvZBXgeQIpTEXK+YqKGGpn8JXY3t2 Vu3YUwScqES/tnD6MOggcFCmPtDw0ziV0+gjEmOTHkSBrK3JSqHTswmAsDCL5Jgz2W JuVq7yVA4/5ik7Djn5+ZYkeJ5UcwjpdnzT+Jy2UVWiD2ktkhv5AHijHIEAXhFE2Xix aiq3GLNCEJMlg== Received: from localhost (unknown [188.27.58.83]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with UTF8SMTPSA id F3DDF17E0DD5; Sun, 23 Feb 2025 12:02:28 +0100 (CET) From: Cristian Ciocaltea Date: Sun, 23 Feb 2025 13:02:11 +0200 Subject: [PATCH v3 4/8] phy: rockchip: samsung-hdptx: Drop unused lcpll_config Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250223-phy-sam-hdptx-bpc-v3-4-66a5c8e68327@collabora.com> References: <20250223-phy-sam-hdptx-bpc-v3-0-66a5c8e68327@collabora.com> In-Reply-To: <20250223-phy-sam-hdptx-bpc-v3-0-66a5c8e68327@collabora.com> To: Vinod Koul , Kishon Vijay Abraham I , Heiko Stuebner Cc: Algea Cao , Sandor Yu , Dmitry Baryshkov , Maxime Ripard , kernel@collabora.com, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.14.2 This is just a leftover from downstream support for HDMI 2.1. Remove the unused struct for now. Signed-off-by: Cristian Ciocaltea --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 31 -------------------= ---- 1 file changed, 31 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/ph= y/rockchip/phy-rockchip-samsung-hdptx.c index cf2c3a46604cb9d8c26fe5ec8346904e0b62848f..f9b5c96d6c789e435657e224032= d35b5a6950945 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -329,37 +329,6 @@ enum dp_link_rate { DP_BW_HBR2, }; =20 -struct lcpll_config { - u32 bit_rate; - u8 lcvco_mode_en; - u8 pi_en; - u8 clk_en_100m; - u8 pms_mdiv; - u8 pms_mdiv_afc; - u8 pms_pdiv; - u8 pms_refdiv; - u8 pms_sdiv; - u8 pi_cdiv_rstn; - u8 pi_cdiv_sel; - u8 sdm_en; - u8 sdm_rstn; - u8 sdc_frac_en; - u8 sdc_rstn; - u8 sdm_deno; - u8 sdm_num_sign; - u8 sdm_num; - u8 sdc_n; - u8 sdc_n2; - u8 sdc_num; - u8 sdc_deno; - u8 sdc_ndiv_rstn; - u8 ssc_en; - u8 ssc_fm_dev; - u8 ssc_fm_freq; - u8 ssc_clk_div_sel; - u8 cd_tx_ser_rate_sel; -}; - struct ropll_config { u32 bit_rate; u8 pms_mdiv; --=20 2.48.1 From nobody Wed Dec 17 03:06:30 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B3D70205E0E for ; Sun, 23 Feb 2025 11:02:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740308554; cv=none; b=qhK6bOZnp4N8570Lz9yI8fE1MauAIaa/yI99PPenVvtEznN9aNYfykKE/rXtIbho7+QQUECx36MCy9J0k6cHNesQtTAo1EhHBNCSXagQE3DbhkYryxXKh0CJD4zxz/p9SOAQFk8kwsbnW3Pfg8k9i9NWyddtK866vfoCu/tBvGE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740308554; c=relaxed/simple; bh=tpPMKEn4y6Q4gIkPhcILqIjsfH9Lu+r8Lssviy8ylJE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=EdfnG9tebR23DPuZjH1qTRVHz2wI7dms86r6sk0Qq48fjgmQ5abssErsxlUUMqHSyLAisnGRQXVuO0T93+mrOdT4oc+8ZCANBTDgWS5W0qHJcYajrTbphKP0fKpG6cwWXp9HJ/TFVmwQOCpV5+KU0vLTYU5OS6NdbXCBduocqVg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=oHi4R4xd; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="oHi4R4xd" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1740308550; bh=tpPMKEn4y6Q4gIkPhcILqIjsfH9Lu+r8Lssviy8ylJE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=oHi4R4xdGmLKlq+ydb5zw2ytPy4NnojgNAWLi3TI7x5rKuGtEXzmq9KpfDRtlyRKw oIxv2VY943jzsX3ne08xc+w3EDXl2vcLExy3aMKOKm3y1dsiMVY/sKGb4zUPiNzlI0 AoaROsM81rHEVfKqN7wMPeE21gPJb/02sdKTfkIaIau4fQMDJyfoP27dyrtj+ERHHI CRIuwK8ERloLbCygNVdExgD0YyED1YqoCT0CCJpTwac4BfAtwHJ2AfTiYHhLPO8j53 4DqSy32OQ+/SmW8nOvJjlkkhKGSd3OV5Zx0i+A2eizaMmpPHh5rm+RIeMNBQmpc0cQ Ow4taIL3jsMEw== Received: from localhost (unknown [188.27.58.83]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with UTF8SMTPSA id D4EC517E0DD7; Sun, 23 Feb 2025 12:02:29 +0100 (CET) From: Cristian Ciocaltea Date: Sun, 23 Feb 2025 13:02:12 +0200 Subject: [PATCH v3 5/8] phy: rockchip: samsung-hdptx: Setup TMDS char rate via phy_configure_opts_hdmi Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250223-phy-sam-hdptx-bpc-v3-5-66a5c8e68327@collabora.com> References: <20250223-phy-sam-hdptx-bpc-v3-0-66a5c8e68327@collabora.com> In-Reply-To: <20250223-phy-sam-hdptx-bpc-v3-0-66a5c8e68327@collabora.com> To: Vinod Koul , Kishon Vijay Abraham I , Heiko Stuebner Cc: Algea Cao , Sandor Yu , Dmitry Baryshkov , Maxime Ripard , kernel@collabora.com, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.14.2 The current workaround to setup the TMDS character rate relies on the unconventional usage of phy_set_bus_width(). Make use of the recently introduced HDMI PHY configuration API for this purpose. The workaround will be dropped as soon as the switch has been completed on both ends. Signed-off-by: Cristian Ciocaltea --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 37 +++++++++++++++++--= ---- 1 file changed, 27 insertions(+), 10 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/ph= y/rockchip/phy-rockchip-samsung-hdptx.c index f9b5c96d6c789e435657e224032d35b5a6950945..dd91a7272e246b2133112effdb0= 80a847fd15abe 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -402,6 +402,9 @@ struct rk_hdptx_phy { int nr_clks; struct reset_control_bulk_data rsts[RST_MAX]; =20 + /* PHY config opts */ + unsigned long tmds_char_rate; + /* clk provider */ struct clk_hw hw; unsigned long rate; @@ -1413,19 +1416,21 @@ static int rk_hdptx_dp_aux_init(struct rk_hdptx_phy= *hdptx) static int rk_hdptx_phy_power_on(struct phy *phy) { struct rk_hdptx_phy *hdptx =3D phy_get_drvdata(phy); - int bus_width =3D phy_get_bus_width(hdptx->phy); + unsigned int rate =3D hdptx->tmds_char_rate / 100; enum phy_mode mode =3D phy_get_mode(phy); int ret, lane; =20 - /* - * FIXME: Temporary workaround to pass pixel_clk_rate - * from the HDMI bridge driver until phy_configure_opts_hdmi - * becomes available in the PHY API. - */ - unsigned int rate =3D bus_width & 0xfffffff; + if (rate =3D=3D 0) { + /* + * FIXME: Temporary workaround to setup TMDS char rate + * from the RK HDMI bridge driver. + * Will be removed as soon the switch to the HDMI PHY + * configuration API has been completed on both ends. + */ + rate =3D phy_get_bus_width(hdptx->phy) & 0xfffffff; + } =20 - dev_dbg(hdptx->dev, "%s bus_width=3D%x rate=3D%u\n", - __func__, bus_width, rate); + dev_dbg(hdptx->dev, "%s rate=3D%u\n", __func__, rate); =20 ret =3D rk_hdptx_phy_consumer_get(hdptx, rate); if (ret) @@ -1734,8 +1739,10 @@ static int rk_hdptx_phy_configure(struct phy *phy, u= nion phy_configure_opts *opt enum phy_mode mode =3D phy_get_mode(phy); int ret; =20 - if (mode !=3D PHY_MODE_DP) + if (mode !=3D PHY_MODE_DP) { + hdptx->tmds_char_rate =3D opts->hdmi.tmds_char_rate; return 0; + } =20 ret =3D rk_hdptx_phy_verify_config(hdptx, &opts->dp); if (ret) { @@ -1830,6 +1837,16 @@ static int rk_hdptx_phy_clk_set_rate(struct clk_hw *= hw, unsigned long rate, { struct rk_hdptx_phy *hdptx =3D to_rk_hdptx_phy(hw); =20 + /* + * The TMDS char rate set via phy_configure(), if any, has + * precedence over the rate provided via clk_set_rate(). + */ + if (hdptx->tmds_char_rate && hdptx->tmds_char_rate !=3D rate) { + dev_dbg(hdptx->dev, "Replaced clk_set_rate=3D%lu with tmds_char_rate=3D%= lu\n", + rate, hdptx->tmds_char_rate); + rate =3D hdptx->tmds_char_rate; + } + return rk_hdptx_ropll_tmds_cmn_config(hdptx, rate / 100); } =20 --=20 2.48.1 From nobody Wed Dec 17 03:06:30 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A1C112063EB for ; Sun, 23 Feb 2025 11:02:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Sun, 23 Feb 2025 12:02:30 +0100 (CET) From: Cristian Ciocaltea Date: Sun, 23 Feb 2025 13:02:13 +0200 Subject: [PATCH v3 6/8] phy: rockchip: samsung-hdptx: Add high color depth management Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250223-phy-sam-hdptx-bpc-v3-6-66a5c8e68327@collabora.com> References: <20250223-phy-sam-hdptx-bpc-v3-0-66a5c8e68327@collabora.com> In-Reply-To: <20250223-phy-sam-hdptx-bpc-v3-0-66a5c8e68327@collabora.com> To: Vinod Koul , Kishon Vijay Abraham I , Heiko Stuebner Cc: Algea Cao , Sandor Yu , Dmitry Baryshkov , Maxime Ripard , kernel@collabora.com, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.14.2 Add support for 8-bit, 10-bit, 12-bit and 16-bit color depth setup. Signed-off-by: Cristian Ciocaltea --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/ph= y/rockchip/phy-rockchip-samsung-hdptx.c index dd91a7272e246b2133112effdb080a847fd15abe..792ed3d1459f84e735041f55cac= 15941f6f785ef 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -404,6 +404,7 @@ struct rk_hdptx_phy { =20 /* PHY config opts */ unsigned long tmds_char_rate; + unsigned int bpc; =20 /* clk provider */ struct clk_hw hw; @@ -1032,6 +1033,9 @@ static int rk_hdptx_ropll_tmds_cmn_config(struct rk_h= dptx_phy *hdptx, regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_POSTDIV_SEL_MASK, FIELD_PREP(PLL_PCG_POSTDIV_SEL_MASK, cfg->pms_sdiv)); =20 + regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_CLK_SEL_MASK, + FIELD_PREP(PLL_PCG_CLK_SEL_MASK, (hdptx->bpc - 8) >> 1)); + regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_CLK_EN_MASK, FIELD_PREP(PLL_PCG_CLK_EN_MASK, 0x1)); =20 @@ -1430,7 +1434,7 @@ static int rk_hdptx_phy_power_on(struct phy *phy) rate =3D phy_get_bus_width(hdptx->phy) & 0xfffffff; } =20 - dev_dbg(hdptx->dev, "%s rate=3D%u\n", __func__, rate); + dev_dbg(hdptx->dev, "%s rate=3D%u bpc=3D%u\n", __func__, rate, hdptx->bpc= ); =20 ret =3D rk_hdptx_phy_consumer_get(hdptx, rate); if (ret) @@ -1741,6 +1745,19 @@ static int rk_hdptx_phy_configure(struct phy *phy, u= nion phy_configure_opts *opt =20 if (mode !=3D PHY_MODE_DP) { hdptx->tmds_char_rate =3D opts->hdmi.tmds_char_rate; + + switch (opts->hdmi.bpc) { + case 8: + case 10: + case 12: + case 16: + hdptx->bpc =3D opts->hdmi.bpc; + break; + default: + dev_warn(hdptx->dev, "Discarded unsupported bpc: %u\n", + opts->hdmi.bpc); + }; + return 0; } =20 @@ -1922,6 +1939,7 @@ static int rk_hdptx_phy_probe(struct platform_device = *pdev) return -ENOMEM; =20 hdptx->dev =3D dev; + hdptx->bpc =3D 8; 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Sun, 23 Feb 2025 12:02:31 +0100 (CET) From: Cristian Ciocaltea Date: Sun, 23 Feb 2025 13:02:14 +0200 Subject: [PATCH v3 7/8] phy: rockchip: samsung-hdptx: Cleanup internal rate handling Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250223-phy-sam-hdptx-bpc-v3-7-66a5c8e68327@collabora.com> References: <20250223-phy-sam-hdptx-bpc-v3-0-66a5c8e68327@collabora.com> In-Reply-To: <20250223-phy-sam-hdptx-bpc-v3-0-66a5c8e68327@collabora.com> To: Vinod Koul , Kishon Vijay Abraham I , Heiko Stuebner Cc: Algea Cao , Sandor Yu , Dmitry Baryshkov , Maxime Ripard , kernel@collabora.com, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.14.2 Drop the rate parameter from a bunch of internal helpers and, instead, make better use of the newly introduced ->tmds_char_rate driver data. No functional changes intended. Signed-off-by: Cristian Ciocaltea --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 27 ++++++++++++-------= ---- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/ph= y/rockchip/phy-rockchip-samsung-hdptx.c index 792ed3d1459f84e735041f55cac15941f6f785ef..fdac60bb87510002626735e0e9f= 18ad5de9a6642 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -1042,14 +1042,13 @@ static int rk_hdptx_ropll_tmds_cmn_config(struct rk= _hdptx_phy *hdptx, return rk_hdptx_post_enable_pll(hdptx); } =20 -static int rk_hdptx_ropll_tmds_mode_config(struct rk_hdptx_phy *hdptx, - unsigned int rate) +static int rk_hdptx_ropll_tmds_mode_config(struct rk_hdptx_phy *hdptx) { rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_sb_init_seq); =20 regmap_write(hdptx->regmap, LNTOP_REG(0200), 0x06); =20 - if (rate > HDMI14_MAX_RATE / 100) { + if (hdptx->tmds_char_rate > HDMI14_MAX_RATE) { /* For 1/40 bitrate clk */ rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lntop_highbr_seq); } else { @@ -1101,10 +1100,10 @@ static void rk_hdptx_dp_reset(struct rk_hdptx_phy *= hdptx) HDPTX_I_BGR_EN << 16 | FIELD_PREP(HDPTX_I_BGR_EN, 0x0)); } =20 -static int rk_hdptx_phy_consumer_get(struct rk_hdptx_phy *hdptx, - unsigned int rate) +static int rk_hdptx_phy_consumer_get(struct rk_hdptx_phy *hdptx) { enum phy_mode mode =3D phy_get_mode(hdptx->phy); + unsigned long rate; u32 status; int ret; =20 @@ -1121,8 +1120,9 @@ static int rk_hdptx_phy_consumer_get(struct rk_hdptx_= phy *hdptx, if (mode =3D=3D PHY_MODE_DP) { rk_hdptx_dp_reset(hdptx); } else { + rate =3D hdptx->tmds_char_rate ?: hdptx->rate; if (rate) { - ret =3D rk_hdptx_ropll_tmds_cmn_config(hdptx, rate); + ret =3D rk_hdptx_ropll_tmds_cmn_config(hdptx, rate / 100); if (ret) goto dec_usage; } @@ -1420,23 +1420,24 @@ static int rk_hdptx_dp_aux_init(struct rk_hdptx_phy= *hdptx) static int rk_hdptx_phy_power_on(struct phy *phy) { struct rk_hdptx_phy *hdptx =3D phy_get_drvdata(phy); - unsigned int rate =3D hdptx->tmds_char_rate / 100; enum phy_mode mode =3D phy_get_mode(phy); int ret, lane; =20 - if (rate =3D=3D 0) { + if (!hdptx->tmds_char_rate) { /* * FIXME: Temporary workaround to setup TMDS char rate * from the RK HDMI bridge driver. * Will be removed as soon the switch to the HDMI PHY * configuration API has been completed on both ends. */ - rate =3D phy_get_bus_width(hdptx->phy) & 0xfffffff; + hdptx->tmds_char_rate =3D phy_get_bus_width(hdptx->phy) & 0xfffffff; + hdptx->tmds_char_rate *=3D 100; } =20 - dev_dbg(hdptx->dev, "%s rate=3D%u bpc=3D%u\n", __func__, rate, hdptx->bpc= ); + dev_dbg(hdptx->dev, "%s tmds_rate=3D%lu bpc=3D%u\n", __func__, + hdptx->tmds_char_rate, hdptx->bpc); =20 - ret =3D rk_hdptx_phy_consumer_get(hdptx, rate); + ret =3D rk_hdptx_phy_consumer_get(hdptx); if (ret) return ret; =20 @@ -1467,7 +1468,7 @@ static int rk_hdptx_phy_power_on(struct phy *phy) regmap_write(hdptx->grf, GRF_HDPTX_CON0, HDPTX_MODE_SEL << 16 | FIELD_PREP(HDPTX_MODE_SEL, 0x0)); =20 - ret =3D rk_hdptx_ropll_tmds_mode_config(hdptx, rate); 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250223-phy-sam-hdptx-bpc-v3-8-66a5c8e68327@collabora.com> References: <20250223-phy-sam-hdptx-bpc-v3-0-66a5c8e68327@collabora.com> In-Reply-To: <20250223-phy-sam-hdptx-bpc-v3-0-66a5c8e68327@collabora.com> To: Vinod Koul , Kishon Vijay Abraham I , Heiko Stuebner Cc: Algea Cao , Sandor Yu , Dmitry Baryshkov , Maxime Ripard , kernel@collabora.com, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.14.2 The ropll_tmds_cfg table used to identify the configuration params for the supported rates expects the search keys - bit_rate field - to be provided in hHz rather than Hz (1 hHz =3D 100 Hz). This requires multiple conversions between these units being performed at runtime. Improve implementation clarity and efficiency by consistently using the Hz units throughout driver's internal data structures and functions. Signed-off-by: Cristian Ciocaltea --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 61 +++++++++++--------= ---- 1 file changed, 30 insertions(+), 31 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/ph= y/rockchip/phy-rockchip-samsung-hdptx.c index fdac60bb87510002626735e0e9f18ad5de9a6642..991ff4a2e7613dd4bb2c9cf5443= d44794d0eb752 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -330,7 +330,7 @@ enum dp_link_rate { }; =20 struct ropll_config { - u32 bit_rate; + u32 rate; u8 pms_mdiv; u8 pms_mdiv_afc; u8 pms_pdiv; @@ -418,45 +418,45 @@ struct rk_hdptx_phy { }; =20 static const struct ropll_config ropll_tmds_cfg[] =3D { - { 5940000, 124, 124, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, + { 594000000, 124, 124, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 3712500, 155, 155, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, + { 371250000, 155, 155, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 2970000, 124, 124, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, + { 297000000, 124, 124, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 1620000, 135, 135, 1, 1, 3, 1, 1, 0, 1, 1, 1, 1, 4, 0, 3, 5, 5, 0x10, + { 162000000, 135, 135, 1, 1, 3, 1, 1, 0, 1, 1, 1, 1, 4, 0, 3, 5, 5, 0x10, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 1856250, 155, 155, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, + { 185625000, 155, 155, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 1540000, 193, 193, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 193, 1, 32, 2, 1, + { 154000000, 193, 193, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 193, 1, 32, 2, 1, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 1485000, 0x7b, 0x7b, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 4, 0, 3, 5, 5, + { 148500000, 0x7b, 0x7b, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 4, 0, 3, 5, 5, 0x10, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 1462500, 122, 122, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 244, 1, 16, 2, 1, 1, + { 146250000, 122, 122, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 244, 1, 16, 2, 1, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 1190000, 149, 149, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 149, 1, 16, 2, 1, 1, + { 119000000, 149, 149, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 149, 1, 16, 2, 1, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 1065000, 89, 89, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 89, 1, 16, 1, 0, 1, + { 106500000, 89, 89, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 89, 1, 16, 1, 0, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 1080000, 135, 135, 1, 1, 5, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0, + { 108000000, 135, 135, 1, 1, 5, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0, 0x14, 0x18, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 855000, 214, 214, 1, 1, 11, 1, 1, 1, 1, 1, 1, 1, 214, 1, 16, 2, 1, + { 85500000, 214, 214, 1, 1, 11, 1, 1, 1, 1, 1, 1, 1, 214, 1, 16, 2, 1, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 835000, 105, 105, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 42, 1, 16, 1, 0, + { 83500000, 105, 105, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 42, 1, 16, 1, 0, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 928125, 155, 155, 1, 1, 7, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, + { 92812500, 155, 155, 1, 1, 7, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 742500, 124, 124, 1, 1, 7, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, + { 74250000, 124, 124, 1, 1, 7, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 650000, 162, 162, 1, 1, 11, 1, 1, 1, 1, 1, 1, 1, 54, 0, 16, 4, 1, + { 65000000, 162, 162, 1, 1, 11, 1, 1, 1, 1, 1, 1, 1, 54, 0, 16, 4, 1, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 337500, 0x70, 0x70, 1, 1, 0xf, 1, 1, 1, 1, 1, 1, 1, 0x2, 0, 0x01, 5, + { 33750000, 0x70, 0x70, 1, 1, 0xf, 1, 1, 1, 1, 1, 1, 1, 0x2, 0, 0x01, 5, 1, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 400000, 100, 100, 1, 1, 11, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0, + { 40000000, 100, 100, 1, 1, 11, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0, 0x14, 0x18, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 270000, 0x5a, 0x5a, 1, 1, 0xf, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0, + { 27000000, 0x5a, 0x5a, 1, 1, 0xf, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0, 0x14, 0x18, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 251750, 84, 84, 1, 1, 0xf, 1, 1, 1, 1, 1, 1, 1, 168, 1, 16, 4, 1, 1, + { 25175000, 84, 84, 1, 1, 0xf, 1, 1, 1, 1, 1, 1, 1, 168, 1, 16, 4, 1, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, }; =20 @@ -902,10 +902,10 @@ static void rk_hdptx_phy_disable(struct rk_hdptx_phy = *hdptx) regmap_write(hdptx->grf, GRF_HDPTX_CON0, val); } =20 -static bool rk_hdptx_phy_clk_pll_calc(unsigned int data_rate, +static bool rk_hdptx_phy_clk_pll_calc(unsigned long rate, struct ropll_config *cfg) { - const unsigned int fout =3D data_rate / 2, fref =3D 24000; + const unsigned int fout =3D rate / 200, fref =3D 24000; unsigned long k =3D 0, lc, k_sub, lc_sub; unsigned int fvco, sdc; u32 mdiv, sdiv, n =3D 8; @@ -975,16 +975,16 @@ static bool rk_hdptx_phy_clk_pll_calc(unsigned int da= ta_rate, } =20 static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx, - unsigned int rate) + unsigned long rate) { const struct ropll_config *cfg =3D NULL; struct ropll_config rc =3D {0}; int i; =20 - hdptx->rate =3D rate * 100; + hdptx->rate =3D rate; =20 for (i =3D 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++) - if (rate =3D=3D ropll_tmds_cfg[i].bit_rate) { + if (rate =3D=3D ropll_tmds_cfg[i].rate) { cfg =3D &ropll_tmds_cfg[i]; break; } @@ -1122,7 +1122,7 @@ static int rk_hdptx_phy_consumer_get(struct rk_hdptx_= phy *hdptx) } else { rate =3D hdptx->tmds_char_rate ?: hdptx->rate; if (rate) { - ret =3D rk_hdptx_ropll_tmds_cmn_config(hdptx, rate / 100); + ret =3D rk_hdptx_ropll_tmds_cmn_config(hdptx, rate); if (ret) goto dec_usage; } @@ -1833,18 +1833,17 @@ static unsigned long rk_hdptx_phy_clk_recalc_rate(s= truct clk_hw *hw, static long rk_hdptx_phy_clk_round_rate(struct clk_hw *hw, unsigned long r= ate, unsigned long *parent_rate) { - u32 bit_rate =3D rate / 100; int i; =20 if (rate > HDMI20_MAX_RATE) return rate; =20 for (i =3D 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++) - if (bit_rate =3D=3D ropll_tmds_cfg[i].bit_rate) + if (rate =3D=3D ropll_tmds_cfg[i].rate) break; =20 if (i =3D=3D ARRAY_SIZE(ropll_tmds_cfg) && - !rk_hdptx_phy_clk_pll_calc(bit_rate, NULL)) + !rk_hdptx_phy_clk_pll_calc(rate, NULL)) return -EINVAL; =20 return rate; @@ -1865,7 +1864,7 @@ static int rk_hdptx_phy_clk_set_rate(struct clk_hw *h= w, unsigned long rate, rate =3D hdptx->tmds_char_rate; } =20 - return rk_hdptx_ropll_tmds_cmn_config(hdptx, rate / 100); + return rk_hdptx_ropll_tmds_cmn_config(hdptx, rate); } =20 static const struct clk_ops hdptx_phy_clk_ops =3D { --=20 2.48.1