From nobody Tue Feb 10 05:09:48 2026 Received: from szxga06-in.huawei.com (szxga06-in.huawei.com [45.249.212.32]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 45808203703 for ; Sat, 22 Feb 2025 02:58:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.32 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740193112; cv=none; b=BZHqDx9AGfjM+bMICPo7eHuact3cXYmRpeOr9RAHApAKOZ+ggKMbB+VN/TJ4CNL2Y+Ot9IaC/gVmFKwWo+0Gtmbt1kEzol7VSG2MZeQ3/X8a7HC9JSKak/a9E3yiceviR4q5pDBfY7bozmwJbI43LHQbmCPhpPp10+wAWnvRQtI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740193112; c=relaxed/simple; bh=x7N1P+OV11s3oLAIOTBP3vZYLLZyUFgLzBOsimVCVZA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=h5CPrmrdlnjkakbJIUbGeEWVifMaEI5eFbsIe/bg5f+aFp7jRgFYjsGfo4N7hKRIN06xNcOzt7G96RLuGUluts32Efy8G5zIuxF6OD1SXPajaJiZ888WDgGrtuOfA5tx3Ja4xlkcEdBLCrrLE4d48DgTxwZ63bgMwtIuks4bXBM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=45.249.212.32 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.88.163]) by szxga06-in.huawei.com (SkyGuard) with ESMTP id 4Z0BXg34pjznl0b; Sat, 22 Feb 2025 10:58:59 +0800 (CST) Received: from kwepemd500013.china.huawei.com (unknown [7.221.188.12]) by mail.maildlp.com (Postfix) with ESMTPS id 13272180069; Sat, 22 Feb 2025 10:58:28 +0800 (CST) Received: from localhost.huawei.com (10.169.71.169) by kwepemd500013.china.huawei.com (7.221.188.12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.34; Sat, 22 Feb 2025 10:58:26 +0800 From: Yongbang Shi To: , , , , , , , CC: , , , , , , , , Subject: [PATCH v3 drm-dp 7/8] drm/hisilicon/hibmc: Enable this hot plug detect of irq feature Date: Sat, 22 Feb 2025 10:51:00 +0800 Message-ID: <20250222025102.1519798-8-shiyongbang@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20250222025102.1519798-1-shiyongbang@huawei.com> References: <20250222025102.1519798-1-shiyongbang@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To kwepemd500013.china.huawei.com (7.221.188.12) Content-Type: text/plain; charset="utf-8" From: Baihan Li Enable HPD feature and add its isr and event function. Add a drm client dev and realized the hotplug callback in it. Signed-off-by: Baihan Li Signed-off-by: Yongbang Shi --- ChangeLog: v2 -> v3: - remove mdelay(100) hpd function in ISR, suggested by Dmitry Baryshkov. - remove enble_display in ISR, suggested by Dmitry Baryshkov. - change drm_kms_helper_connector_hotplug_event() to drm_connector_helper_hpd_irq_event(), suggested by Dmitry Baryshkov. - move macros to dp_reg.h, suggested by Dmitry Baryshkov. - remove struct irqs, suggested by Dmitry Baryshkov. - split this patch into two parts, suggested by Dmitry Baryshkov. - add a drm client dev to handle HPD event. v1 -> v2: - optimizing the description in commit message, suggested by Dmitry Barys= hkov. - add mdelay(100) comments, suggested by Dmitry Baryshkov. - deleting display enable in hpd event, suggested by Dmitry Baryshkov. --- .../gpu/drm/hisilicon/hibmc/dp/dp_config.h | 1 + drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c | 22 +++++++ drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.h | 6 ++ .../gpu/drm/hisilicon/hibmc/hibmc_drm_dp.c | 61 +++++++++++++++++++ .../gpu/drm/hisilicon/hibmc/hibmc_drm_drv.h | 2 + 5 files changed, 92 insertions(+) diff --git a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_config.h b/drivers/gpu/d= rm/hisilicon/hibmc/dp/dp_config.h index c5feef8dc27d..08f9e1caf7fc 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_config.h +++ b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_config.h @@ -16,5 +16,6 @@ #define HIBMC_DP_SYNC_EN_MASK 0x3 #define HIBMC_DP_LINK_RATE_CAL 27 #define HIBMC_DP_SYNC_DELAY(lanes) ((lanes) =3D=3D 0x2 ? 86 : 46) +#define HIBMC_DP_INT_ENABLE 0xc =20 #endif diff --git a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c b/drivers/gpu/drm/h= isilicon/hibmc/dp/dp_hw.c index a921b98dbf50..b2116395b8dd 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c +++ b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c @@ -182,6 +182,7 @@ int hibmc_dp_hw_init(struct hibmc_dp *dp) /* int init */ writel(0, dp_dev->base + HIBMC_DP_INTR_ENABLE); writel(HIBMC_DP_INT_RST, dp_dev->base + HIBMC_DP_INTR_ORIGINAL_STATUS); + writel(HIBMC_DP_INT_ENABLE, dp_dev->base + HIBMC_DP_INTR_ENABLE); /* rst */ writel(HIBMC_DP_DPTX_RST, dp_dev->base + HIBMC_DP_DPTX_RST_CTRL); /* clock enable */ @@ -190,6 +191,21 @@ int hibmc_dp_hw_init(struct hibmc_dp *dp) return 0; } =20 +void hibmc_dp_hpd_cfg(struct hibmc_dp *dp) +{ + struct hibmc_dp_dev *dp_dev =3D dp->dp_dev; + + hibmc_dp_reg_write_field(dp_dev, HIBMC_DP_AUX_REQ, HIBMC_DP_CFG_AUX_SYNC_= LEN_SEL, 0x0); + hibmc_dp_reg_write_field(dp_dev, HIBMC_DP_AUX_REQ, HIBMC_DP_CFG_AUX_TIMER= _TIMEOUT, 0x1); + hibmc_dp_reg_write_field(dp->dp_dev, HIBMC_DP_AUX_REQ, HIBMC_DP_CFG_AUX_M= IN_PULSE_NUM, 0x9); + writel(HIBMC_DP_HDCP, dp_dev->base + HIBMC_DP_HDCP_CFG); + writel(0, dp_dev->base + HIBMC_DP_INTR_ENABLE); + writel(HIBMC_DP_INT_RST, dp_dev->base + HIBMC_DP_INTR_ORIGINAL_STATUS); + writel(HIBMC_DP_INT_ENABLE, dp_dev->base + HIBMC_DP_INTR_ENABLE); + writel(HIBMC_DP_DPTX_RST, dp_dev->base + HIBMC_DP_DPTX_RST_CTRL); + writel(HIBMC_DP_CLK_EN, dp_dev->base + HIBMC_DP_DPTX_CLK_CTRL); +} + void hibmc_dp_display_en(struct hibmc_dp *dp, bool enable) { struct hibmc_dp_dev *dp_dev =3D dp->dp_dev; @@ -228,6 +244,12 @@ int hibmc_dp_mode_set(struct hibmc_dp *dp, struct drm_= display_mode *mode) return 0; } =20 +void hibmc_dp_reset_link(struct hibmc_dp *dp) +{ + dp->dp_dev->link.status.clock_recovered =3D false; + dp->dp_dev->link.status.channel_equalized =3D false; +} + static const struct hibmc_dp_color_raw g_rgb_raw[] =3D { {CBAR_COLOR_BAR, 0x000, 0x000, 0x000}, {CBAR_WHITE, 0xfff, 0xfff, 0xfff}, diff --git a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.h b/drivers/gpu/drm/h= isilicon/hibmc/dp/dp_hw.h index 83a53dae8012..a55d66d53966 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.h +++ b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.h @@ -11,6 +11,7 @@ #include #include #include +#include =20 struct hibmc_dp_dev; =20 @@ -49,11 +50,16 @@ struct hibmc_dp { void __iomem *mmio; struct drm_dp_aux aux; struct hibmc_dp_cbar_cfg cfg; + u32 irq_status; + u32 hpd_status; + struct drm_client_dev client; }; =20 int hibmc_dp_hw_init(struct hibmc_dp *dp); int hibmc_dp_mode_set(struct hibmc_dp *dp, struct drm_display_mode *mode); void hibmc_dp_display_en(struct hibmc_dp *dp, bool enable); void hibmc_dp_set_cbar(struct hibmc_dp *dp, const struct hibmc_dp_cbar_cfg= *cfg); +void hibmc_dp_reset_link(struct hibmc_dp *dp); +void hibmc_dp_hpd_cfg(struct hibmc_dp *dp); =20 #endif diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_dp.c b/drivers/gpu/d= rm/hisilicon/hibmc/hibmc_drm_dp.c index a7f611e82f73..40a3ebb8ac4b 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_dp.c +++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_dp.c @@ -9,10 +9,13 @@ #include #include #include +#include =20 #include "hibmc_drm_drv.h" #include "dp/dp_hw.h" =20 +#define DP_MASKED_SINK_HPD_PLUG_INT BIT(2) + static int hibmc_dp_connector_get_modes(struct drm_connector *connector) { struct hibmc_dp *dp =3D to_hibmc_dp(connector); @@ -98,6 +101,58 @@ static const struct drm_encoder_helper_funcs hibmc_dp_e= ncoder_helper_funcs =3D { .atomic_disable =3D hibmc_dp_encoder_disable, }; =20 +irqreturn_t hibmc_dp_hpd_isr(int irq, void *arg) +{ + struct drm_device *dev =3D (struct drm_device *)arg; + struct hibmc_drm_private *priv =3D to_hibmc_drm_private(dev); + int idx; + + if (!drm_dev_enter(dev, &idx)) + return -ENODEV; + + if (priv->dp.irq_status & DP_MASKED_SINK_HPD_PLUG_INT) { + drm_dbg_dp(&priv->dev, "HPD IN isr occur!\n"); + priv->dp.hpd_status =3D 1; + } else { + drm_dbg_dp(&priv->dev, "HPD OUT isr occur!\n"); + priv->dp.hpd_status =3D 0; + } + + if (dev->registered) + drm_connector_helper_hpd_irq_event(&priv->dp.connector); + + drm_dev_exit(idx); + + return IRQ_HANDLED; +} + +static int hibmc_dp_hpd_event(struct drm_client_dev *client) +{ + struct hibmc_dp *dp =3D container_of(client, struct hibmc_dp, client); + struct hibmc_drm_private *priv =3D to_hibmc_drm_private(dp->drm_dev); + struct drm_display_mode *mode =3D &priv->crtc.state->adjusted_mode; + int ret; + + if (dp->hpd_status) { + hibmc_dp_hpd_cfg(&priv->dp); + ret =3D hibmc_dp_prepare(dp, mode); + if (ret) + return ret; + + hibmc_dp_display_en(dp, true); + } else { + hibmc_dp_display_en(dp, false); + hibmc_dp_reset_link(&priv->dp); + } + + return 0; +} + +static const struct drm_client_funcs hibmc_dp_client_funcs =3D { + .hotplug =3D hibmc_dp_hpd_event, + .unregister =3D drm_client_release, +}; + int hibmc_dp_init(struct hibmc_drm_private *priv) { struct drm_device *dev =3D &priv->dev; @@ -138,5 +193,11 @@ int hibmc_dp_init(struct hibmc_drm_private *priv) =20 drm_connector_attach_encoder(connector, encoder); =20 + ret =3D drm_client_init(dev, &dp->client, "hibmc-DP-HPD", &hibmc_dp_clien= t_funcs); + if (ret) + return ret; + + drm_client_register(&dp->client); + return 0; } diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.h b/drivers/gpu/= drm/hisilicon/hibmc/hibmc_drm_drv.h index bc89e4b9f4e3..daed1330b961 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.h +++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.h @@ -71,4 +71,6 @@ int hibmc_dp_init(struct hibmc_drm_private *priv); =20 void hibmc_debugfs_init(struct drm_connector *connector, struct dentry *ro= ot); =20 +irqreturn_t hibmc_dp_hpd_isr(int irq, void *arg); + #endif --=20 2.33.0