From nobody Thu Dec 18 00:50:24 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id E41F5253F3E; Fri, 21 Feb 2025 18:04:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740161060; cv=none; b=PvDnna0YscP5eX9jsNZy53ECsX0W7PPNlgza3i7TuLo1sJ2jxdG8SY2OH+5WK+d3Etj8XTE2vXpDxC+JNeUBGMT2C960XZuteyMHfr600u4hNEFRPgUzqZ05fHC8qlk7MEImwpTMWQu43RFUvDIDigYS5hNP+B+VqJsucts+dyg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740161060; c=relaxed/simple; bh=w3+kiSyJXOb0pNy8ocDnDQd7Cizm2vu6drwZHcAQ1+w=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=U8vHRH06N041EaAGgHAnsPSyuomzH6+p+c9brU+7lEvkkv24ls8jvlznWM4h3n7vrUc+UHQ6jiHjfsagHbGJTO2ODO4zywIW3/LbLecPIVA5kXTRXIpEASNqhWbnlV97XPTXwDQ7tzjEML8JjNWRlKPBcnr+ABp/xoVb/y1acto= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 371F2169C; Fri, 21 Feb 2025 10:04:36 -0800 (PST) Received: from e119884-lin.cambridge.arm.com (e119884-lin.cambridge.arm.com [10.1.196.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6147C3F59E; Fri, 21 Feb 2025 10:04:16 -0800 (PST) From: Vincenzo Frascino To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Vincenzo Frascino , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Russell King , Will Deacon , Mark Rutland , Jessica Clarke Subject: [PATCH v7 09/10] arm64: dts: morello: Add support for fvp dts Date: Fri, 21 Feb 2025 18:03:48 +0000 Message-ID: <20250221180349.1413089-10-vincenzo.frascino@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250221180349.1413089-1-vincenzo.frascino@arm.com> References: <20250221180349.1413089-1-vincenzo.frascino@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Morello architecture is an experimental extension to Armv8.2-A, which extends the AArch64 state with the principles proposed in version 7 of the Capability Hardware Enhanced RISC Instructions (CHERI) ISA. Introduce Morello fvp dts. Signed-off-by: Vincenzo Frascino Reviewed-by: Linus Walleij --- arch/arm64/boot/dts/arm/Makefile | 2 +- arch/arm64/boot/dts/arm/morello-fvp.dts | 77 +++++++++++++++++++++++++ 2 files changed, 78 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/arm/morello-fvp.dts diff --git a/arch/arm64/boot/dts/arm/Makefile b/arch/arm64/boot/dts/arm/Mak= efile index 869667bef7c0..f30ee045dc95 100644 --- a/arch/arm64/boot/dts/arm/Makefile +++ b/arch/arm64/boot/dts/arm/Makefile @@ -7,4 +7,4 @@ dtb-$(CONFIG_ARCH_VEXPRESS) +=3D rtsm_ve-aemv8a.dtb dtb-$(CONFIG_ARCH_VEXPRESS) +=3D vexpress-v2f-1xv7-ca53x2.dtb dtb-$(CONFIG_ARCH_VEXPRESS) +=3D fvp-base-revc.dtb dtb-$(CONFIG_ARCH_VEXPRESS) +=3D corstone1000-fvp.dtb corstone1000-mps3.dtb -dtb-$(CONFIG_ARCH_VEXPRESS) +=3D morello-sdp.dtb +dtb-$(CONFIG_ARCH_VEXPRESS) +=3D morello-sdp.dtb morello-fvp.dtb diff --git a/arch/arm64/boot/dts/arm/morello-fvp.dts b/arch/arm64/boot/dts/= arm/morello-fvp.dts new file mode 100644 index 000000000000..2072c0b72325 --- /dev/null +++ b/arch/arm64/boot/dts/arm/morello-fvp.dts @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (c) 2021-2024, Arm Limited. All rights reserved. + */ + +/dts-v1/; +#include "morello.dtsi" + +/ { + model =3D "Arm Morello Fixed Virtual Platform"; + compatible =3D "arm,morello-fvp", "arm,morello"; + + aliases { + serial0 =3D &uart0; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + bp_refclock24mhz: clock-24000000 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <24000000>; + clock-output-names =3D "bp:clock24mhz"; + }; + + block_0: virtio_block@1c170000 { + compatible =3D "virtio,mmio"; + reg =3D <0x0 0x1c170000 0x0 0x200>; + interrupts =3D ; + }; + + net_0: virtio_net@1c180000 { + compatible =3D "virtio,mmio"; + reg =3D <0x0 0x1c180000 0x0 0x200>; + interrupts =3D ; + }; + + rng_0: virtio_rng@1c190000 { + compatible =3D "virtio,mmio"; + reg =3D <0x0 0x1c190000 0x0 0x200>; + interrupts =3D ; + }; + + p9_0: virtio_p9@1c1a0000 { + compatible =3D "virtio,mmio"; + reg =3D <0x0 0x1c1a0000 0x0 0x200>; + interrupts =3D ; + }; + + kmi_0: kmi@1c150000 { + compatible =3D "arm,pl050", "arm,primecell"; + reg =3D <0x0 0x1c150000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&bp_refclock24mhz>, <&bp_refclock24mhz>; + clock-names =3D "KMIREFCLK", "apb_pclk"; + }; + + kmi_1: kmi@1c160000 { + compatible =3D "arm,pl050", "arm,primecell"; + reg =3D <0x0 0x1c160000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&bp_refclock24mhz>, <&bp_refclock24mhz>; + clock-names =3D "KMIREFCLK", "apb_pclk"; + }; + + eth_0: ethernet@1d100000 { + compatible =3D "smsc,lan91c111"; + reg =3D <0x0 0x1d100000 0x0 0x10000>; + interrupts =3D ; + }; +}; + +&uart0 { + status =3D "okay"; +}; --=20 2.43.0