From nobody Tue Dec 16 19:33:07 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 7925F2512F3; Fri, 21 Feb 2025 18:03:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740161041; cv=none; b=oWEC8YMqnEG/63GYkokiRvosIt+Z8UmqAkM2D3QxfIsMetAWsCdXhik006a+yMhe6nlAJVHn6QjrA0C46lUs6GDsmkzUAu+MDW4VHrVIRu2VfAFZ6XeCoillBZpGm+vtSMbTF2+cIGwrY+iOW4sncKSInAAYRO065TBn1n04Etc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740161041; c=relaxed/simple; bh=VPMbdL1Vw7lgqdn6uC7hmtkVo6hwUFSfKhhgxZm5IJI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=r0Wj8c4LaLgU0FRES5Vkz4J4/XaozHz6cYgHFR56PxqNkjZTDb1GYwjfPy08HxU4CTWJuFLObJiFTL6q01TYO5MbPbVXJUzfds/CQ/rPE3S5x4quu+XXsZ33DxrPNU48LAsTWWede4y9qDfNk508lU4ppCZGO6PbEZC/bfRMhtg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6567B1CC4; Fri, 21 Feb 2025 10:04:16 -0800 (PST) Received: from e119884-lin.cambridge.arm.com (e119884-lin.cambridge.arm.com [10.1.196.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 90B463F59E; Fri, 21 Feb 2025 10:03:56 -0800 (PST) From: Vincenzo Frascino To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Vincenzo Frascino , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Russell King , Will Deacon , Mark Rutland , Jessica Clarke Subject: [PATCH v7 01/10] arm64: Kconfig: Update description for CONFIG_ARCH_VEXPRESS Date: Fri, 21 Feb 2025 18:03:40 +0000 Message-ID: <20250221180349.1413089-2-vincenzo.frascino@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250221180349.1413089-1-vincenzo.frascino@arm.com> References: <20250221180349.1413089-1-vincenzo.frascino@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update the description and contextually the help text of CONFIG_ARCH_VEXPRESS to reflect the inclusion of all ARM Ltd Platforms. Signed-off-by: Vincenzo Frascino Reviewed-by: Liviu Dudau --- arch/arm64/Kconfig.platforms | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 02f9248f7c84..c468c23b2bba 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -374,13 +374,12 @@ config ARCH_UNIPHIER This enables support for Socionext UniPhier SoC family. =20 config ARCH_VEXPRESS - bool "ARMv8 software model (Versatile Express)" + bool "ARM Ltd Platforms" select GPIOLIB select PM select PM_GENERIC_DOMAINS help - This enables support for the ARMv8 software model (Versatile - Express). + This enables support for the ARM Ltd Platforms. =20 config ARCH_VISCONTI bool "Toshiba Visconti SoC Family" --=20 2.43.0 From nobody Tue Dec 16 19:33:07 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id E33C32528F5; Fri, 21 Feb 2025 18:04:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740161043; cv=none; b=MG5FatdLOSwhZWeGcq1fLNGRLhpUZ5mla5qzCTMGcaLZBvfuDi6WtB2qIbZ5sLmpFyRi0wZOsP69e8zK2tWGla7l2TjUVxZRF8tXDXNDvKQV1ubN/g0GkLt9PuADWfp63YeFh7Csi9qDp9O65JW5QnI/AcoVO+CpaDexioM8yZk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740161043; c=relaxed/simple; bh=qkj/B6w4AoL9CIf7WbDkzuqMAMet4sgOBNo5Lp+Ci1U=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Fz/1YbHhyBkpPh9RMx+YAMAar2CUmAxf7lNXljZS+VTflLXRahiNc7mzu0YgJnighJ1+nMgFSrnj7/uA7ND3Kt2VRplu/8gSioO8ojeh3eCWpbCsQi8qoS57rkTKjfgnuy11MAl2KIPsEelhvn2brfLyNU7ODrU2jT+kJiSl+HE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id ECBD2169C; Fri, 21 Feb 2025 10:04:18 -0800 (PST) Received: from e119884-lin.cambridge.arm.com (e119884-lin.cambridge.arm.com [10.1.196.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 052803F59E; Fri, 21 Feb 2025 10:03:58 -0800 (PST) From: Vincenzo Frascino To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Vincenzo Frascino , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Russell King , Will Deacon , Mark Rutland , Jessica Clarke , Krzysztof Kozlowski Subject: [PATCH v7 02/10] dt-bindings: arm: Add Morello compatibility Date: Fri, 21 Feb 2025 18:03:41 +0000 Message-ID: <20250221180349.1413089-3-vincenzo.frascino@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250221180349.1413089-1-vincenzo.frascino@arm.com> References: <20250221180349.1413089-1-vincenzo.frascino@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add compatibility to Arm Morello System Development Platform. Note: Morello is at the same time the name of an Architecture [1], an SoC [2] and a Board [2]. To distinguish in between Architecture/SoC and Board we refer to the first as arm,morello and to the second as arm,morello-sdp. [1] https://developer.arm.com/Architectures/Morello [2] https://www.morello-project.org/ Acked-by: Krzysztof Kozlowski Signed-off-by: Vincenzo Frascino Reviewed-by: Linus Walleij --- .../devicetree/bindings/arm/arm,morello.yaml | 33 +++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/arm,morello.yaml diff --git a/Documentation/devicetree/bindings/arm/arm,morello.yaml b/Docum= entation/devicetree/bindings/arm/arm,morello.yaml new file mode 100644 index 000000000000..b4cfa8d048c4 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,morello.yaml @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,morello.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM Morello Platforms + +maintainers: + - Vincenzo Frascino + +description: |+ + The Morello architecture is an experimental extension to Armv8.2-A, + which extends the AArch64 state with the principles proposed in + version 7 of the Capability Hardware Enhanced RISC Instructions + (CHERI) ISA. + + ARM's Morello Platforms are built as a research project to explore + capability architectures based on arm. + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: Arm Morello System Development Platform + items: + - const: arm,morello-sdp + - const: arm,morello + +additionalProperties: true + +... --=20 2.43.0 From nobody Tue Dec 16 19:33:07 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 4B19F25332D; Fri, 21 Feb 2025 18:04:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740161045; cv=none; b=Ql52qyBp/PBD17Qfg6OYOe3iG8d2OfaXn63uoA45BEbJ1AjuIX0ds4cLWCZHEOw9xzDmO0tZc872yoEyUXEtq1ujIcVS9K2y2FiNskE4lWekAeEvtSTb2A5ChE+im3jo2mAsjH5h7qxmpeZRobXht/gSpt4KSipVOwSRJwIuwig= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740161045; c=relaxed/simple; bh=aeOJd1pNcikYlgrHklgsL8hYd4QhP4EpxZRIKOihJcE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=rKGi+yo3R7Pu9TywskXtF2lFslxbcaXWbOjNQf2eSaKAojtnUHsMPLY0ak2YK0yze2P+XrBZm6gtfH0znL0GoIooQQFTEQWGZMacWx7w/NtXAIMER5BZEe0IT/f/38gfFZBpI/Oi1sDDHMsp1CPRf/2wvG+mrq7zUsYDQOCnp1k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 607D61CC4; Fri, 21 Feb 2025 10:04:21 -0800 (PST) Received: from e119884-lin.cambridge.arm.com (e119884-lin.cambridge.arm.com [10.1.196.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8CB503F59E; Fri, 21 Feb 2025 10:04:01 -0800 (PST) From: Vincenzo Frascino To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Vincenzo Frascino , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Russell King , Will Deacon , Mark Rutland , Jessica Clarke Subject: [PATCH v7 03/10] dt-bindings: arm: Add Morello fvp compatibility Date: Fri, 21 Feb 2025 18:03:42 +0000 Message-ID: <20250221180349.1413089-4-vincenzo.frascino@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250221180349.1413089-1-vincenzo.frascino@arm.com> References: <20250221180349.1413089-1-vincenzo.frascino@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add compatibility to Arm Morello Fixed Virtual Platform. Signed-off-by: Vincenzo Frascino Reviewed-by: Linus Walleij Reviewed-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/arm/arm,morello.yaml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/arm,morello.yaml b/Docum= entation/devicetree/bindings/arm/arm,morello.yaml index b4cfa8d048c4..e843b97fa485 100644 --- a/Documentation/devicetree/bindings/arm/arm,morello.yaml +++ b/Documentation/devicetree/bindings/arm/arm,morello.yaml @@ -23,9 +23,11 @@ properties: const: '/' compatible: oneOf: - - description: Arm Morello System Development Platform + - description: Arm Morello System Platforms items: - - const: arm,morello-sdp + - enum: + - arm,morello-sdp + - arm,morello-fvp - const: arm,morello =20 additionalProperties: true --=20 2.43.0 From nobody Tue Dec 16 19:33:07 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id E0B58253352; Fri, 21 Feb 2025 18:04:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740161048; cv=none; b=BL/5V1DBuc7huZHG99KADlBADo85KaCfRu+LT5r//5U2AyMnPglap7M56pXvd1bQ0x6UrT8grdaK3iPhbhKP16USUQoXw0oGBVbn/bE7Rm9sKcmP9nsKzhT52Z7nO1rMfpks0wc8GxvrQgHLNiUNy0sLSjQM6lUa0XN+efgzX3s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740161048; c=relaxed/simple; bh=9rofk5/Vnma3elUi1VHrh8uQrwo12MtZp2jMCxVJyu8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=uagPnxIrRJAlb0XTlDGDvUNrrhDitrpqzc2PnwifyzV1LYaL4r54W/F220tfibbqvvzaah9f9Y6gwsBK/h5pglQ8uFZeX0rBuhYonoGBLrhkT8DphB9ODPc2nkWVhx46EdAHvZriWqMqQtP53mQIt9huPbEKNL2juDSpT/wi2Ps= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E80B7169C; Fri, 21 Feb 2025 10:04:23 -0800 (PST) Received: from e119884-lin.cambridge.arm.com (e119884-lin.cambridge.arm.com [10.1.196.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id F41C23F59E; Fri, 21 Feb 2025 10:04:03 -0800 (PST) From: Vincenzo Frascino To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Vincenzo Frascino , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Russell King , Will Deacon , Mark Rutland , Jessica Clarke , Krzysztof Kozlowski Subject: [PATCH v7 04/10] dt-bindings: arm: Add Rainier compatibility Date: Fri, 21 Feb 2025 18:03:43 +0000 Message-ID: <20250221180349.1413089-5-vincenzo.frascino@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250221180349.1413089-1-vincenzo.frascino@arm.com> References: <20250221180349.1413089-1-vincenzo.frascino@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Arm Morello System Development Platform uses Rainier CPUs. Add compatibility to Rainier. Acked-by: Krzysztof Kozlowski Signed-off-by: Vincenzo Frascino --- Documentation/devicetree/bindings/arm/cpus.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentatio= n/devicetree/bindings/arm/cpus.yaml index 73dd73d2d4fa..2e666b2a4dcd 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -177,6 +177,7 @@ properties: - arm,neoverse-v2 - arm,neoverse-v3 - arm,neoverse-v3ae + - arm,rainier - brcm,brahma-b15 - brcm,brahma-b53 - brcm,vulcan --=20 2.43.0 From nobody Tue Dec 16 19:33:07 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 72CB7253B42; Fri, 21 Feb 2025 18:04:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740161050; cv=none; b=FEDlA93fNUkg++vnTqVYNq91PQMG+FscrtgOCAeQwCWOw2CSby3oJdUxzPpZ0O0tKwohKqAB2OSMcCDRfC7s7Z3Bk6IAzbGqqaVdmluw8ktq7MM+pwspwsS185+8Y7toEtpDgNzy3esgTA7E6Yy6EOnXsbKqWkdoLNbT/CS2VOI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740161050; c=relaxed/simple; bh=xLPhUv/7InGqVeGLHEvlqDXHIMCnOAzOpCoDyWSS4Ug=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=gE9JGIwRl/ZxNI1aY80PfuM1bGR785DlsNdjRIq9EctxbRo1UyBKWPe+9FoOYK2kyPJsSmbem0bzw6ecQYSMZgDfwp8YmnIxpowBt5+T6ikdFcYXTus2fchlN9UyEZOGQ3BEd6KkIplnZo+ykhhUkHIEK6e75cLuEHpvjLrNbZk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 817811CC4; Fri, 21 Feb 2025 10:04:26 -0800 (PST) Received: from e119884-lin.cambridge.arm.com (e119884-lin.cambridge.arm.com [10.1.196.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 87C3D3F59E; Fri, 21 Feb 2025 10:04:06 -0800 (PST) From: Vincenzo Frascino To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Vincenzo Frascino , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Russell King , Will Deacon , Mark Rutland , Jessica Clarke , Krzysztof Kozlowski Subject: [PATCH v7 05/10] dt-bindings: arm-pmu: Add support for ARM Rainier PMU Date: Fri, 21 Feb 2025 18:03:44 +0000 Message-ID: <20250221180349.1413089-6-vincenzo.frascino@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250221180349.1413089-1-vincenzo.frascino@arm.com> References: <20250221180349.1413089-1-vincenzo.frascino@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for the ARM Rainier CPU core PMU. Acked-by: Krzysztof Kozlowski Signed-off-by: Vincenzo Frascino Reviewed-by: Linus Walleij --- Documentation/devicetree/bindings/arm/pmu.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/pmu.yaml b/Documentation= /devicetree/bindings/arm/pmu.yaml index a148ff54f2b8..295963a3cae7 100644 --- a/Documentation/devicetree/bindings/arm/pmu.yaml +++ b/Documentation/devicetree/bindings/arm/pmu.yaml @@ -67,6 +67,7 @@ properties: - arm,neoverse-v2-pmu - arm,neoverse-v3-pmu - arm,neoverse-v3ae-pmu + - arm,rainier-pmu - brcm,vulcan-pmu - cavium,thunder-pmu - nvidia,denver-pmu --=20 2.43.0 From nobody Tue Dec 16 19:33:07 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D1501253B7D; Fri, 21 Feb 2025 18:04:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740161053; cv=none; b=g8wW/BsNGTmUfec9OfzIdRy98Pu2Sen2iwVEjAx3aU7AVr1SPCVUk083e8OC5ppxmkoamHgvFz+ROcReC5Cfz5aj/mev8UvitBw6xr4bfu9wq+413DocQ4GKnKhXPA64CeWIdCOSBrbyYZXkjLOop3SoPKU6FsvynoQqhlKOf5s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740161053; c=relaxed/simple; bh=Gkzd+0+eoZlvdbPR8c1GU4RoDNPv/6Zi7aLQNFled24=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Xj0pMNuMgwx1CJn3eqYQy9UGXrDnmCzfS2IDVs9vMyMIqki3tZLgAZrRu55IStboOF8YqfUbAh5wbJ1tTdUiasCG+uhI2AS79HnsZvBMa0Wcc2PKi1MWXTG+BqWCo8dN8GoNbds0z4I6CDB7oTn9xTuHRBJlqiMynigfTHeZqMs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E37EC169C; Fri, 21 Feb 2025 10:04:28 -0800 (PST) Received: from e119884-lin.cambridge.arm.com (e119884-lin.cambridge.arm.com [10.1.196.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1A6A63F59E; Fri, 21 Feb 2025 10:04:08 -0800 (PST) From: Vincenzo Frascino To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Vincenzo Frascino , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Russell King , Will Deacon , Mark Rutland , Jessica Clarke Subject: [PATCH v7 06/10] perf: arm_pmuv3: Add support for ARM Rainier PMU Date: Fri, 21 Feb 2025 18:03:45 +0000 Message-ID: <20250221180349.1413089-7-vincenzo.frascino@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250221180349.1413089-1-vincenzo.frascino@arm.com> References: <20250221180349.1413089-1-vincenzo.frascino@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for the ARM Rainier CPU core PMU. Signed-off-by: Vincenzo Frascino --- drivers/perf/arm_pmuv3.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/perf/arm_pmuv3.c b/drivers/perf/arm_pmuv3.c index 0e360feb3432..3785522a08e7 100644 --- a/drivers/perf/arm_pmuv3.c +++ b/drivers/perf/arm_pmuv3.c @@ -1369,6 +1369,7 @@ PMUV3_INIT_SIMPLE(armv8_neoverse_v1) PMUV3_INIT_SIMPLE(armv8_neoverse_v2) PMUV3_INIT_SIMPLE(armv8_neoverse_v3) PMUV3_INIT_SIMPLE(armv8_neoverse_v3ae) +PMUV3_INIT_SIMPLE(armv8_rainier) =20 PMUV3_INIT_SIMPLE(armv8_nvidia_carmel) PMUV3_INIT_SIMPLE(armv8_nvidia_denver) @@ -1416,6 +1417,7 @@ static const struct of_device_id armv8_pmu_of_device_= ids[] =3D { {.compatible =3D "arm,neoverse-v2-pmu", .data =3D armv8_neoverse_v2_pmu_i= nit}, {.compatible =3D "arm,neoverse-v3-pmu", .data =3D armv8_neoverse_v3_pmu_i= nit}, {.compatible =3D "arm,neoverse-v3ae-pmu", .data =3D armv8_neoverse_v3ae_p= mu_init}, + {.compatible =3D "arm,rainier-pmu", .data =3D armv8_rainier_pmu_init}, {.compatible =3D "cavium,thunder-pmu", .data =3D armv8_cavium_thunder_pmu= _init}, {.compatible =3D "brcm,vulcan-pmu", .data =3D armv8_brcm_vulcan_pmu_init}, {.compatible =3D "nvidia,carmel-pmu", .data =3D armv8_nvidia_carmel_pmu_i= nit}, --=20 2.43.0 From nobody Tue Dec 16 19:33:07 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 62D272512ED; Fri, 21 Feb 2025 18:04:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740161056; cv=none; b=NV7AO79+BLXJUmvCKNMJf4hCnrxPZ4PbFnMPzIs2WW4L/FMLqe2SRvU5DtoVly32EOXQj+H5tCiStFQ9H1VmoB9mNuZC4pi0srZVitbpHCLTZiB2s2Ub4pW0ltSdP5T7iXTEQIXuMRoQ/gTsCbM2dMnRaM4WXkCPj7x2QlhWctc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740161056; c=relaxed/simple; bh=wSGkRHix23Rg/RD0EtFj6NYDI+obYIqaysIit5V1FIw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=nbuLasRDbpNVNUaaiHYfPyJXrUgP2b2byvScaNriTAby1rZUBDBzN/HFh7kUD+HFHLFpL8Oz9M8JH5Fd7b6A3fYUJsNgQEhPQtZIP9+ELnozmbADyd4oB6mI/s3+oDMQ1fiD6ow6i8uUJyqy4+/fhbYKD7PbPSv9ZfZEmU0KYFM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 59231169C; Fri, 21 Feb 2025 10:04:31 -0800 (PST) Received: from e119884-lin.cambridge.arm.com (e119884-lin.cambridge.arm.com [10.1.196.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 839023F59E; Fri, 21 Feb 2025 10:04:11 -0800 (PST) From: Vincenzo Frascino To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Vincenzo Frascino , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Russell King , Will Deacon , Mark Rutland , Jessica Clarke Subject: [PATCH v7 07/10] arm64: dts: morello: Add support for common functionalities Date: Fri, 21 Feb 2025 18:03:46 +0000 Message-ID: <20250221180349.1413089-8-vincenzo.frascino@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250221180349.1413089-1-vincenzo.frascino@arm.com> References: <20250221180349.1413089-1-vincenzo.frascino@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Morello architecture is an experimental extension to Armv8.2-A, which extends the AArch64 state with the principles proposed in version 7 of the Capability Hardware Enhanced RISC Instructions (CHERI) ISA. The Morello Platform (soc) and the Fixed Virtual Platfom (fvp) share some functionalities that have conveniently been included in morello.dtsi to avoid duplication. Introduce morello.dtsi. Note: Morello fvp will be introduced with a future patch series. Signed-off-by: Vincenzo Frascino Reviewed-by: Linus Walleij --- arch/arm64/boot/dts/arm/morello.dtsi | 323 +++++++++++++++++++++++++++ 1 file changed, 323 insertions(+) create mode 100644 arch/arm64/boot/dts/arm/morello.dtsi diff --git a/arch/arm64/boot/dts/arm/morello.dtsi b/arch/arm64/boot/dts/arm= /morello.dtsi new file mode 100644 index 000000000000..e35e5e482720 --- /dev/null +++ b/arch/arm64/boot/dts/arm/morello.dtsi @@ -0,0 +1,323 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (c) 2020-2024, Arm Limited. All rights reserved. + */ + +#include + +/ { + interrupt-parent =3D <&gic>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + + soc_refclk50mhz: clock-50000000 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <50000000>; + clock-output-names =3D "apb_pclk"; + }; + + soc_refclk85mhz: clock-85000000 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <85000000>; + clock-output-names =3D "iofpga:aclk"; + }; + + cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + compatible =3D "arm,rainier"; + reg =3D <0x0 0x0>; + device_type =3D "cpu"; + enable-method =3D "psci"; + /* 4 ways set associative */ + i-cache-size =3D <0x10000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <512>; + d-cache-size =3D <0x10000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_0>; + clocks =3D <&scmi_dvfs 0>; + + l2_0: l2-cache-0 { + compatible =3D "cache"; + cache-level =3D <2>; + /* 8 ways set associative */ + cache-size =3D <0x100000>; + cache-line-size =3D <64>; + cache-sets =3D <2048>; + cache-unified; + next-level-cache =3D <&l3_0>; + + l3_0: l3-cache { + compatible =3D "cache"; + cache-level =3D <3>; + cache-size =3D <0x100000>; + cache-unified; + }; + }; + }; + + cpu1: cpu@100 { + compatible =3D "arm,rainier"; + reg =3D <0x0 0x100>; + device_type =3D "cpu"; + enable-method =3D "psci"; + /* 4 ways set associative */ + i-cache-size =3D <0x10000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <512>; + d-cache-size =3D <0x10000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_1>; + clocks =3D <&scmi_dvfs 0>; + + l2_1: l2-cache-1 { + compatible =3D "cache"; + cache-level =3D <2>; + /* 8 ways set associative */ + cache-size =3D <0x100000>; + cache-line-size =3D <64>; + cache-sets =3D <2048>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu2: cpu@10000 { + compatible =3D "arm,rainier"; + reg =3D <0x0 0x10000>; + device_type =3D "cpu"; + enable-method =3D "psci"; + /* 4 ways set associative */ + i-cache-size =3D <0x10000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <512>; + d-cache-size =3D <0x10000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_2>; + clocks =3D <&scmi_dvfs 1>; + + l2_2: l2-cache-2 { + compatible =3D "cache"; + cache-level =3D <2>; + /* 8 ways set associative */ + cache-size =3D <0x100000>; + cache-line-size =3D <64>; + cache-sets =3D <2048>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu3: cpu@10100 { + compatible =3D "arm,rainier"; + reg =3D <0x0 0x10100>; + device_type =3D "cpu"; + enable-method =3D "psci"; + /* 4 ways set associative */ + i-cache-size =3D <0x10000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <512>; + d-cache-size =3D <0x10000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_3>; + clocks =3D <&scmi_dvfs 1>; + + l2_3: l2-cache-3 { + compatible =3D "cache"; + cache-level =3D <2>; + /* 8 ways set associative */ + cache-size =3D <0x100000>; + cache-line-size =3D <64>; + cache-sets =3D <2048>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + }; + + firmware { + interrupt-parent =3D <&gic>; + + scmi { + compatible =3D "arm,scmi"; + mbox-names =3D "tx", "rx"; + mboxes =3D <&mailbox 1 0>, <&mailbox 1 1>; + shmem =3D <&cpu_scp_hpri0>, <&cpu_scp_hpri1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + scmi_dvfs: protocol@13 { + reg =3D <0x13>; + #clock-cells =3D <1>; + }; + + scmi_clk: protocol@14 { + reg =3D <0x14>; + #clock-cells =3D <1>; + }; + }; + }; + + /* The first bank of memory, memory map is actually provided by UEFI. */ + memory@80000000 { + device_type =3D "memory"; + /* [0x80000000-0xffffffff] */ + reg =3D <0x00000000 0x80000000 0x0 0x7f000000>; + }; + + memory@8080000000 { + device_type =3D "memory"; + /* [0x8080000000-0x83f7ffffff] */ + reg =3D <0x00000080 0x80000000 0x3 0x78000000>; + }; + + pmu { + compatible =3D "arm,rainier-pmu"; + interrupts =3D ; + }; + + psci { + compatible =3D "arm,psci-0.2"; + method =3D "smc"; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + secure-firmware@ff000000 { + reg =3D <0x0 0xff000000 0x0 0x01000000>; + no-map; + }; + }; + + spe-pmu { + compatible =3D "arm,statistical-profiling-extension-v1"; + interrupts =3D ; + }; + + soc: soc { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + interrupt-parent =3D <&gic>; + ranges; + + uart0: serial@2a400000 { + compatible =3D "arm,pl011", "arm,primecell"; + reg =3D <0x0 0x2a400000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&soc_refclk50mhz>, <&soc_refclk50mhz>; + clock-names =3D "uartclk", "apb_pclk"; + + status =3D "disabled"; + }; + + gic: interrupt-controller@2c010000 { + compatible =3D "arm,gic-v3"; + reg =3D <0x0 0x30000000 0x0 0x10000>, /* GICD */ + <0x0 0x300c0000 0x0 0x80000>; /* GICR */ + + interrupts =3D ; + + #interrupt-cells =3D <3>; + interrupt-controller; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + its1: msi-controller@30040000 { + compatible =3D "arm,gic-v3-its"; + reg =3D <0x0 0x30040000 0x0 0x20000>; + + msi-controller; + #msi-cells =3D <1>; + }; + + its2: msi-controller@30060000 { + compatible =3D "arm,gic-v3-its"; + reg =3D <0x0 0x30060000 0x0 0x20000>; + + msi-controller; + #msi-cells =3D <1>; + }; + + its_ccix: msi-controller@30080000 { + compatible =3D "arm,gic-v3-its"; + reg =3D <0x0 0x30080000 0x0 0x20000>; + + msi-controller; + #msi-cells =3D <1>; + }; + + its_pcie: msi-controller@300a0000 { + compatible =3D "arm,gic-v3-its"; + reg =3D <0x0 0x300a0000 0x0 0x20000>; + + msi-controller; + #msi-cells =3D <1>; + }; + }; + + smmu_dp: iommu@2ce00000 { + compatible =3D "arm,smmu-v3"; + reg =3D <0x0 0x2ce00000 0x0 0x40000>; + + interrupts =3D , + , + ; + interrupt-names =3D "eventq", "gerror", "cmdq-sync"; + #iommu-cells =3D <1>; + }; + + mailbox: mhu@45000000 { + compatible =3D "arm,mhu-doorbell", "arm,primecell"; + reg =3D <0x0 0x45000000 0x0 0x1000>; + + interrupts =3D , + ; + #mbox-cells =3D <2>; + clocks =3D <&soc_refclk50mhz>; + clock-names =3D "apb_pclk"; + }; + + sram: sram@45200000 { + compatible =3D "mmio-sram"; + reg =3D <0x0 0x06000000 0x0 0x8000>; + ranges =3D <0 0x0 0x06000000 0x8000>; + + #address-cells =3D <1>; + #size-cells =3D <1>; + + cpu_scp_hpri0: scp-sram@0 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0x80>; + }; + + cpu_scp_hpri1: scp-sram@80 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x80 0x80>; + }; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + }; +}; --=20 2.43.0 From nobody Tue Dec 16 19:33:07 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id BD690253F35; Fri, 21 Feb 2025 18:04:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740161059; cv=none; b=nvVNGaFn/qhYaxS23NlccENXAEPOJFbc4yUxdYs1KsOyy2OL1ylvT29eAblqGsQuD2xX4hhqhi+Brs7Un4TzIOn2+jsIYdWUbxmoTNKG1/RySB6dwyixRE5QisbYeFrzge3sFZg18lVP6NMq/mM5/Ph9GFtaXjzcazolWEDrvWw= ARC-Message-Signature: i=1; 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Fri, 21 Feb 2025 10:04:13 -0800 (PST) From: Vincenzo Frascino To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Vincenzo Frascino , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Russell King , Will Deacon , Mark Rutland , Jessica Clarke Subject: [PATCH v7 08/10] arm64: dts: morello: Add support for soc dts Date: Fri, 21 Feb 2025 18:03:47 +0000 Message-ID: <20250221180349.1413089-9-vincenzo.frascino@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250221180349.1413089-1-vincenzo.frascino@arm.com> References: <20250221180349.1413089-1-vincenzo.frascino@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Morello architecture is an experimental extension to Armv8.2-A, which extends the AArch64 state with the principles proposed in version 7 of the Capability Hardware Enhanced RISC Instructions (CHERI) ISA. Introduce Morello SoC dts. Signed-off-by: Vincenzo Frascino Reviewed-by: Linus Walleij --- arch/arm64/boot/dts/arm/Makefile | 1 + arch/arm64/boot/dts/arm/morello-sdp.dts | 157 ++++++++++++++++++++++++ 2 files changed, 158 insertions(+) create mode 100644 arch/arm64/boot/dts/arm/morello-sdp.dts diff --git a/arch/arm64/boot/dts/arm/Makefile b/arch/arm64/boot/dts/arm/Mak= efile index d908e96d7ddc..869667bef7c0 100644 --- a/arch/arm64/boot/dts/arm/Makefile +++ b/arch/arm64/boot/dts/arm/Makefile @@ -7,3 +7,4 @@ dtb-$(CONFIG_ARCH_VEXPRESS) +=3D rtsm_ve-aemv8a.dtb dtb-$(CONFIG_ARCH_VEXPRESS) +=3D vexpress-v2f-1xv7-ca53x2.dtb dtb-$(CONFIG_ARCH_VEXPRESS) +=3D fvp-base-revc.dtb dtb-$(CONFIG_ARCH_VEXPRESS) +=3D corstone1000-fvp.dtb corstone1000-mps3.dtb +dtb-$(CONFIG_ARCH_VEXPRESS) +=3D morello-sdp.dtb diff --git a/arch/arm64/boot/dts/arm/morello-sdp.dts b/arch/arm64/boot/dts/= arm/morello-sdp.dts new file mode 100644 index 000000000000..cee49dee7571 --- /dev/null +++ b/arch/arm64/boot/dts/arm/morello-sdp.dts @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (c) 2021-2024, Arm Limited. All rights reserved. + */ + +/dts-v1/; +#include "morello.dtsi" + +/ { + model =3D "Arm Morello System Development Platform"; + compatible =3D "arm,morello-sdp", "arm,morello"; + + aliases { + serial0 =3D &uart0; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + dpu_aclk: clock-350000000 { + /* 77.1 MHz derived from 24 MHz reference clock */ + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <350000000>; + clock-output-names =3D "aclk"; + }; + + dpu_pixel_clk: clock-148500000 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <148500000>; + clock-output-names =3D "pxclk"; + }; + + i2c0: i2c@1c0f0000 { + compatible =3D "cdns,i2c-r1p14"; + reg =3D <0x0 0x1c0f0000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&dpu_aclk>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + clock-frequency =3D <100000>; + + hdmi_tx: hdmi-transmitter@70 { + compatible =3D "nxp,tda998x"; + reg =3D <0x70>; + video-ports =3D <0x234501>; + port { + tda998x_0_input: endpoint { + remote-endpoint =3D <&dp_pl0_out0>; + }; + }; + }; + }; + + dp0: display@2cc00000 { + compatible =3D "arm,mali-d32", "arm,mali-d71"; + reg =3D <0x0 0x2cc00000 0x0 0x20000>; + interrupts =3D <0 69 4>; + clocks =3D <&dpu_aclk>; + clock-names =3D "aclk"; + iommus =3D <&smmu_dp 0>, <&smmu_dp 1>, <&smmu_dp 2>, <&smmu_dp 3>, + <&smmu_dp 8>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + pl0: pipeline@0 { + reg =3D <0>; + clocks =3D <&dpu_pixel_clk>; + clock-names =3D "pxclk"; + port { + dp_pl0_out0: endpoint { + remote-endpoint =3D <&tda998x_0_input>; + }; + }; + }; + }; + + smmu_ccix: iommu@4f000000 { + compatible =3D "arm,smmu-v3"; + reg =3D <0x0 0x4f000000 0x0 0x40000>; + + interrupts =3D , + , + , + ; + interrupt-names =3D "eventq", "gerror", "priq", "cmdq-sync"; + msi-parent =3D <&its1 0>; + #iommu-cells =3D <1>; + dma-coherent; + }; + + smmu_pcie: iommu@4f400000 { + compatible =3D "arm,smmu-v3"; + reg =3D <0x0 0x4f400000 0x0 0x40000>; + + interrupts =3D , + , + , + ; + interrupt-names =3D "eventq", "gerror", "priq", "cmdq-sync"; + msi-parent =3D <&its2 0>; + #iommu-cells =3D <1>; + dma-coherent; + }; + + pcie_ctlr: pcie@28c0000000 { + device_type =3D "pci"; + compatible =3D "pci-host-ecam-generic"; + reg =3D <0x28 0xC0000000 0 0x10000000>; + ranges =3D <0x01000000 0x00 0x00000000 0x00 0x6f000000 0x00 0x00800000>, + <0x02000000 0x00 0x60000000 0x00 0x60000000 0x00 0x0f000000>, + <0x42000000 0x09 0x00000000 0x09 0x00000000 0x1f 0xc0000000>; + bus-range =3D <0 255>; + linux,pci-domain =3D <0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + dma-coherent; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &gic 0 0 0 169 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic 0 0 0 170 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic 0 0 0 171 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic 0 0 0 172 IRQ_TYPE_LEVEL_HIGH>; + msi-map =3D <0 &its_pcie 0 0x10000>; + iommu-map =3D <0 &smmu_pcie 0 0x10000>; + }; + + ccix_pcie_ctlr: pcie@4fc0000000 { + device_type =3D "pci"; + compatible =3D "pci-host-ecam-generic"; + reg =3D <0x4f 0xC0000000 0 0x10000000>; + ranges =3D <0x01000000 0x00 0x00000000 0x00 0x7f000000 0x00 0x00800000>, + <0x02000000 0x00 0x70000000 0x00 0x70000000 0x00 0x0f000000>, + <0x42000000 0x30 0x00000000 0x30 0x00000000 0x1f 0xc0000000>; + linux,pci-domain =3D <1>; + #address-cells =3D <3>; + #size-cells =3D <2>; + dma-coherent; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &gic 0 0 0 201 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic 0 0 0 202 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic 0 0 0 203 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic 0 0 0 204 IRQ_TYPE_LEVEL_HIGH>; + msi-map =3D <0 &its_ccix 0 0x10000>; + iommu-map =3D <0 &smmu_ccix 0 0x10000>; + }; +}; + +&uart0 { + status =3D "okay"; +}; --=20 2.43.0 From nobody Tue Dec 16 19:33:07 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id E41F5253F3E; Fri, 21 Feb 2025 18:04:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 371F2169C; Fri, 21 Feb 2025 10:04:36 -0800 (PST) Received: from e119884-lin.cambridge.arm.com (e119884-lin.cambridge.arm.com [10.1.196.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6147C3F59E; Fri, 21 Feb 2025 10:04:16 -0800 (PST) From: Vincenzo Frascino To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Vincenzo Frascino , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Russell King , Will Deacon , Mark Rutland , Jessica Clarke Subject: [PATCH v7 09/10] arm64: dts: morello: Add support for fvp dts Date: Fri, 21 Feb 2025 18:03:48 +0000 Message-ID: <20250221180349.1413089-10-vincenzo.frascino@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250221180349.1413089-1-vincenzo.frascino@arm.com> References: <20250221180349.1413089-1-vincenzo.frascino@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Morello architecture is an experimental extension to Armv8.2-A, which extends the AArch64 state with the principles proposed in version 7 of the Capability Hardware Enhanced RISC Instructions (CHERI) ISA. Introduce Morello fvp dts. Signed-off-by: Vincenzo Frascino Reviewed-by: Linus Walleij --- arch/arm64/boot/dts/arm/Makefile | 2 +- arch/arm64/boot/dts/arm/morello-fvp.dts | 77 +++++++++++++++++++++++++ 2 files changed, 78 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/arm/morello-fvp.dts diff --git a/arch/arm64/boot/dts/arm/Makefile b/arch/arm64/boot/dts/arm/Mak= efile index 869667bef7c0..f30ee045dc95 100644 --- a/arch/arm64/boot/dts/arm/Makefile +++ b/arch/arm64/boot/dts/arm/Makefile @@ -7,4 +7,4 @@ dtb-$(CONFIG_ARCH_VEXPRESS) +=3D rtsm_ve-aemv8a.dtb dtb-$(CONFIG_ARCH_VEXPRESS) +=3D vexpress-v2f-1xv7-ca53x2.dtb dtb-$(CONFIG_ARCH_VEXPRESS) +=3D fvp-base-revc.dtb dtb-$(CONFIG_ARCH_VEXPRESS) +=3D corstone1000-fvp.dtb corstone1000-mps3.dtb -dtb-$(CONFIG_ARCH_VEXPRESS) +=3D morello-sdp.dtb +dtb-$(CONFIG_ARCH_VEXPRESS) +=3D morello-sdp.dtb morello-fvp.dtb diff --git a/arch/arm64/boot/dts/arm/morello-fvp.dts b/arch/arm64/boot/dts/= arm/morello-fvp.dts new file mode 100644 index 000000000000..2072c0b72325 --- /dev/null +++ b/arch/arm64/boot/dts/arm/morello-fvp.dts @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (c) 2021-2024, Arm Limited. All rights reserved. + */ + +/dts-v1/; +#include "morello.dtsi" + +/ { + model =3D "Arm Morello Fixed Virtual Platform"; + compatible =3D "arm,morello-fvp", "arm,morello"; + + aliases { + serial0 =3D &uart0; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + bp_refclock24mhz: clock-24000000 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <24000000>; + clock-output-names =3D "bp:clock24mhz"; + }; + + block_0: virtio_block@1c170000 { + compatible =3D "virtio,mmio"; + reg =3D <0x0 0x1c170000 0x0 0x200>; + interrupts =3D ; + }; + + net_0: virtio_net@1c180000 { + compatible =3D "virtio,mmio"; + reg =3D <0x0 0x1c180000 0x0 0x200>; + interrupts =3D ; + }; + + rng_0: virtio_rng@1c190000 { + compatible =3D "virtio,mmio"; + reg =3D <0x0 0x1c190000 0x0 0x200>; + interrupts =3D ; + }; + + p9_0: virtio_p9@1c1a0000 { + compatible =3D "virtio,mmio"; + reg =3D <0x0 0x1c1a0000 0x0 0x200>; + interrupts =3D ; + }; + + kmi_0: kmi@1c150000 { + compatible =3D "arm,pl050", "arm,primecell"; + reg =3D <0x0 0x1c150000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&bp_refclock24mhz>, <&bp_refclock24mhz>; + clock-names =3D "KMIREFCLK", "apb_pclk"; + }; + + kmi_1: kmi@1c160000 { + compatible =3D "arm,pl050", "arm,primecell"; + reg =3D <0x0 0x1c160000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&bp_refclock24mhz>, <&bp_refclock24mhz>; + clock-names =3D "KMIREFCLK", "apb_pclk"; + }; + + eth_0: ethernet@1d100000 { + compatible =3D "smsc,lan91c111"; + reg =3D <0x0 0x1d100000 0x0 0x10000>; + interrupts =3D ; + }; +}; + +&uart0 { + status =3D "okay"; +}; --=20 2.43.0 From nobody Tue Dec 16 19:33:07 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 75F53254B0C; Fri, 21 Feb 2025 18:04:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740161062; cv=none; b=E2en3nRnPZ/Vaxp0U+TydIbzkMiHj7PDTnvBkX8KPMxQ2btVBVDJVtmX49Stn7BqaDJiW7mTY0exZgUlB98HQW4YZd23jaqCkR0beuyIxH5Uxj2+Ozl9bEFLnagPiIiD8h2lQVyiMGHsxHWSpsozKHl6Fcju7RYmrC2M7D/mxXE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740161062; c=relaxed/simple; bh=0kLYZcRL43WmeeTxClig95KR+zknL1JhMw9OnsaSdb4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=o1lFUDDM1I6t2117kuQvId8UirSgKC9NBJSVmKCOdEi3eGKP60TicB11Y8P7yEzw9jC2CtK0K4TRJqF8HJdbly+PFc/Cx5WHLQbuuxxmGKXYDFlxzZDBBx9iXdplAIVHkxILNWjPNGF4wWiZgeMCavhvWG7lOXDHNd2y9tzJQE8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BDEB41CC4; Fri, 21 Feb 2025 10:04:38 -0800 (PST) Received: from e119884-lin.cambridge.arm.com (e119884-lin.cambridge.arm.com [10.1.196.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id CA64E3F59E; Fri, 21 Feb 2025 10:04:18 -0800 (PST) From: Vincenzo Frascino To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Vincenzo Frascino , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Russell King , Will Deacon , Mark Rutland , Jessica Clarke , Krzysztof Kozlowski Subject: [PATCH v7 10/10] MAINTAINERS: Add Vincenzo Frascino as Arm Morello Maintainer Date: Fri, 21 Feb 2025 18:03:49 +0000 Message-ID: <20250221180349.1413089-11-vincenzo.frascino@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250221180349.1413089-1-vincenzo.frascino@arm.com> References: <20250221180349.1413089-1-vincenzo.frascino@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add Vincenzo Frascino as Arm Morello Software Development Platform Maintainer. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Vincenzo Frascino Reviewed-by: Linus Walleij --- MAINTAINERS | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 3864d473f52f..6aaef2286de8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2750,6 +2750,13 @@ F: arch/arm/boot/dts/socionext/milbeaut* F: arch/arm/mach-milbeaut/ N: milbeaut =20 +ARM/MORELLO PLATFORM +M: Vincenzo Frascino +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +S: Maintained +F: Documentation/devicetree/bindings/arm/arm,morello.yaml +F: arch/arm64/boot/dts/arm/morello* + ARM/MOXA ART SOC M: Krzysztof Kozlowski L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) --=20 2.43.0