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Fri, 21 Feb 2025 09:23:21 -0800 (PST) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dingwei@marvell.com, cassel@kernel.org, Manivannan Sadhasivam Subject: [PATCH 1/2] PCI: Add pci_host_bridge_handle_link_down() API to handle the PCI link down event Date: Fri, 21 Feb 2025 22:53:08 +0530 Message-Id: <20250221172309.120009-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250221172309.120009-1-manivannan.sadhasivam@linaro.org> References: <20250221172309.120009-1-manivannan.sadhasivam@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The PCI link, when down, needs to be retrained to bring it back. But that cannot be done in a generic way as link retrain procedure is specific to host bridges. So add a new API pci_host_bridge_handle_link_down() that could be called by the host bridge drivers when the link goes down. The API will remove all the devices from the root bus since there is no way the PCI core/drivers can access them and then calls the bus specific 'retrain_link()' callback if available. This callback is supposed to be implemented by the host bridge drivers to retrain the link in a platform specific way. Once that succeeds, the API will rescan the bus to bring the devices back. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/probe.c | 34 ++++++++++++++++++++++++++++++++++ include/linux/pci.h | 2 ++ 2 files changed, 36 insertions(+) diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index b6536ed599c3..36ffcd2a44a5 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -706,6 +706,40 @@ void pci_free_host_bridge(struct pci_host_bridge *brid= ge) } EXPORT_SYMBOL(pci_free_host_bridge); =20 +void pci_host_bridge_handle_link_down(struct pci_host_bridge *bridge) +{ + struct pci_bus *bus =3D bridge->bus; + struct device *dev =3D &bridge->dev; + struct pci_dev *child, *tmp; + int ret; + + pci_lock_rescan_remove(); + + /* Knock the devices off root bus since we cannot access them */ + dev_warn(dev, "Removing devices from root bus due to link down\n"); + list_for_each_entry_safe(child, tmp, &bus->devices, bus_list) + pci_stop_and_remove_bus_device(child); + + /* Now retrain the link in a vendor specific way to bring it back */ + if (bus->ops->retrain_link) { + dev_info(dev, "Starting link retraining\n"); + ret =3D bus->ops->retrain_link(bus); + if (ret) { + dev_err(dev, "Failed to retrain the link\n"); + pci_unlock_rescan_remove(); + return; + } + dev_info(dev, "Link retraining completed\n"); + } else { + dev_warn(dev, "retrain_link() callback not implemented!\n"); + } + + /* Finally, rescan the bus to bring the devices back */ + pci_rescan_bus(bus); + pci_unlock_rescan_remove(); +} +EXPORT_SYMBOL(pci_host_bridge_handle_link_down); + /* Indexed by PCI_X_SSTATUS_FREQ (secondary bus mode and frequency) */ static const unsigned char pcix_bus_speed[] =3D { PCI_SPEED_UNKNOWN, /* 0 */ diff --git a/include/linux/pci.h b/include/linux/pci.h index 47b31ad724fa..1c6f18a51bdd 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -637,6 +637,7 @@ struct pci_host_bridge *pci_alloc_host_bridge(size_t pr= iv); struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev, size_t priv); void pci_free_host_bridge(struct pci_host_bridge *bridge); +void pci_host_bridge_handle_link_down(struct pci_host_bridge *bridge); struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus); =20 void pci_set_host_bridge_release(struct pci_host_bridge *bridge, @@ -804,6 +805,7 @@ struct pci_ops { void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int whe= re); int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size,= u32 *val); int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size= , u32 val); + int (*retrain_link)(struct pci_bus *bus); }; =20 /* --=20 2.25.1 From nobody Tue Dec 16 19:23:21 2025 Received: from mail-pl1-f181.google.com (mail-pl1-f181.google.com [209.85.214.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C2B972505D1 for ; Fri, 21 Feb 2025 17:23:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.181 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740158609; cv=none; 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Fri, 21 Feb 2025 09:23:25 -0800 (PST) Received: from localhost.localdomain ([120.60.73.12]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-220d545c814sm141243405ad.148.2025.02.21.09.23.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2025 09:23:25 -0800 (PST) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dingwei@marvell.com, cassel@kernel.org, Manivannan Sadhasivam Subject: [PATCH 2/2] PCI: qcom: Add support for retraining the link due to link down event Date: Fri, 21 Feb 2025 22:53:09 +0530 Message-Id: <20250221172309.120009-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250221172309.120009-1-manivannan.sadhasivam@linaro.org> References: <20250221172309.120009-1-manivannan.sadhasivam@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The PCIe link can go down under circumstances such as the device removed from the bus, reset condition, etc... When that happens, the link needs to be retrained back to make it operational again. Currently, the driver is not handling the link down event, due to which the users have to restart the machine to make PCIe link operational again. So fix it by detecting the link down event and adding support to retraining the link. Since the Qcom PCIe controllers report the link down event through the 'global' IRQ, enable the link down event by setting PARF_INT_ALL_LINK_DOWN bit in PARF_INT_ALL_MASK register. Then in the case of the event, call pci_host_bridge_handle_link_down() API in the handler to let the PCI core handle the link down condition. The API will internally call, 'pci_ops::retrain_link()' callback to retrain the link in a platform specific way. So implement the callback to retrain the link by first resetting the PCIe core, followed by reinitializing the resources and then finally starting the link again. The PCI core will finally rescan the bus to enumerate the devices. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 90 +++++++++++++++++++++++++- 1 file changed, 88 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index e4d3366ead1f..ebc58e88161e 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -55,6 +55,7 @@ #define PARF_INT_ALL_STATUS 0x224 #define PARF_INT_ALL_CLEAR 0x228 #define PARF_INT_ALL_MASK 0x22c +#define PARF_STATUS 0x230 #define PARF_SID_OFFSET 0x234 #define PARF_BDF_TRANSLATE_CFG 0x24c #define PARF_DBI_BASE_ADDR_V2 0x350 @@ -130,8 +131,11 @@ =20 /* PARF_LTSSM register fields */ #define LTSSM_EN BIT(8) +#define SW_CLEAR_FLUSH_MODE BIT(10) +#define FLUSH_MODE BIT(11) =20 /* PARF_INT_ALL_{STATUS/CLEAR/MASK} register fields */ +#define PARF_INT_ALL_LINK_DOWN BIT(1) #define PARF_INT_ALL_LINK_UP BIT(13) #define PARF_INT_MSI_DEV_0_7 GENMASK(30, 23) =20 @@ -145,6 +149,9 @@ /* PARF_BDF_TO_SID_CFG fields */ #define BDF_TO_SID_BYPASS BIT(0) =20 +/* PARF_STATUS fields */ +#define FLUSH_COMPLETED BIT(8) + /* ELBI_SYS_CTRL register fields */ #define ELBI_SYS_CTRL_LT_ENABLE BIT(0) =20 @@ -169,6 +176,7 @@ PCIE_CAP_SLOT_POWER_LIMIT_SCALE) =20 #define PERST_DELAY_US 1000 +#define FLUSH_TIMEOUT_US 100 =20 #define QCOM_PCIE_CRC8_POLYNOMIAL (BIT(2) | BIT(1) | BIT(0)) =20 @@ -239,6 +247,7 @@ union qcom_pcie_resources { }; =20 struct qcom_pcie; +static struct pci_ops qcom_pcie_bridge_ops; =20 struct qcom_pcie_ops { int (*get_resources)(struct qcom_pcie *pcie); @@ -274,6 +283,7 @@ struct qcom_pcie { struct icc_path *icc_cpu; const struct qcom_pcie_cfg *cfg; struct dentry *debugfs; + int global_irq; bool suspended; bool use_pm_opp; }; @@ -1263,6 +1273,8 @@ static int qcom_pcie_host_init(struct dw_pcie_rp *pp) goto err_assert_reset; } =20 + pp->bridge->ops =3D &qcom_pcie_bridge_ops; + return 0; =20 err_assert_reset: @@ -1300,6 +1312,75 @@ static const struct dw_pcie_host_ops qcom_pcie_dw_op= s =3D { .post_init =3D qcom_pcie_host_post_init, }; =20 +static int qcom_pcie_retrain_link(struct pci_bus *bus) +{ + struct dw_pcie_rp *pp =3D bus->sysdata; + struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); + struct qcom_pcie *pcie =3D to_qcom_pcie(pci); + struct device *dev =3D pcie->pci->dev; + u32 val; + int ret; + + /* Wait for the pending transactions to be completed */ + ret =3D readl_relaxed_poll_timeout(pcie->parf + PARF_STATUS, val, + val & FLUSH_COMPLETED, 10, + FLUSH_TIMEOUT_US); + if (ret) { + dev_err(dev, "Flush completion failed: %d\n", ret); + goto err_host_deinit; + } + + /* Clear the FLUSH_MODE to allow the core to be reset */ + val =3D readl(pcie->parf + PARF_LTSSM); + val |=3D SW_CLEAR_FLUSH_MODE; + writel(val, pcie->parf + PARF_LTSSM); + + /* Wait for the FLUSH_MODE to clear */ + ret =3D readl_relaxed_poll_timeout(pcie->parf + PARF_LTSSM, val, + !(val & FLUSH_MODE), 10, + FLUSH_TIMEOUT_US); + if (ret) { + dev_err(dev, "Flush mode clear failed: %d\n", ret); + goto err_host_deinit; + } + + qcom_pcie_host_deinit(pp); + + ret =3D qcom_pcie_host_init(pp); + if (ret) { + dev_err(dev, "Host init failed\n"); + return ret; + } + + ret =3D dw_pcie_setup_rc(pp); + if (ret) + goto err_host_deinit; + + /* + * Re-enable global IRQ events as the PARF_INT_ALL_MASK register is + * non-sticky. + */ + if (pcie->global_irq) + writel_relaxed(PARF_INT_ALL_LINK_UP | PARF_INT_ALL_LINK_DOWN | + PARF_INT_MSI_DEV_0_7, pcie->parf + PARF_INT_ALL_MASK); + + qcom_pcie_start_link(pci); + + return 0; + +err_host_deinit: + qcom_pcie_host_deinit(pp); + + return ret; +} + +static struct pci_ops qcom_pcie_bridge_ops =3D { + .map_bus =3D dw_pcie_own_conf_map_bus, + .read =3D pci_generic_config_read, + .write =3D pci_generic_config_write, + .retrain_link =3D qcom_pcie_retrain_link, +}; + /* Qcom IP rev.: 2.1.0 Synopsys IP rev.: 4.01a */ static const struct qcom_pcie_ops ops_2_1_0 =3D { .get_resources =3D qcom_pcie_get_resources_2_1_0, @@ -1571,6 +1652,9 @@ static irqreturn_t qcom_pcie_global_irq_thread(int ir= q, void *data) pci_unlock_rescan_remove(); =20 qcom_pcie_icc_opp_update(pcie); + } else if (FIELD_GET(PARF_INT_ALL_LINK_DOWN, status)) { + dev_dbg(dev, "Received Link down event\n"); + pci_host_bridge_handle_link_down(pp->bridge); } else { dev_WARN_ONCE(dev, 1, "Received unknown event. INT_STATUS: 0x%08x\n", status); @@ -1732,8 +1816,10 @@ static int qcom_pcie_probe(struct platform_device *p= dev) goto err_host_deinit; } =20 - writel_relaxed(PARF_INT_ALL_LINK_UP | PARF_INT_MSI_DEV_0_7, - pcie->parf + PARF_INT_ALL_MASK); + writel_relaxed(PARF_INT_ALL_LINK_UP | PARF_INT_ALL_LINK_DOWN | + PARF_INT_MSI_DEV_0_7, pcie->parf + PARF_INT_ALL_MASK); + + pcie->global_irq =3D irq; } =20 qcom_pcie_icc_opp_update(pcie); --=20 2.25.1