From nobody Mon Feb 9 13:10:09 2026 Received: from s2.avantea.pl (s2.avantea.pl [46.242.128.95]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ED1D4214A97; Fri, 21 Feb 2025 16:40:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=46.242.128.95 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740156021; cv=none; b=YI4nJ8HlzG02oqGCV2SVike5aAINCfJK+9XdeHc3zIT4iYvXz7s+RiVOAV+uQWKqCeU6PxCZyHsvYTKAGIehTFv6A8jVSca0+uz6fFfELEMug7/0OBia7klVeiFg8KjLzuGMouIiHUglpHSE5etuQUvNeyDZ04scucDe4wTmnJ0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740156021; c=relaxed/simple; bh=xJu7so+7BBYyhSfxXPYt/2ar3s2g1qidAkZvUjP5T2c=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=ZmfWumwhNV4lbhwiAmc9iQsyFYsqtVJHNFu+/T/uvM2gpT54iJuToBqYmbwjEa0Kaga21MdnoP0EZgSp5HxipjhlcGADYWzXznahorB09G5N8Ah6R+txCQ/vmttlvC+5aSrOwsw+KpjC4I3W77PmKcsI2NDECBhJi7Vk9a+FpIo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=szczodrzynski.pl; spf=pass smtp.mailfrom=szczodrzynski.pl; dkim=pass (2048-bit key) header.d=szczodrzynski.pl header.i=@szczodrzynski.pl header.b=HcK5seWl; arc=none smtp.client-ip=46.242.128.95 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=szczodrzynski.pl Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=szczodrzynski.pl Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=szczodrzynski.pl header.i=@szczodrzynski.pl header.b="HcK5seWl" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=szczodrzynski.pl; s=x; h=Content-Transfer-Encoding:Content-Type: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender :Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help: List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=5/V9/R7a9isS+zNiVj1HLAhpc5SCNNFYHIXlJodspTU=; b=HcK5seWlZAZbl0hkdyDFlNS5rh zZbbTejohyTCnv9XobrgEqiUzeWFg02A27ueeoZcrmNhZZKVl2qGxpFFjE9ffbW+00X6Jx7F0YRwi O00wkrUdGkcVfqQUjiEw6HFhlMvIcRVel6Wf2ZeN2uRYVPokh/iRjKMB0YB3Y2tGXG50AoSqWy1Sg RHOYGl52iJ0kDEAvqFsQLkSYEVp2UVgrBYiB1+Hi2PVUj/AAHxxuH8q+zOBC7CqTUkgiZybWb3R7D ARmTlh34ETeynSRA7MHUeRj+l8WI3F4wh9fyhev6lEATYAVlqor0dcaUQWYkHb1vqlNwStGf10Czu E9ZVLf7w==; Received: from [62.171.184.96] (helo=buildhost.contaboserver.net) by s2.avantea.pl with esmtpsa (TLS1.3) tls TLS_AES_256_GCM_SHA384 (Exim 4.96-58-g4e9ed49f8) (envelope-from ) id 1tlViu-00AOLX-1R; Fri, 21 Feb 2025 17:17:56 +0100 From: =?UTF-8?q?Kuba=20Szczodrzy=C5=84ski?= To: Maxime Ripard , Samuel Holland , Chen-Yu Tsai , Jernej Skrabec , Maarten Lankhorst , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: David Airlie , Simona Vetter , linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org Subject: [PATCH 1/5] phy: allwinner: phy-sun6i-mipi-dphy: Support LVDS in combo D-PHY Date: Fri, 21 Feb 2025 17:17:47 +0100 Message-Id: <20250221161751.1278049-2-kuba@szczodrzynski.pl> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250221161751.1278049-1-kuba@szczodrzynski.pl> References: <20250221161751.1278049-1-kuba@szczodrzynski.pl> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Authenticated-Id: kuba@szczodrzynski.pl Some Allwinner chips (notably the D1s/T113 and the A100) have a "combo MIPI DSI D-PHY" which is required when using single-link LVDS0. In this mode, the DSI peripheral is not used and the PHY is not configured for DSI. Instead, the COMBO_PHY_REGx registers are set to enable LVDS operation. Enable the PHY driver to work in LVDS mode on chips with a combo D-PHY. Signed-off-by: Kuba Szczodrzy=C5=84ski --- drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 65 ++++++++++++++++++++- 1 file changed, 63 insertions(+), 2 deletions(-) diff --git a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c b/drivers/phy/allw= inner/phy-sun6i-mipi-dphy.c index 36eab9527..f958e34da 100644 --- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c +++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c @@ -166,8 +166,8 @@ #define SUN50I_COMBO_PHY_REG0_EN_CP BIT(0) =20 #define SUN50I_COMBO_PHY_REG1 0x114 -#define SUN50I_COMBO_PHY_REG2_REG_VREF1P6(n) (((n) & 0x7) << 4) -#define SUN50I_COMBO_PHY_REG2_REG_VREF0P8(n) ((n) & 0x7) +#define SUN50I_COMBO_PHY_REG1_REG_VREF1P6(n) (((n) & 0x7) << 4) +#define SUN50I_COMBO_PHY_REG1_REG_VREF0P8(n) ((n) & 0x7) =20 #define SUN50I_COMBO_PHY_REG2 0x118 #define SUN50I_COMBO_PHY_REG2_HS_STOP_DLY(n) ((n) & 0xff) @@ -181,7 +181,9 @@ struct sun6i_dphy; =20 struct sun6i_dphy_variant { void (*tx_power_on)(struct sun6i_dphy *dphy); + void (*lvds_power_on)(struct sun6i_dphy *dphy); bool rx_supported; + bool is_combo_dphy; }; =20 struct sun6i_dphy { @@ -222,6 +224,18 @@ static int sun6i_dphy_configure(struct phy *phy, union= phy_configure_opts *opts) return 0; } =20 +static int sun6i_dphy_set_mode(struct phy *phy, enum phy_mode mode, int su= bmode) +{ + struct sun6i_dphy *dphy =3D phy_get_drvdata(phy); + + if (mode =3D=3D PHY_MODE_LVDS && !dphy->variant->is_combo_dphy) { + /* Not a combo D-PHY: LVDS is not supported */ + return -EINVAL; + } + + return 0; +} + static void sun6i_a31_mipi_dphy_tx_power_on(struct sun6i_dphy *dphy) { u8 lanes_mask =3D GENMASK(dphy->config.lanes - 1, 0); @@ -329,6 +343,37 @@ static void sun50i_a100_mipi_dphy_tx_power_on(struct s= un6i_dphy *dphy) udelay(1); } =20 +static void sun50i_a100_mipi_dphy_lvds_power_on(struct sun6i_dphy *dphy) +{ + regmap_write(dphy->regs, SUN50I_COMBO_PHY_REG1, + SUN50I_COMBO_PHY_REG1_REG_VREF1P6(4) | + SUN50I_COMBO_PHY_REG1_REG_VREF0P8(3)); + + regmap_write(dphy->regs, SUN50I_COMBO_PHY_REG0, + SUN50I_COMBO_PHY_REG0_EN_CP); + udelay(5); + regmap_update_bits(dphy->regs, SUN50I_COMBO_PHY_REG0, + SUN50I_COMBO_PHY_REG0_EN_LVDS, + SUN50I_COMBO_PHY_REG0_EN_LVDS); + udelay(5); + regmap_update_bits(dphy->regs, SUN50I_COMBO_PHY_REG0, + SUN50I_COMBO_PHY_REG0_EN_COMBOLDO, + SUN50I_COMBO_PHY_REG0_EN_COMBOLDO); + udelay(5); + regmap_update_bits(dphy->regs, SUN50I_COMBO_PHY_REG0, + SUN50I_COMBO_PHY_REG0_EN_MIPI, + SUN50I_COMBO_PHY_REG0_EN_MIPI); + + regmap_write(dphy->regs, SUN6I_DPHY_ANA4_REG, + SUN6I_DPHY_ANA4_REG_EN_MIPI | + SUN6I_DPHY_ANA4_REG_IB(2)); + regmap_write(dphy->regs, SUN6I_DPHY_ANA3_REG, + SUN6I_DPHY_ANA3_EN_LDOR | + SUN6I_DPHY_ANA3_EN_LDOD); + regmap_write(dphy->regs, SUN6I_DPHY_ANA2_REG, 0); + regmap_write(dphy->regs, SUN6I_DPHY_ANA1_REG, 0); +} + static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy) { u8 lanes_mask =3D GENMASK(dphy->config.lanes - 1, 0); @@ -492,6 +537,14 @@ static int sun6i_dphy_power_on(struct phy *phy) { struct sun6i_dphy *dphy =3D phy_get_drvdata(phy); =20 + if (phy->attrs.mode =3D=3D PHY_MODE_LVDS && dphy->variant->is_combo_dphy)= { + if (dphy->variant->lvds_power_on) { + dphy->variant->lvds_power_on(dphy); + return 0; + } + return -EINVAL; + } + switch (dphy->direction) { case SUN6I_DPHY_DIRECTION_TX: return sun6i_dphy_tx_power_on(dphy); @@ -514,6 +567,11 @@ static int sun6i_dphy_power_off(struct phy *phy) regmap_write(dphy->regs, SUN6I_DPHY_ANA3_REG, 0); regmap_write(dphy->regs, SUN6I_DPHY_ANA4_REG, 0); =20 + if (phy->attrs.mode =3D=3D PHY_MODE_LVDS && dphy->variant->is_combo_dphy)= { + regmap_write(dphy->regs, SUN50I_COMBO_PHY_REG1, 0); + regmap_write(dphy->regs, SUN50I_COMBO_PHY_REG0, 0); + } + return 0; } =20 @@ -533,6 +591,7 @@ static const struct phy_ops sun6i_dphy_ops =3D { .configure =3D sun6i_dphy_configure, .power_on =3D sun6i_dphy_power_on, .power_off =3D sun6i_dphy_power_off, + .set_mode =3D sun6i_dphy_set_mode, .init =3D sun6i_dphy_init, .exit =3D sun6i_dphy_exit, }; @@ -619,6 +678,8 @@ static const struct sun6i_dphy_variant sun6i_a31_mipi_d= phy_variant =3D { =20 static const struct sun6i_dphy_variant sun50i_a100_mipi_dphy_variant =3D { .tx_power_on =3D sun50i_a100_mipi_dphy_tx_power_on, + .lvds_power_on =3D sun50i_a100_mipi_dphy_lvds_power_on, + .is_combo_dphy =3D true, }; =20 static const struct of_device_id sun6i_dphy_of_table[] =3D { --=20 2.25.1 From nobody Mon Feb 9 13:10:09 2026 Received: from s2.avantea.pl (s2.avantea.pl [46.242.128.95]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7CEC82139B0; Fri, 21 Feb 2025 16:40:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=46.242.128.95 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740156013; cv=none; b=OckEOL1NoUTjDhlIyczXfn13pnXFniXc3hoz/8mpl1nVxMmqVqHnh7oOUC0kmidi1VpU1Lddrx58t1SGDjWSqyUnjxmmQL4HtbNqiompkT//s7uUdv09wGUTs77II2b+x8ooAM7viifA0yRl/e4TBpQyg4INa/Yk8fp8vdJ5MvY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740156013; c=relaxed/simple; bh=NMsmeC5zTjZJ1Hso2G2RkLErT+oye4jJJeqv6TaydpA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=t+FzUaCnkNRHPFXVGt9t5Qbn+CeuPxtjXCbfAu7GZi3g8+cXCflesq/H6z4crwEojZseRqgh/9Q31/UJybABenB3qhEaX5Ic4tgSsHBl+t+DwHMpZOvRyQpvTied1lKKwu+g29DIluPW5TANfLz1O1XDtPBAiVzQWjj9s3E8EpM= ARC-Authentication-Results: i=1; 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bh=UFXO1Gy61HIc3X2s04g2rF4mqurOzi2/2JTsODv/dro=; b=1o8W83wHSBrDm/t1B7qCpi4ixz kf7OYIbWcpgCR+W1fnJIk9ILEvIsEbePlyNmxteQto38eQZK6X3bWzcIHM/uNLN/bnhwOwlEZ78Pn /Zac86Vl6IzLzK/YrbB8gywurgnIbab7Cu581QjuwUxEMpO9rKuVUdB4dSRULi8Vo+CYFWIH7cFFK nCxQaB55szc822dBf1LSfD8LYwZf7ackLHJsjLAkagUpwIdbm9rAxE3MyMp92QrVNeJll1F5SGzaW X2m0uBcUfIZTv4I0Ijn5OlcF7PBhwgI9esG8YF2zqsZ4B2v/UOE59YT0NI1fL1OIoNRK+3lgLWORV WZTju8dA==; Received: from [62.171.184.96] (helo=buildhost.contaboserver.net) by s2.avantea.pl with esmtpsa (TLS1.3) tls TLS_AES_256_GCM_SHA384 (Exim 4.96-58-g4e9ed49f8) (envelope-from ) id 1tlViv-00AOLX-0d; Fri, 21 Feb 2025 17:17:57 +0100 From: =?UTF-8?q?Kuba=20Szczodrzy=C5=84ski?= To: Maxime Ripard , Samuel Holland , Chen-Yu Tsai , Jernej Skrabec , Maarten Lankhorst , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: David Airlie , Simona Vetter , linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org Subject: [PATCH 2/5] drm/sun4i: Support LVDS using MIPI DSI combo D-PHY Date: Fri, 21 Feb 2025 17:17:48 +0100 Message-Id: <20250221161751.1278049-3-kuba@szczodrzynski.pl> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250221161751.1278049-1-kuba@szczodrzynski.pl> References: <20250221161751.1278049-1-kuba@szczodrzynski.pl> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Authenticated-Id: kuba@szczodrzynski.pl On Allwinner chips with a combo D-PHY, the TCON LCD0 should fetch it from device tree, in order to enable LVDS. Since the PHY also needs to be powered off to disable LVDS, add a function to the quirks. Signed-off-by: Kuba Szczodrzy=C5=84ski --- drivers/gpu/drm/sun4i/sun4i_tcon.c | 12 ++++++++++++ drivers/gpu/drm/sun4i/sun4i_tcon.h | 6 ++++++ 2 files changed, 18 insertions(+) diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun= 4i_tcon.c index 960e83c82..ccf335a61 100644 --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -183,6 +184,8 @@ static void sun4i_tcon_lvds_set_status(struct sun4i_tco= n *tcon, } else { regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG, SUN4I_TCON0_LVDS_IF_EN, 0); + if (tcon->quirks->disable_lvds_phy) + tcon->quirks->disable_lvds_phy(tcon, encoder); } } =20 @@ -1245,6 +1248,15 @@ static int sun4i_tcon_bind(struct device *dev, struc= t device *master, goto err_free_dclk; } =20 + if (tcon->quirks->has_combo_dphy) { + tcon->dphy =3D devm_phy_get(dev, "dphy"); + if (IS_ERR(tcon->dphy)) { + dev_err(dev, "Couldn't get the combo D-PHY\n"); + ret =3D PTR_ERR(tcon->dphy); + goto err_free_dclk; + } + } + if (tcon->quirks->has_channel_0) { /* * If we have an LVDS panel connected to the TCON, we should diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.h b/drivers/gpu/drm/sun4i/sun= 4i_tcon.h index fa23aa23f..b270d1a13 100644 --- a/drivers/gpu/drm/sun4i/sun4i_tcon.h +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.h @@ -239,6 +239,7 @@ struct sun4i_tcon_quirks { bool has_channel_0; /* a83t does not have channel 0 on second TCON */ bool has_channel_1; /* a33 does not have channel 1 */ bool has_lvds_alt; /* Does the LVDS clock have a parent other than the TC= ON clock? */ + bool has_combo_dphy; /* Is the D-PHY used for LVDS output? */ bool needs_de_be_mux; /* sun6i needs mux to select backend */ bool needs_edp_reset; /* a80 edp reset needed for tcon0 access */ bool supports_lvds; /* Does the TCON support an LVDS output? */ @@ -250,6 +251,8 @@ struct sun4i_tcon_quirks { /* handler for LVDS setup routine */ void (*setup_lvds_phy)(struct sun4i_tcon *tcon, const struct drm_encoder *encoder); + void (*disable_lvds_phy)(struct sun4i_tcon *tcon, + const struct drm_encoder *encoder); }; =20 struct sun4i_tcon { @@ -282,6 +285,9 @@ struct sun4i_tcon { /* Associated crtc */ struct sun4i_crtc *crtc; =20 + /* Associated D-PHY */ + struct phy *dphy; + int id; =20 /* TCON list management */ --=20 2.25.1 From nobody Mon Feb 9 13:10:09 2026 Received: from s2.avantea.pl (s2.avantea.pl [46.242.128.95]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D1C5521420D; Fri, 21 Feb 2025 16:40:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=46.242.128.95 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740156017; cv=none; b=WFDnaaw3y8faKyjGJ6Uh3s3XzDa56B/JBwqN31v1JDtKpVqqf4hDW80S07XXdgSR65eqnjSIYrD7G0m2d1RW+CFTpmbm399I3ECLrLpyfIUd/L9SHWo6ZB9o4gSnWrjWeFkZPSw5f8Gp95p0ow354ZB4r4aju+lz7c1B0raFi/A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740156017; c=relaxed/simple; bh=TES/SuY81HkKlCk4x2V0WYEnKObg3ukIt1CVKciqxW0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=F0H83O2Px/uLgJs52UtgB/mHisvdx/3ZzoK/QUfr3fQl9b3LsB5MFY/FZC36K/2RNqMgWiFMpYYvB/H6fQvlC0Un8eayNGQE8ixdWIpNWsxt9agpT8+LAKJ5yBBFaOgyB12yPYpVlG6sBxZGcabEXU7qex6EC5x3ZJpROA9ZbRE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=szczodrzynski.pl; spf=pass smtp.mailfrom=szczodrzynski.pl; dkim=pass (2048-bit key) header.d=szczodrzynski.pl header.i=@szczodrzynski.pl header.b=p1pGOIC5; arc=none smtp.client-ip=46.242.128.95 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=szczodrzynski.pl Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=szczodrzynski.pl Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=szczodrzynski.pl header.i=@szczodrzynski.pl header.b="p1pGOIC5" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=szczodrzynski.pl; s=x; h=Content-Transfer-Encoding:Content-Type: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender :Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help: List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=U2i+tFSML7sT+8AM5vIWnSdSP/UjJ3mmCMahXU8/Uc0=; b=p1pGOIC5KroF7U+KU+hMlEUo2p gChyrkqBaGtW4djBrZcHJhS7RQ5U87eV3gBR0dq7UttRIsAgWjI6xO3/nqnC4b+SKV8QeQEBlaB3C swS5I8XmqwD65u1uZ9rcwEblo7RAuCroiAnfp0t7tPZKL+1upBfmtIkjLuwF8ZS3GvYJaQ9jwfoN5 CCLk37otP528jmLS1hF5EZyU/apPvK46QKaH91zhQGFWYWoJi+yJyZaNvqPB6CudOEUmG2EMT+YR0 ErHfYDXNJIrtLZWcnMSLIQ7bghLo3J6Ot8WpQ1lEID/GBdBcllqj5ifmla+CDnOoy0piCwj3LFNtu 7/aU6zCQ==; Received: from [62.171.184.96] (helo=buildhost.contaboserver.net) by s2.avantea.pl with esmtpsa (TLS1.3) tls TLS_AES_256_GCM_SHA384 (Exim 4.96-58-g4e9ed49f8) (envelope-from ) id 1tlViv-00AOLX-34; Fri, 21 Feb 2025 17:17:58 +0100 From: =?UTF-8?q?Kuba=20Szczodrzy=C5=84ski?= To: Maxime Ripard , Samuel Holland , Chen-Yu Tsai , Jernej Skrabec , Maarten Lankhorst , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: David Airlie , Simona Vetter , linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org Subject: [PATCH 3/5] drm/sun4i: Enable LVDS output on sun20i D1s/T113 Date: Fri, 21 Feb 2025 17:17:49 +0100 Message-Id: <20250221161751.1278049-4-kuba@szczodrzynski.pl> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250221161751.1278049-1-kuba@szczodrzynski.pl> References: <20250221161751.1278049-1-kuba@szczodrzynski.pl> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Authenticated-Id: kuba@szczodrzynski.pl The Allwinner D1s/T113 needs to use the combo D-PHY to enable LVDS output. Enable LVDS support in the TCON and configure it using the PHY. Signed-off-by: Kuba Szczodrzy=C5=84ski --- drivers/gpu/drm/sun4i/sun4i_tcon.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun= 4i_tcon.c index ccf335a61..58230a552 100644 --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c @@ -171,6 +171,30 @@ static void sun6i_tcon_setup_lvds_phy(struct sun4i_tco= n *tcon, SUN6I_TCON0_LVDS_ANA0_EN_DRVD(val)); } =20 +static void sun20i_tcon_setup_lvds_dphy(struct sun4i_tcon *tcon, + const struct drm_encoder *encoder) +{ + union phy_configure_opts opts =3D { }; + + if (!tcon->quirks->has_combo_dphy || !tcon->dphy) + return; + + phy_init(tcon->dphy); + phy_set_mode(tcon->dphy, PHY_MODE_LVDS); + phy_configure(tcon->dphy, &opts); + phy_power_on(tcon->dphy); +} + +static void sun20i_tcon_disable_lvds_dphy(struct sun4i_tcon *tcon, + const struct drm_encoder *encoder) +{ + if (!tcon->quirks->has_combo_dphy || !tcon->dphy) + return; + + phy_power_off(tcon->dphy); + phy_exit(tcon->dphy); +} + static void sun4i_tcon_lvds_set_status(struct sun4i_tcon *tcon, const struct drm_encoder *encoder, bool enabled) @@ -1550,8 +1574,12 @@ static const struct sun4i_tcon_quirks sun9i_a80_tcon= _tv_quirks =3D { =20 static const struct sun4i_tcon_quirks sun20i_d1_lcd_quirks =3D { .has_channel_0 =3D true, + .has_combo_dphy =3D true, + .supports_lvds =3D true, .dclk_min_div =3D 1, .set_mux =3D sun8i_r40_tcon_tv_set_mux, + .setup_lvds_phy =3D sun20i_tcon_setup_lvds_dphy, + .disable_lvds_phy =3D sun20i_tcon_disable_lvds_dphy, }; =20 /* sun4i_drv uses this list to check if a device node is a TCON */ --=20 2.25.1 From nobody Mon Feb 9 13:10:09 2026 Received: from s2.avantea.pl (s2.avantea.pl [46.242.128.95]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E98CB21506B; Fri, 21 Feb 2025 16:40:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=46.242.128.95 ARC-Seal: i=1; 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Received: from [62.171.184.96] (helo=buildhost.contaboserver.net) by s2.avantea.pl with esmtpsa (TLS1.3) tls TLS_AES_256_GCM_SHA384 (Exim 4.96-58-g4e9ed49f8) (envelope-from ) id 1tlViw-00AOLX-2K; Fri, 21 Feb 2025 17:17:58 +0100 From: =?UTF-8?q?Kuba=20Szczodrzy=C5=84ski?= To: Maxime Ripard , Samuel Holland , Chen-Yu Tsai , Jernej Skrabec , Maarten Lankhorst , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: David Airlie , Simona Vetter , linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org Subject: [PATCH 4/5] riscv: dts: allwinner: d1s-t113: Add D-PHY to TCON LCD0 Date: Fri, 21 Feb 2025 17:17:50 +0100 Message-Id: <20250221161751.1278049-5-kuba@szczodrzynski.pl> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250221161751.1278049-1-kuba@szczodrzynski.pl> References: <20250221161751.1278049-1-kuba@szczodrzynski.pl> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Authenticated-Id: kuba@szczodrzynski.pl The sun4i TCON needs a reference to the D-PHY in order to support LVDS on Allwinner D1s/T113. Signed-off-by: Kuba Szczodrzy=C5=84ski --- arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv= /boot/dts/allwinner/sunxi-d1s-t113.dtsi index e4175adb0..d241ba306 100644 --- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi @@ -828,6 +828,8 @@ tcon_lcd0: lcd-controller@5461000 { resets =3D <&ccu RST_BUS_TCON_LCD0>, <&ccu RST_BUS_LVDS0>; reset-names =3D "lcd", "lvds"; + phys =3D <&dphy>; + phy-names =3D "dphy"; #clock-cells =3D <0>; =20 ports { --=20 2.25.1 From nobody Mon Feb 9 13:10:09 2026 Received: from s2.avantea.pl (s2.avantea.pl [46.242.128.95]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A80AB2F60A7; Sun, 16 Nov 2025 13:25:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=46.242.128.95 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763299522; cv=none; b=muEdWXgApfS1cisldJJTlD4Gu46wJsO0LV1SeIzd0TlAoGa2d3LvaOfca/aLhenk2EHCM+L7gJt6RZl5meLTr/KsO+Iasf4lvUKLErjAk1F7L1yo6Ri2dJ2ZB/WkXqG36P7SsXaH6tPOq1eK2pmHWiA+/v514A1pBDKOw7AaWy4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763299522; c=relaxed/simple; bh=g47VNxOuIRVfIjJ9Gd6MyaohN5b5SV9VKZlky0fDxHc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=kyQEpnqFAehmwKAtXODhkcnpN3krX+EPYS5dTm0RMxHAox4dTEbBOXjUKmzAWGkCQV4xVwbg1Skl+EnfrdXTVwEuo5gVU867IfOE3fKnRuPr9mE2IVCm6OvvU+iwES9/9Yy5DgkwgarJBdaoptegH8oeBT7KF7nlLZAbkqBpAcc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=szczodrzynski.pl; spf=pass smtp.mailfrom=szczodrzynski.pl; dkim=pass (2048-bit key) header.d=szczodrzynski.pl header.i=@szczodrzynski.pl header.b=oqYIW28M; arc=none smtp.client-ip=46.242.128.95 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=szczodrzynski.pl Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=szczodrzynski.pl Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=szczodrzynski.pl header.i=@szczodrzynski.pl header.b="oqYIW28M" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=szczodrzynski.pl; s=x; h=Content-Transfer-Encoding:Content-Type: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender :Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help: List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=BPO9NrD7t7ozHNmv9SwKBa5YjnO0HgIRT0temEkfh70=; b=oqYIW28MTYchaus5P4hPdqBMcw 8w9RZoiGHzBso3Fy8hSBWffJ6uTQq8OC61xOZXDkdr8db5Z3qY3ZKZVVjkv9hyHc0lTpmfM9zR3I/ dD+Lx1poqOVYaSfouhdkmSymdGihzeTgYPajNIlem8qvtBZ7J5FN9nL1B6p1d7E5tUPxF2kUoucox U9vjnQYVSGknlAKuGjUMHnlw0e4khAKvVLjhJKBDojgl3mmMQgVbTajBVPmfUeAmSt9gMnNGH0dxH apBQeVCOQbM2ByyMp6Q5t2vD0DS/M8OXoZFAnZ+AfLCtD9LJt2MQSnh3O1rbQecCAzl03U+pvtNjO lPlC6zwA==; Received: from [62.171.184.96] (helo=buildhost.contaboserver.net) by s2.avantea.pl with esmtpsa (TLS1.3) tls TLS_AES_256_GCM_SHA384 (Exim 4.98.1) (envelope-from ) id 1vKckk-0000000FWTF-2WDU; Sun, 16 Nov 2025 14:25:14 +0100 From: =?UTF-8?q?Kuba=20Szczodrzy=C5=84ski?= To: Maxime Ripard , Samuel Holland , Chen-Yu Tsai , Jernej Skrabec , Maarten Lankhorst , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: David Airlie , Simona Vetter , linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, parthiban@linumiz.com, paulk@sys-base.io Subject: [PATCH v2 5/6] riscv: dts: allwinner: d1s-t113: Add D-PHY to TCON LCD0 Date: Sun, 16 Nov 2025 14:25:02 +0100 Message-Id: <20251116132503.441015-1-kuba@szczodrzynski.pl> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250221161751.1278049-1-kuba@szczodrzynski.pl> References: <20250221161751.1278049-1-kuba@szczodrzynski.pl> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Authenticated-Id: kuba@szczodrzynski.pl The sun4i TCON needs a reference to the D-PHY in order to support LVDS on Allwinner D1s/T113. Add phys and phy-names to sunxi-d1s-t113 common device tree. Signed-off-by: Kuba Szczodrzy=C5=84ski --- arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv= /boot/dts/allwinner/sunxi-d1s-t113.dtsi index 63e252b44..78aa61607 100644 --- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi @@ -876,6 +876,8 @@ tcon_lcd0: lcd-controller@5461000 { resets =3D <&ccu RST_BUS_TCON_LCD0>, <&ccu RST_BUS_LVDS0>; reset-names =3D "lcd", "lvds"; + phys =3D <&dphy>; + phy-names =3D "combo-phy"; #clock-cells =3D <0>; =20 ports { --=20 2.25.1 From nobody Mon Feb 9 13:10:09 2026 Received: from s2.avantea.pl (s2.avantea.pl [46.242.128.95]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 82BDD1EBA14; Fri, 21 Feb 2025 16:40:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=46.242.128.95 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740156009; cv=none; b=oYl0vjFDdPIgd51OsuzShMcXBLF/P9Yyzt337Xmf4Q7rjrvmTny8LSVu8HhaJiVD+78ihqehQpX3xYcPyg5bT5ovEgiyFaNzkrOLPxs9JmqAR74/wgYaLWUhm9ykI1OrFyjyLmTv2koJPEzTBRuJxJ1NZmweKi4eVSJKJupmq/U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740156009; c=relaxed/simple; bh=0ZMDRFPUNe4qk8G8SolkBVr1G4m1qg1ow0otgDRhPwA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=fde2tVnxSz1bMmpmWnkh26E4FA9W5YcbTCKQCP6Aa/50E7k8qL1QFv2/YET4TtWHYuS3ZTtrt+WyCtJzubQQV9r2+HMCsmAT5IyuFIwJodiHCapxulao3FKUVAUVGI/PhatI4cQUt7CuXdZVHjS2Yq+8f4m37fCtgd4/1auMx94= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=szczodrzynski.pl; spf=pass smtp.mailfrom=szczodrzynski.pl; dkim=pass (2048-bit key) header.d=szczodrzynski.pl header.i=@szczodrzynski.pl header.b=CMNzlDdk; arc=none smtp.client-ip=46.242.128.95 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=szczodrzynski.pl Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=szczodrzynski.pl Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=szczodrzynski.pl header.i=@szczodrzynski.pl header.b="CMNzlDdk" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=szczodrzynski.pl; s=x; h=Content-Transfer-Encoding:Content-Type: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender :Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help: List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=w2E197Qc+tMzoaRduX1xKII3x7kGR5ATZ73uNFSwZtQ=; b=CMNzlDdkHQ6mojLXa6tNiP/3VC RkIZGgKGLCLwEE4kPiGTssFxkaN0xfA7iu5WpmszAXMImsPodll8V0+9AC8TDn4YfEsc7Wp+sVXyP bw5eGzs6xhuk9T8yiqzR2bKgTIf9mcr2aydxbSSuy9e5FQlKv/eQgku1xjrcD+KHsyrXwB0RX8aOF +yPQyPm+M+bXvN+Ih7QHFFDOLh1/NMvVhCBjuWb8/Mr9AHv7Icatpoe8wI8gVs18Vru9xNko2ePe8 ezPts3Z/Y0LIeJ7RWEUIpJ9F4dU8HijLXrwRyvvCShp5JHvXij14iwDn5G9u79LBlPQChA6Vp66ID +GldAbUw==; Received: from [62.171.184.96] (helo=buildhost.contaboserver.net) by s2.avantea.pl with esmtpsa (TLS1.3) tls TLS_AES_256_GCM_SHA384 (Exim 4.96-58-g4e9ed49f8) (envelope-from ) id 1tlVix-00AOLX-1V; Fri, 21 Feb 2025 17:17:59 +0100 From: =?UTF-8?q?Kuba=20Szczodrzy=C5=84ski?= To: Maxime Ripard , Samuel Holland , Chen-Yu Tsai , Jernej Skrabec , Maarten Lankhorst , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: David Airlie , Simona Vetter , linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org Subject: [PATCH 5/5] riscv: dts: allwinner: d1s-t113: Add LVDS0 pins Date: Fri, 21 Feb 2025 17:17:51 +0100 Message-Id: <20250221161751.1278049-6-kuba@szczodrzynski.pl> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250221161751.1278049-1-kuba@szczodrzynski.pl> References: <20250221161751.1278049-1-kuba@szczodrzynski.pl> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Authenticated-Id: kuba@szczodrzynski.pl Add LVDS pins to the PIO since it's now supported on D1s/T113. Signed-off-by: Kuba Szczodrzy=C5=84ski --- arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv= /boot/dts/allwinner/sunxi-d1s-t113.dtsi index d241ba306..174b6d8f9 100644 --- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi @@ -78,6 +78,15 @@ dsi_4lane_pins: dsi-4lane-pins { function =3D "dsi"; }; =20 + /omit-if-no-ref/ + lvds0_pins: lvds0-pins { + pins =3D "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", + "PD6", "PD7", "PD8", "PD9"; + function =3D "lvds0"; + drive-strength =3D <30>; + bias-disable; + }; + /omit-if-no-ref/ lcd_rgb666_pins: lcd-rgb666-pins { pins =3D "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", --=20 2.25.1