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charset="utf-8" From: Lad Prabhakar Prepare for adding support for RZ/G3E and RZ/V2HP SoCs, which have a CRU-IP that is mostly identical to RZ/G2L but with different register offsets and additional registers. Introduce a flexible register mapping mechanism to handle these variations. Define the `rzg2l_cru_info` structure to store register mappings and pass it as part of the OF match data. Update the read/write functions to use indexed register offsets from `rzg2l_cru_info`, ensuring compatibility across different SoC variants. Signed-off-by: Lad Prabhakar Signed-off-by: Tommaso Merciai --- .../platform/renesas/rzg2l-cru/rzg2l-core.c | 46 ++++++++++++- .../renesas/rzg2l-cru/rzg2l-cru-regs.h | 65 ++++++++++--------- .../platform/renesas/rzg2l-cru/rzg2l-cru.h | 4 ++ .../platform/renesas/rzg2l-cru/rzg2l-video.c | 12 ++-- 4 files changed, 92 insertions(+), 35 deletions(-) diff --git a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-core.c b/driver= s/media/platform/renesas/rzg2l-cru/rzg2l-core.c index eed9d2bd0841..abc2a979833a 100644 --- a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-core.c +++ b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-core.c @@ -22,6 +22,7 @@ #include =20 #include "rzg2l-cru.h" +#include "rzg2l-cru-regs.h" =20 static inline struct rzg2l_cru_dev *notifier_to_cru(struct v4l2_async_noti= fier *n) { @@ -269,6 +270,9 @@ static int rzg2l_cru_probe(struct platform_device *pdev) =20 cru->dev =3D dev; cru->info =3D of_device_get_match_data(dev); + if (!cru->info) + return dev_err_probe(dev, -EINVAL, + "Failed to get OF match data\n"); =20 irq =3D platform_get_irq(pdev, 0); if (irq < 0) @@ -317,8 +321,48 @@ static void rzg2l_cru_remove(struct platform_device *p= dev) rzg2l_cru_dma_unregister(cru); } =20 +static const u16 rzg2l_cru_regs[] =3D { + [CRUnCTRL] =3D 0x0, + [CRUnIE] =3D 0x4, + [CRUnINTS] =3D 0x8, + [CRUnRST] =3D 0xc, + [AMnMB1ADDRL] =3D 0x100, + [AMnMB1ADDRH] =3D 0x104, + [AMnMB2ADDRL] =3D 0x108, + [AMnMB2ADDRH] =3D 0x10c, + [AMnMB3ADDRL] =3D 0x110, + [AMnMB3ADDRH] =3D 0x114, + [AMnMB4ADDRL] =3D 0x118, + [AMnMB4ADDRH] =3D 0x11c, + [AMnMB5ADDRL] =3D 0x120, + [AMnMB5ADDRH] =3D 0x124, + [AMnMB6ADDRL] =3D 0x128, + [AMnMB6ADDRH] =3D 0x12c, + [AMnMB7ADDRL] =3D 0x130, + [AMnMB7ADDRH] =3D 0x134, + [AMnMB8ADDRL] =3D 0x138, + [AMnMB8ADDRH] =3D 0x13c, + [AMnMBVALID] =3D 0x148, + [AMnMBS] =3D 0x14c, + [AMnAXIATTR] =3D 0x158, + [AMnFIFOPNTR] =3D 0x168, + [AMnAXISTP] =3D 0x174, + [AMnAXISTPACK] =3D 0x178, + [ICnEN] =3D 0x200, + [ICnMC] =3D 0x208, + [ICnMS] =3D 0x254, + [ICnDMR] =3D 0x26c, +}; + +static const struct rzg2l_cru_info rzgl2_cru_info =3D { + .regs =3D rzg2l_cru_regs, +}; + static const struct of_device_id rzg2l_cru_of_id_table[] =3D { - { .compatible =3D "renesas,rzg2l-cru", }, + { + .compatible =3D "renesas,rzg2l-cru", + .data =3D &rzgl2_cru_info, + }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, rzg2l_cru_of_id_table); diff --git a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-cru-regs.h b/dr= ivers/media/platform/renesas/rzg2l-cru/rzg2l-cru-regs.h index 1c9f22118a5d..82920db7134e 100644 --- a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-cru-regs.h +++ b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-cru-regs.h @@ -10,71 +10,76 @@ =20 /* HW CRU Registers Definition */ =20 -/* CRU Control Register */ -#define CRUnCTRL 0x0 #define CRUnCTRL_VINSEL(x) ((x) << 0) =20 -/* CRU Interrupt Enable Register */ -#define CRUnIE 0x4 #define CRUnIE_EFE BIT(17) =20 -/* CRU Interrupt Status Register */ -#define CRUnINTS 0x8 #define CRUnINTS_SFS BIT(16) =20 -/* CRU Reset Register */ -#define CRUnRST 0xc #define CRUnRST_VRESETN BIT(0) =20 /* Memory Bank Base Address (Lower) Register for CRU Image Data */ -#define AMnMBxADDRL(x) (0x100 + ((x) * 8)) +#define AMnMBxADDRL(base, x) ((base) + (x) * 2) =20 /* Memory Bank Base Address (Higher) Register for CRU Image Data */ -#define AMnMBxADDRH(x) (0x104 + ((x) * 8)) +#define AMnMBxADDRH(base, x) AMnMBxADDRL(base, x) =20 -/* Memory Bank Enable Register for CRU Image Data */ -#define AMnMBVALID 0x148 #define AMnMBVALID_MBVALID(x) GENMASK(x, 0) =20 -/* Memory Bank Status Register for CRU Image Data */ -#define AMnMBS 0x14c #define AMnMBS_MBSTS 0x7 =20 -/* AXI Master Transfer Setting Register for CRU Image Data */ -#define AMnAXIATTR 0x158 #define AMnAXIATTR_AXILEN_MASK GENMASK(3, 0) #define AMnAXIATTR_AXILEN (0xf) =20 -/* AXI Master FIFO Pointer Register for CRU Image Data */ -#define AMnFIFOPNTR 0x168 #define AMnFIFOPNTR_FIFOWPNTR GENMASK(7, 0) #define AMnFIFOPNTR_FIFORPNTR_Y GENMASK(23, 16) =20 -/* AXI Master Transfer Stop Register for CRU Image Data */ -#define AMnAXISTP 0x174 #define AMnAXISTP_AXI_STOP BIT(0) =20 -/* AXI Master Transfer Stop Status Register for CRU Image Data */ -#define AMnAXISTPACK 0x178 #define AMnAXISTPACK_AXI_STOP_ACK BIT(0) =20 -/* CRU Image Processing Enable Register */ -#define ICnEN 0x200 #define ICnEN_ICEN BIT(0) =20 -/* CRU Image Processing Main Control Register */ -#define ICnMC 0x208 #define ICnMC_CSCTHR BIT(5) #define ICnMC_INF(x) ((x) << 16) #define ICnMC_VCSEL(x) ((x) << 22) #define ICnMC_INF_MASK GENMASK(21, 16) =20 -/* CRU Module Status Register */ -#define ICnMS 0x254 #define ICnMS_IA BIT(2) =20 -/* CRU Data Output Mode Register */ -#define ICnDMR 0x26c #define ICnDMR_YCMODE_UYVY (1 << 4) =20 +enum rzg2l_cru_common_regs { + CRUnCTRL, /* CRU Control */ + CRUnIE, /* CRU Interrupt Enable */ + CRUnINTS, /* CRU Interrupt Status */ + CRUnRST, /* CRU Reset */ + AMnMB1ADDRL, /* Bank 1 Address (Lower) for CRU Image Data */ + AMnMB1ADDRH, /* Bank 1 Address (Higher) for CRU Image Data */ + AMnMB2ADDRL, /* Bank 2 Address (Lower) for CRU Image Data */ + AMnMB2ADDRH, /* Bank 2 Address (Higher) for CRU Image Data */ + AMnMB3ADDRL, /* Bank 3 Address (Lower) for CRU Image Data */ + AMnMB3ADDRH, /* Bank 3 Address (Higher) for CRU Image Data */ + AMnMB4ADDRL, /* Bank 4 Address (Lower) for CRU Image Data */ + AMnMB4ADDRH, /* Bank 4 Address (Higher) for CRU Image Data */ + AMnMB5ADDRL, /* Bank 5 Address (Lower) for CRU Image Data */ + AMnMB5ADDRH, /* Bank 5 Address (Higher) for CRU Image Data */ + AMnMB6ADDRL, /* Bank 6 Address (Lower) for CRU Image Data */ + AMnMB6ADDRH, /* Bank 6 Address (Higher) for CRU Image Data */ + AMnMB7ADDRL, /* Bank 7 Address (Lower) for CRU Image Data */ + AMnMB7ADDRH, /* Bank 7 Address (Higher) for CRU Image Data */ + AMnMB8ADDRL, /* Bank 8 Address (Lower) for CRU Image Data */ + AMnMB8ADDRH, /* Bank 8 Address (Higher) for CRU Image Data */ + AMnMBVALID, /* Memory Bank Enable for CRU Image Data */ + AMnMBS, /* Memory Bank Status for CRU Image Data */ + AMnAXIATTR, /* AXI Master Transfer Setting Register for CRU Image Data */ + AMnFIFOPNTR, /* AXI Master FIFO Pointer for CRU Image Data */ + AMnAXISTP, /* AXI Master Transfer Stop for CRU Image Data */ + AMnAXISTPACK, /* AXI Master Transfer Stop Status for CRU Image Data */ + ICnEN, /* CRU Image Processing Enable */ + ICnMC, /* CRU Image Processing Main Control */ + ICnMS, /* CRU Module Status */ + ICnDMR, /* CRU Data Output Mode */ +}; + #endif /* __RZG2L_CRU_REGS_H__ */ diff --git a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-cru.h b/drivers= /media/platform/renesas/rzg2l-cru/rzg2l-cru.h index 8b898ce05b84..00c3f7458e20 100644 --- a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-cru.h +++ b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-cru.h @@ -80,6 +80,10 @@ struct rzg2l_cru_ip_format { bool yuv; }; =20 +struct rzg2l_cru_info { + const u16 *regs; +}; + /** * struct rzg2l_cru_dev - Renesas CRU device structure * @dev: (OF) device diff --git a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-video.c b/drive= rs/media/platform/renesas/rzg2l-cru/rzg2l-video.c index cd69c8a686d3..f25fd9b35c55 100644 --- a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-video.c +++ b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-video.c @@ -44,12 +44,16 @@ struct rzg2l_cru_buffer { */ static void rzg2l_cru_write(struct rzg2l_cru_dev *cru, u32 offset, u32 val= ue) { - iowrite32(value, cru->base + offset); + const u16 *regs =3D cru->info->regs; + + iowrite32(value, cru->base + regs[offset]); } =20 static u32 rzg2l_cru_read(struct rzg2l_cru_dev *cru, u32 offset) { - return ioread32(cru->base + offset); + const u16 *regs =3D cru->info->regs; + + return ioread32(cru->base + regs[offset]); } =20 /* Need to hold qlock before calling */ @@ -132,8 +136,8 @@ static void rzg2l_cru_set_slot_addr(struct rzg2l_cru_de= v *cru, return; =20 /* Currently, we just use the buffer in 32 bits address */ - rzg2l_cru_write(cru, AMnMBxADDRL(slot), addr); - rzg2l_cru_write(cru, AMnMBxADDRH(slot), 0); + rzg2l_cru_write(cru, AMnMBxADDRL(AMnMB1ADDRL, slot), addr); + rzg2l_cru_write(cru, AMnMBxADDRH(AMnMB1ADDRH, slot), 0); } =20 /* --=20 2.34.1