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[2001:14ba:a0c3:3a00::782]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-30a2be45876sm16021071fa.68.2025.02.20.19.06.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Feb 2025 19:06:06 -0800 (PST) From: Dmitry Baryshkov Date: Fri, 21 Feb 2025 05:06:00 +0200 Subject: [PATCH v2 1/6] dt-bindings: PCI: qcom-ep: describe optional IOMMU Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250221-sar2130p-pci-v2-1-cc87590ffbeb@linaro.org> References: <20250221-sar2130p-pci-v2-0-cc87590ffbeb@linaro.org> In-Reply-To: <20250221-sar2130p-pci-v2-0-cc87590ffbeb@linaro.org> To: Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Mrinmay Sarkar , Bjorn Andersson , Konrad Dybcio Cc: =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1332; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=h41p5OP+JGUWnkefKPRuMJP7onFPK2xv7UsIeCTWeA0=; b=owEBbQKS/ZANAwAKARTbcu2+gGW4AcsmYgBnt+2ZJ1d2rnD4QvueIoK3bZoOBqEM3ytwcD+Rk feHNpdrg/mJAjMEAAEKAB0WIQRdB85SOKWMgfgVe+4U23LtvoBluAUCZ7ftmQAKCRAU23LtvoBl uPghD/9cbfOizPzPViaH53MjmsJG+AMwDka8bh0Ol5Ah/3WZi3m2G9pb/VIEW2UfXCCI5vOq2J1 FlrsOGw0sgnjgDQZDptaXxutCri2EHVAl7OoXIT1Ghg/OoMgyCrAlEEJDNJjIzVdHMm2wX1Dpel dRK453wZiEbTV11pThtkcZTGU0A139G/AqeaHfEM1kyBqNG4o0jCKFq3ORSEl/j+b004CQh60sf pXc9AbjPGMB0RycngkK9txFg/MHNAWFsK4YUyodcnIgmOegqAt279r4fiUup5UnQ7+a0ASNn0cQ ALI429oQB4G6KO2oNJz5E6hmBigdlklfHG2E8TQbPK/hYW9H8lEG34qtPozt7fWbJUJq5Ll+u6y lb5LLTF5YQaredQemJjlY2usB52eEcEdvlZ3KwGc5rQyl0M7hXEB16DvgaLWlDPJf03m8ygR9MK jq66RRblrrTyovlWlMAcihjL16u1vFQ33hdJ2plQ3tPt7EHwn8J/lbqqFuXuBf4b0obMkKzRXgc KDRBMc8L7kO1Ac2H3au80EkiXZBGDO00Zv9a0dcsqqh5bXashm1b4ZREUdTmtBnPuGyeNi05eJk fQcgKnJTEkpL9VO4FHyCyM9MoU5mxT3nz8bkrAnYg3U1OFFeUYV1D70/89CyKeMTSH0QVURgH5W saFTFxbhjkq6bDA== X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Some of Qualcomm platforms have an IOMMU unit between the PCIe IP and DDR. Changethe schema in order to allow specifying the IOMMU. Fixes: 9d3d5e75f31c ("dt-bindings: PCI: qcom-ep: Add support for SA8775P So= C") Signed-off-by: Dmitry Baryshkov --- Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml | 17 +++++++++++++= ++++ 1 file changed, 17 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Docu= mentation/devicetree/bindings/pci/qcom,pcie-ep.yaml index 1226ee5d08d1ae909b07b0d78014618c4c74e9a8..800accdf5947e7178ad80f0759c= f53111be1a814 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml @@ -75,6 +75,9 @@ properties: - const: doorbell - const: dma =20 + iommus: + maxItems: 1 + reset-gpios: description: GPIO used as PERST# input signal maxItems: 1 @@ -233,6 +236,20 @@ allOf: minItems: 3 maxItems: 3 =20 + - if: + properties: + compatible: + contains: + const: qcom,sdx55-pcie-ep + then: + properties: + iommus: + false + + else: + required: + - iommus + unevaluatedProperties: false =20 examples: --=20 2.39.5 From nobody Mon Feb 9 06:45:02 2026 Received: from mail-lf1-f52.google.com (mail-lf1-f52.google.com [209.85.167.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6F9EF1D5CC2 for ; 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[2001:14ba:a0c3:3a00::782]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-30a2be45876sm16021071fa.68.2025.02.20.19.06.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Feb 2025 19:06:09 -0800 (PST) From: Dmitry Baryshkov Date: Fri, 21 Feb 2025 05:06:01 +0200 Subject: [PATCH v2 2/6] dt-bindings: PCI: qcom-ep: enable DMA for SM8450 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250221-sar2130p-pci-v2-2-cc87590ffbeb@linaro.org> References: <20250221-sar2130p-pci-v2-0-cc87590ffbeb@linaro.org> In-Reply-To: <20250221-sar2130p-pci-v2-0-cc87590ffbeb@linaro.org> To: Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Mrinmay Sarkar , Bjorn Andersson , Konrad Dybcio Cc: =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1595; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=lb3UDfByEeVlM9MYXJhgnTQM/WREpWu1N/uL89//nZ0=; b=owEBbQKS/ZANAwAKARTbcu2+gGW4AcsmYgBnt+2Zwhe9h8wd6aEzObnZ0j8f+L8uZ2eYDZcVo 2fuM8LfTaSJAjMEAAEKAB0WIQRdB85SOKWMgfgVe+4U23LtvoBluAUCZ7ftmQAKCRAU23LtvoBl uJu+D/9UIjc3mwk+X9zmhQJ1LDmsX1Mdtf/JJLr41qllYHMnncZOrzGvfFq6y4D+G3uKWbdWIfO wNlt0N+wjpVlrPvfc1LoppJxsQpnHSC2AjAPOFQahohtI9OvUK96/sEFD9h2lhA8Rt5Zj/2qkkQ /mSYlqU+W/aYkA1msPS2zMqA7mSyFBBq60XBNMbdSrLPvABp2pztZJpWoNqMZI9bEi1yriptGa5 mEKy2AJRMG/jqq1C9QicN49cm8JIV5pC3oexzvksZzDgnnquHTMlVlh/LbSXVxJgE+GCaU7gbjs 85/Ei8ryyT4OjufhqyTvKsNsX9yYHY1tykkvGnlXzr5iZWBule463rprUS27qnqjUcP/N/v75vd A4lvkzRScYDSeHKaW2uIk14rptPV+UhOk5xftpwl+DxiuxxVkrFf6UTnqL0/Y6O9qVqnEnj/Umv StPYPLjlc8qDMNuRxoMb3PK7aHlQU7O6KMQh1U44aWPkpDW1kOqkXXIMxYs9uctJHWtk/StWbRv vEkz6FcHjzOPYKOzOM6xeOZpGb48zakskoItVTWEgZAb0MPb9ObvpwxtMpvSsqKVIyIFzYdJYtp hmxU79BWXMn3Qdon8nA0XQxOsKsRBYGjYOeHMFLLXfA3FCsp1s/r0FqNliesigAXnzTuxkwdh5I RzqbGPZ/rBOwCWA== X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Qualcomm SM8450 platform can (and should) be using DMA for the PCIe EP transfers. Extend the MMIO regions and interrupts in order to acommodate for the DMA resources. Upstream DT doesn't provide support for the EP mode of the PCIe controller, so while this is an ABI break, it doesn't break any of the supported platforms. Fixes: 63e445b746aa ("dt-bindings: PCI: qcom-ep: Add support for SM8450 SoC= ") Reviewed-by: Manivannan Sadhasivam Signed-off-by: Dmitry Baryshkov --- Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Docu= mentation/devicetree/bindings/pci/qcom,pcie-ep.yaml index 800accdf5947e7178ad80f0759cf53111be1a814..460191fc4ff1b64206bce89e15c= e38e59c112ba6 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml @@ -173,9 +173,9 @@ allOf: then: properties: reg: - maxItems: 6 + maxItems: 7 reg-names: - maxItems: 6 + maxItems: 7 clocks: items: - description: PCIe Auxiliary clock @@ -197,9 +197,9 @@ allOf: - const: ddrss_sf_tbu - const: aggre_noc_axi interrupts: - maxItems: 2 + maxItems: 3 interrupt-names: - maxItems: 2 + maxItems: 3 =20 - if: properties: --=20 2.39.5 From nobody Mon Feb 9 06:45:02 2026 Received: from mail-lj1-f178.google.com (mail-lj1-f178.google.com [209.85.208.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E44E61D9688 for ; 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[2001:14ba:a0c3:3a00::782]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-30a2be45876sm16021071fa.68.2025.02.20.19.06.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Feb 2025 19:06:11 -0800 (PST) From: Dmitry Baryshkov Date: Fri, 21 Feb 2025 05:06:02 +0200 Subject: [PATCH v2 3/6] dt-bindings: PCI: qcom-ep: add SAR2130P compatible Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250221-sar2130p-pci-v2-3-cc87590ffbeb@linaro.org> References: <20250221-sar2130p-pci-v2-0-cc87590ffbeb@linaro.org> In-Reply-To: <20250221-sar2130p-pci-v2-0-cc87590ffbeb@linaro.org> To: Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Mrinmay Sarkar , Bjorn Andersson , Konrad Dybcio Cc: =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2656; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=SXeEbK5yXT+z0ytiJDbxKyhHdrBTsXe3P9N1F7xf4BM=; b=owEBbQKS/ZANAwAKARTbcu2+gGW4AcsmYgBnt+2aKQj+ktotPagVyE9Cku3l77SmU3n1J0Dsr gQdkbOorDWJAjMEAAEKAB0WIQRdB85SOKWMgfgVe+4U23LtvoBluAUCZ7ftmgAKCRAU23LtvoBl uGoJD/0QrpPH8bgdU/0dHSGPRlgoYLL10yIe+EF6bUr0qbjM4y7LT/C1/iJJUlfs35OaSWGBeOJ yLA7R/MapdHxYWmlatzGOAlg9uJ9BiHSzG1c10jdouehNEYUbYrqtgzcrQO/dhqljduWLezZt2d 3Airv+GZKxJcnp0IN91+40lSu6GBpRQOhrrzYva6Xmd/x+pV68ZTPoPY2hkKy1ZmCTPn7WDj59T 1Km1X4GLrSA6acN49h4wl3CFut/dydhv3C2+jL/FJQ9GPzOR5cJiYTjl10/NwnLtlEKiaXYNxRJ 6hdaSCqmVsPp5Zv3AJvp2i32PwKOUgfqpYFmKg8tw7mSfFKDkvmnvqZrS/WXmYb9b6T0VStJPfm JacKyi3wa8UbLcQ9YOLCZnFyV8L1bRdlS9S8SPqch8on4LZJaJQgpdV8+PEhZRweOm151SRSJWc SJMz57IhtU+PJg7wNRuiaMx0CRHmtyJ7StRA+OUE3R8OJpNQz9/Elx4NU7mjplz7cNdQ6mFmr+7 DzYx4GWT4yn4kZjzRs/rscKZW+eRh0/cL2Sjz5SI4C+D0cGxS2D+dr6muoED6gzeIc/ikKbMOOT ns3BRhGtIQaeO/eA0ebvacuUNl0+fXHfBkkvHPesCG1HkMNBOQbPS1eNllyYJazPKoX7HnXASei NJsknxv+P6W2ARQ== X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Add support for using the PCI controller in the endpoint mode on the SAR2130P platform. It is impossible to use fallback compatible to any other platform since SAR2130P uses slightly different set of clocks. Reviewed-by: Manivannan Sadhasivam Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/pci/qcom,pcie-ep.yaml | 44 ++++++++++++++++++= +++- 1 file changed, 42 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Docu= mentation/devicetree/bindings/pci/qcom,pcie-ep.yaml index 460191fc4ff1b64206bce89e15ce38e59c112ba6..6e516589f0edb4dfec78f9ff549= 3c06ee25418f0 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml @@ -14,6 +14,7 @@ properties: oneOf: - enum: - qcom,sa8775p-pcie-ep + - qcom,sar2130p-pcie-ep - qcom,sdx55-pcie-ep - qcom,sm8450-pcie-ep - items: @@ -44,11 +45,11 @@ properties: =20 clocks: minItems: 5 - maxItems: 8 + maxItems: 9 =20 clock-names: minItems: 5 - maxItems: 8 + maxItems: 9 =20 qcom,perst-regs: description: Reference to a syscon representing TCSR followed by the t= wo @@ -129,6 +130,45 @@ required: =20 allOf: - $ref: pci-ep.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,sar2130p-pcie-ep + then: + properties: + reg: + maxItems: 7 + reg-names: + maxItems: 7 + clocks: + items: + - description: PCIe Auxiliary clock + - description: PCIe CFG AHB clock + - description: PCIe Master AXI clock + - description: PCIe Slave AXI clock + - description: PCIe Slave Q2A AXI clock + - description: PCIe DDRSS SF TBU clock + - description: PCIe AGGRE NOC AXI clock + - description: PCIe CFG NOC AXI clock + - description: PCIe QMIP AHB clock + clock-names: + items: + - const: aux + - const: cfg + - const: bus_master + - const: bus_slave + - const: slave_q2a + - const: ddrss_sf_tbu + - const: aggre_noc_axi + - const: cnoc_sf_axi + - const: qmip_pcie_ahb + interrupts: + maxItems: 3 + interrupt-names: + maxItems: 3 + - if: properties: compatible: --=20 2.39.5 From nobody Mon Feb 9 06:45:02 2026 Received: from mail-lj1-f178.google.com (mail-lj1-f178.google.com [209.85.208.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 277841E7C0B for ; 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[2001:14ba:a0c3:3a00::782]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-30a2be45876sm16021071fa.68.2025.02.20.19.06.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Feb 2025 19:06:14 -0800 (PST) From: Dmitry Baryshkov Date: Fri, 21 Feb 2025 05:06:03 +0200 Subject: [PATCH v2 4/6] PCI: dwc: pcie-qcom-ep: enable EP support for SAR2130P Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250221-sar2130p-pci-v2-4-cc87590ffbeb@linaro.org> References: <20250221-sar2130p-pci-v2-0-cc87590ffbeb@linaro.org> In-Reply-To: <20250221-sar2130p-pci-v2-0-cc87590ffbeb@linaro.org> To: Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Mrinmay Sarkar , Bjorn Andersson , Konrad Dybcio Cc: =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=992; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=r63bMyziS5VAUoRIbBTBNVf6CyjstQjiNuFZTwV1jAY=; b=owEBbQKS/ZANAwAKARTbcu2+gGW4AcsmYgBnt+2aLBoqC7gDH2lR6m3K+MOfN99dXco+FQOjY Z7D5QrZfN6JAjMEAAEKAB0WIQRdB85SOKWMgfgVe+4U23LtvoBluAUCZ7ftmgAKCRAU23LtvoBl uNpAD/4kNOZSOtJdaVWeVbYNca7r58HQ6qqCh6bHGhy2ow0CqxOf3rrkU++ZvfSR+uU+7nMIOhB dPIj/V1OG694l1g6LN0r2mYQGAwzhkGID6G1A30OQJg6Jeb4qCGOIBrv0GLKdeppxVk4O9k5Euk X85HA795bwkpC95P9r4jYNMFr1oNagHER9g1KKlUOJH6fYOB+llzsCYVNaCmad5of9zuMOkK6Qw 8PnYX3uP+YKUog7y52RIca5OC/v4WRzzp8U8fNcxsjuEtngK2igQuvsMaZLM46jL9rP4wbr6Gtt OZ5WK78E+a0lqaUM22kkOCFkmkZ4gMM1q08hQFZOi0snXM5WCRJvIJOv1dbTBrtJ6x0xaAV1HKp yahVAV+hB/DiUlYvB6KoxAJjuixvSz1v8ZmZcCKnK7awHOYjVKgFTpb0BNab4VfHol1xUdc+fUx DWQOfBb4uzMPQFr8LRgMpVrumqf0gNrm+Nf8SJCHYAq1LPGqVfomkKWGtq05gsJ6OFQlHTeQLA6 g1mq7f4ZRp4m6jAX6d0yLeJDdLFZdftnlAhJYrF+k61kqr7fIHUIWKi7PS62nfWGoGQKEvfbWZn k5SCY/74hHLh5Ii8iFRYLoSuCtsrPw8dNTBirjYm3XL1ysv0OIkoQnzcGk9z937Vc+SrZjecIY7 SmyMA1H7CsmeeGA== X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Enable PCIe endpoint support for the Qualcomm SAR2130P platform. It is impossible to use fallback compatible to any other platform since SAR2130P uses slightly different set of clocks. Signed-off-by: Dmitry Baryshkov --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/contro= ller/dwc/pcie-qcom-ep.c index c08f64d7a825fa5da22976c8020f96ee5faa5462..dec5675c7c9d52b77f084ae1398= 45b488fa02d2c 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -933,6 +933,7 @@ static const struct of_device_id qcom_pcie_ep_match[] = =3D { { .compatible =3D "qcom,sa8775p-pcie-ep", .data =3D &cfg_1_34_0}, { .compatible =3D "qcom,sdx55-pcie-ep", }, { .compatible =3D "qcom,sm8450-pcie-ep", }, + { .compatible =3D "qcom,sar2130p-pcie-ep", }, { } }; MODULE_DEVICE_TABLE(of, qcom_pcie_ep_match); --=20 2.39.5 From nobody Mon Feb 9 06:45:02 2026 Received: from mail-lj1-f180.google.com (mail-lj1-f180.google.com [209.85.208.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7AB521EBFE6 for ; Fri, 21 Feb 2025 03:06:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.180 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740107181; cv=none; b=uIu0Igu7JWqipTLzoyJVJSD9D9GjjVj5i3GhxtYowDQ9T+7SXo/3Dr5Bn8WdL0z/Sw/i3fe+bKanRPu2MGMa/j/EUiWpzJ8gnwCymWY8JpTkZMEtwe+T6eMoy+G3JxDRHnAOhSJsF8IZi1hQb4rgY9b/N9w5Z+A0M+SJjN46d+o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740107181; c=relaxed/simple; bh=b6PLMBw7yyw15o3VEzosQAWxFJYLV5zXvl5ZUGHocbU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=dSuHdrQA76ZXjBKJYOmCVY7nfcPsLXT1dP9mByJ87ynpWYOC0GX6+nAFiwgCQZBRwdtKbYX95AHHq8MXOCgWvF+yJD56pom0qTZbSr7C3uT6U/qFgFKvS8KFed2xZPofNZQz161eRFgGQUQLDBgSeD/BE0ZLUt9FtsWXXOjbNCM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=fJIXdnMh; arc=none smtp.client-ip=209.85.208.180 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="fJIXdnMh" Received: by mail-lj1-f180.google.com with SMTP id 38308e7fff4ca-30a3092a9ebso18291761fa.1 for ; Thu, 20 Feb 2025 19:06:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1740107178; x=1740711978; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Hf+01lWdYqM6cH2pf9TEQebVcTlfAkpm0nesnJVjo8c=; b=fJIXdnMhnFFRD7MiHalQg29wbAstLuu+0VUc2u1aA4KK0VsZnW/SLBt8863ph6InV2 NNHIAucXAgzm2mjTCAzpLlN/RY7s8XrYO9EoRhjYAzSoCGsG8T4QNj+o6a/1IGrh4wYT m8WlfKRJfTMl4KRnBziHHLYynqtQH1yducUjdHdimnHCks/lnfDW1NuHOarolN+7Rzj0 x7Vartn/NCd0MRKfwgUuof1vtkYtV/IMbONd8F0Elrb2ai4x331mMD3UsovnmQrDvCqw nRUDRUkEA7PoZf02CKEN9MZ0y4KqgjGkCVH5Rm/q0nethq21sqD+ztflzSLJgcTpl7aP Zy5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740107178; x=1740711978; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Hf+01lWdYqM6cH2pf9TEQebVcTlfAkpm0nesnJVjo8c=; b=Nq1tQkxoxpIlauoi/zDQDETDQ8lLnF+EoS/bcBnimYv/hfXPMXwa7tcvzBEIZNghWl sBbTxy3tZvec10qY5dHVjJ+jprT9JB1E//zbGHE5oVpO8jNqX4gLwMlKO0PM5kXk60Su yTnh9j5gEQ+zDoi4I9dozIJ9OivqitRBWPk+4rybTvqzp5JvTjam8Z2QpCHQRfAie00N EziYEIZ2p5GCMJYTVW2FzBH7tMFh1AJICvSGpoOHwaxWOO6zoWadAHcKXjXiZIqMN1ae ekAwbOcI1YWqUsIGjgEbjOIXCWi/3bGf+on1ZGPQFoeqh+m5NQgLuDRvICQqIlgjbUgA J4XA== X-Forwarded-Encrypted: i=1; AJvYcCWfgZWI5ZmXMOveWKbDUDFmJKStE/QY8a82O32u7CrkTf89YFq/9ROQ69drNw7mGhpmQMed8JS20UFj4oQ=@vger.kernel.org X-Gm-Message-State: AOJu0YxviWjQrhq46+fVQ9Ep0oTxP/Dpxz0C4SeReWYkeuMUjugyb1qm JMU8evmw3uMS69tKLZM9zQnXhouwbB9kB9Wt3Uaa/MrnFC2XjqlNl30v7MNqF/o= X-Gm-Gg: ASbGncsDL8WcZMAZ2M0j1ZZHa/7v+WCivqbxcqQxH3sejZrqPVL+onUFy5pmnJqAFpS dQWrENojUE3huCKX+raWmIiCICe//AtBRBgsZaM8wztzJrkhUPmhUUX9wKMFLJOpEgy6hHcWNn3 eShRTJqHxf9niY/jQozgQSXZfVvlWX9i/zZJIbhU5QGVGEoDE/bRMFRWCHdFltYiermNtJY+SPT uFMSjRTs7hTjlglMApJTylhQkNt+VIB+NQh0E2UmAjRWEChaS41gf5B/6L+wNf96tVg1AwsW3QV aJeumEMyouqJ4/2xyJdP5ZzqylQiYZkc7Pr3xGh6JwJD8ehn8zXRkX79VZ9IOQbAZDPB8A== X-Google-Smtp-Source: AGHT+IFIkUTVECcUanvIgEQylzLf9cAeuyCvSYP0ViEN5AYii2FSHeNuyGSW+Wo3XvGPACfY4hAK+Q== X-Received: by 2002:a2e:9dd1:0:b0:302:22e6:5f8 with SMTP id 38308e7fff4ca-30a5b1a0abbmr2867681fa.22.1740107177715; Thu, 20 Feb 2025 19:06:17 -0800 (PST) Received: from [127.0.1.1] (2001-14ba-a0c3-3a00--782.rev.dnainternet.fi. [2001:14ba:a0c3:3a00::782]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-30a2be45876sm16021071fa.68.2025.02.20.19.06.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Feb 2025 19:06:16 -0800 (PST) From: Dmitry Baryshkov Date: Fri, 21 Feb 2025 05:06:04 +0200 Subject: [PATCH v2 5/6] arm64: dts: qcom: sar2130p: add PCIe EP device nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250221-sar2130p-pci-v2-5-cc87590ffbeb@linaro.org> References: <20250221-sar2130p-pci-v2-0-cc87590ffbeb@linaro.org> In-Reply-To: <20250221-sar2130p-pci-v2-0-cc87590ffbeb@linaro.org> To: Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Mrinmay Sarkar , Bjorn Andersson , Konrad Dybcio Cc: =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2669; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=b6PLMBw7yyw15o3VEzosQAWxFJYLV5zXvl5ZUGHocbU=; b=owEBbQKS/ZANAwAKARTbcu2+gGW4AcsmYgBnt+2b+vvnC24YRd+vl6st9IhT/q4OakLKzn3F1 t8d/ehBxPaJAjMEAAEKAB0WIQRdB85SOKWMgfgVe+4U23LtvoBluAUCZ7ftmwAKCRAU23LtvoBl uAF/EACctPzzgaDqLQSaaREFQA19W77YUO8fSLwo3g+BSjaRWIwdGGBwAYYblO6NDQbrbFBLBeR 8eF7IJ8kUlXvnyu4KSXXIgnDBBz/WLUuMTMRnpceYGLb6tyTDwD0Xud9/6KLl4MUSMPB1wEAZuq 46ejpKeBjz+WebjjgGHhJBTJENBluVHXQxAmY775Xz4kzri80ApF2jPAp+r01yDYx3/pT9x+ssa WjwgRG5QcB9Bk6RL4HtvK67DeDuIOmlcNr/LiByWzyHdCjKGciVB4wU+rmOeQqX1OVrHR8nN17E RGpX+V/T/aTMo5brQIb7qpppdLjQYIbqavISKKvkffR9xNsNJoMC+qfXrfsGWeSTW+WJB6gYagz 83JFjAlhFRv020J13Xo37JZih7UakHZqu+OPRTLv037h5WCuMsGpI9S4RwzMrmqr3eQmVvCqi31 mi7tozjx5CIq01SxleumvS+dGtxZEgmMg8i50tUkYZZkoB6piCFSpGjhESpdIMoMqBzJPB/Zdqr lWJwJvnj7ZuvqyNWkmNgwglr5yzaL+JxPo7VVpjmPaiDRzKSzMd85Rr2JV+55MC18H3REqLbJlW uIgAW70fhj9sjmdql0B0oJ49fFyXkTnkckt4NRoNfGMJSpRpui/adCnNj5hMuLxlsJ/Jnv8p+MY zcyXB9UJ+LWiNjg== X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A On the Qualcomm AR2 Gen1 platform the second PCIe host can be used either as an RC or as an EP device. Add device node for the PCIe EP. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sar2130p.dtsi | 61 ++++++++++++++++++++++++++++++= ++++ 1 file changed, 61 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sar2130p.dtsi b/arch/arm64/boot/dts/q= com/sar2130p.dtsi index dd832e6816be85817fd1ecc853f8d4c800826bc4..b45e9e2ae0357bd0c7d719eaf4f= c1faa1cf913f2 100644 --- a/arch/arm64/boot/dts/qcom/sar2130p.dtsi +++ b/arch/arm64/boot/dts/qcom/sar2130p.dtsi @@ -1474,6 +1474,67 @@ pcie@0 { }; }; =20 + pcie1_ep: pcie-ep@1c08000 { + compatible =3D "qcom,sar2130p-pcie-ep"; + reg =3D <0x0 0x01c08000 0x0 0x3000>, + <0x0 0x40000000 0x0 0xf1d>, + <0x0 0x40000f20 0x0 0xa8>, + <0x0 0x40001000 0x0 0x1000>, + <0x0 0x40200000 0x0 0x1000000>, + <0x0 0x01c0b000 0x0 0x1000>, + <0x0 0x40002000 0x0 0x2000>; + reg-names =3D "parf", + "dbi", + "elbi", + "atu", + "addr_space", + "mmio", + "dma"; + + clocks =3D <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, + <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>, + <&gcc GCC_QMIP_PCIE_AHB_CLK>; + clock-names =3D "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ddrss_sf_tbu", + "aggre_noc_axi", + "cnoc_sf_axi", + "qmip_pcie_ahb"; + + interrupts =3D , + , + ; + interrupt-names =3D "global", + "doorbell", + "dma"; + + interconnects =3D <&pcie_noc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_PCIE_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "pcie-mem", + "cpu-pcie"; + iommus =3D <&apps_smmu 0x1e00 0x1>; + resets =3D <&gcc GCC_PCIE_1_BCR>; + reset-names =3D "core"; + power-domains =3D <&gcc PCIE_1_GDSC>; + phys =3D <&pcie1_phy>; + phy-names =3D "pciephy"; + + num-lanes =3D <2>; + + status =3D "disabled"; + }; + pcie1_phy: phy@1c0e000 { compatible =3D "qcom,sar2130p-qmp-gen3x2-pcie-phy"; reg =3D <0x0 0x01c0e000 0x0 0x2000>; --=20 2.39.5 From nobody Mon Feb 9 06:45:02 2026 Received: from mail-lf1-f52.google.com (mail-lf1-f52.google.com [209.85.167.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1AEB01F03F4 for ; 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[2001:14ba:a0c3:3a00::782]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-30a2be45876sm16021071fa.68.2025.02.20.19.06.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Feb 2025 19:06:18 -0800 (PST) From: Dmitry Baryshkov Date: Fri, 21 Feb 2025 05:06:05 +0200 Subject: [PATCH v2 6/6] arm64: dts: qcom: sm8450: add PCIe EP device nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250221-sar2130p-pci-v2-6-cc87590ffbeb@linaro.org> References: <20250221-sar2130p-pci-v2-0-cc87590ffbeb@linaro.org> In-Reply-To: <20250221-sar2130p-pci-v2-0-cc87590ffbeb@linaro.org> To: Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Mrinmay Sarkar , Bjorn Andersson , Konrad Dybcio Cc: =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2643; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=itIH8UmE28DLal026/vQWt51OaBADCkRmt6MMWb6ec0=; b=owEBbQKS/ZANAwAKARTbcu2+gGW4AcsmYgBnt+2bRGfqizSlKdB8tdyZiV1VxNhZGs2adFF6Q ur6WJ32FfSJAjMEAAEKAB0WIQRdB85SOKWMgfgVe+4U23LtvoBluAUCZ7ftmwAKCRAU23LtvoBl uIuzEACbi9w3d7ZvRKbNhxJBhT/FFx65l6Q3qqCPHdUy0xu8P27eHy4CEE+HUKOdryYpUAX7PN+ F2DOuhUd16MznS4jqU8J3f0TUKZQGygL/ywiCs73mWFHdbBXe2c/WUiuvtkwzVu5v4eYcUEYLv1 SxF5W9gILOOHxxWAn63F2DJBHYjQ9pUrUdIlQdfSG1cr3SH1mOsJFEqaIYOQ7nNj8PEn1gQjMj4 b3JaDSvjfQglIvYCefHMgFuapvnEQkKqK7U+JnIrTCkMyY2N4vWLfZHBfsseBHyFADSrWcKXmAB XsLL5mT9hpKnGQ3l8hiLXLvgdpMf7IqGR3zAOf/BbWny2PgXcu/9kWVj7k4LEFl/J5Lu4HOHftP QMm8B9EEIIjHMLjCxT2a45mKVkgV2U9cM+hGbmKY9uxdJP1qReRQ8vnIGWRC3zp5vsgys8oxYp8 XKAbPH7NB74VTjheIGFQkPqNS7qJqDw3pSo45anzlfED8U51oqjzIAZkOJZHcdWJEO2JsSFnFkh Vd1vI8i9mLAEDl1jlEd9pjyT5pEmLUXfNsbEYYNq1GDlaDQmafRGkDmCAjO5AZOUAFM62BUTED5 rY09HCjSKqVtJMby7JsVMyThE7X8LAOxJhtp3qnd4gFbUzwfCp1iNtRF1Leq4E3xUmCvjyCHgQV NbXKbg4/8LoBT3w== X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A On the Qualcomm SM8450 platform the second PCIe host can be used either as an RC or as an EP device. Add device node for the PCIe EP. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 62 ++++++++++++++++++++++++++++++++= ++++ 1 file changed, 62 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qco= m/sm8450.dtsi index 9c809fc5fa45a98ff5441a0b6809931588897243..3783930d63a73158addc44d00d9= da2efa0986a25 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -2262,6 +2262,68 @@ pcie@0 { }; }; =20 + pcie1_ep: pcie-ep@1c08000 { + compatible =3D "qcom,sm8450-pcie-ep"; + reg =3D <0x0 0x01c08000 0x0 0x3000>, + <0x0 0x40000000 0x0 0xf1d>, + <0x0 0x40000f20 0x0 0xa8>, + <0x0 0x40001000 0x0 0x1000>, + <0x0 0x40200000 0x0 0x1000000>, + <0x0 0x01c0b000 0x0 0x1000>, + <0x0 0x40002000 0x0 0x1000>; + reg-names =3D "parf", + "dbi", + "elbi", + "atu", + "addr_space", + "mmio", + "dma"; + + clocks =3D <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; + clock-names =3D "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ref", + "ddrss_sf_tbu", + "aggre_noc_axi"; + + interrupts =3D , + , + ; + interrupt-names =3D "global", + "doorbell", + "dma"; + + interconnects =3D <&pcie_noc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_PCIE_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "pcie-mem", + "cpu-pcie"; + + iommus =3D <&apps_smmu 0x1c80 0x7f>; + resets =3D <&gcc GCC_PCIE_1_BCR>; + reset-names =3D "core"; + power-domains =3D <&gcc PCIE_1_GDSC>; + phys =3D <&pcie1_phy>; + phy-names =3D "pciephy"; + num-lanes =3D <2>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie1_default_state>; + + status =3D "disabled"; + }; + pcie1_phy: phy@1c0e000 { compatible =3D "qcom,sm8450-qmp-gen4x2-pcie-phy"; reg =3D <0 0x01c0e000 0 0x2000>; --=20 2.39.5