From nobody Fri Dec 19 01:44:28 2025 Received: from smtp-42ab.mail.infomaniak.ch (smtp-42ab.mail.infomaniak.ch [84.16.66.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9E3B41420DD; Fri, 21 Feb 2025 14:15:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=84.16.66.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740147314; cv=none; b=EZr4s6KxKuWYbqnRYEVKV1f2CxZxnmt5zRuQVTbXNtu6gBfDTySvxntYWaYcg4Ejpp3HYcHS8lgNaPB9ujZM+QeZg/yvvgbLU4Nf7jmRXflLpyETgnr7GIpTWfA8IHO1EjdvGvz2xNQXwmemOZ3yDyRl/z47qJU/k4iDcC9g/u4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740147314; c=relaxed/simple; bh=RXAxhxVzfrqG1qHIsuf8PzuIRfypisrlFp/ZVrBCPRA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=nACeeJBGv2gybvkK/Dayq6Ze5gBmJ7ZLv2ZbZWHj+5F9WI9Mpa/f0FQJxkjTqtmTqnDRckXhQF5qLI3vDbmzcegLXytI3Q3VeT+WhpNbufSjAYlnoAmxpsJoHomWkHm2pbOwAMItb744t/Mylsd/lqiGmzWotUV3bn32FY0ql8c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=0leil.net; spf=pass smtp.mailfrom=0leil.net; arc=none smtp.client-ip=84.16.66.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=0leil.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=0leil.net Received: from smtp-4-0000.mail.infomaniak.ch (unknown [IPv6:2001:1600:7:10:40ca:feff:fe05:0]) by smtp-4-3000.mail.infomaniak.ch (Postfix) with ESMTPS id 4YzsMc4NCDzVD1; Fri, 21 Feb 2025 15:05:00 +0100 (CET) Received: from unknown by smtp-4-0000.mail.infomaniak.ch (Postfix) with ESMTPA id 4YzsMb6vqwzYln; Fri, 21 Feb 2025 15:04:59 +0100 (CET) From: Quentin Schulz Date: Fri, 21 Feb 2025 15:04:33 +0100 Subject: [PATCH v2 1/5] arm64: dts: rockchip: fix pinmux of UART0 for PX30 Ringneck on Haikou Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250221-ringneck-dtbos-v2-1-310c0b9a3909@cherry.de> References: <20250221-ringneck-dtbos-v2-0-310c0b9a3909@cherry.de> In-Reply-To: <20250221-ringneck-dtbos-v2-0-310c0b9a3909@cherry.de> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Quentin Schulz , Farouk Bouabid Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Quentin Schulz , stable@vger.kernel.org X-Mailer: b4 0.14.2 X-Infomaniak-Routing: alpha From: Quentin Schulz UART0 pinmux by default configures GPIO0_B5 in its UART RTS function for UART0. However, by default on Haikou, it is used as GPIO as UART RTS for UART5. Therefore, let's update UART0 pinmux to not configure the pin in that mode, a later commit will make UART5 to request the GPIO pinmux. Fixes: c484cf93f61b ("arm64: dts: rockchip: add PX30-=C2=B5Q7 (Ringneck) So= M with Haikou baseboard") Cc: stable@vger.kernel.org Signed-off-by: Quentin Schulz --- arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts b/arch/a= rm64/boot/dts/rockchip/px30-ringneck-haikou.dts index e4517f47d519cc08ec9ee705a6f51a740687f6df..2321536c553fed20bc02d91f40a= 5d5a6dc20892c 100644 --- a/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts +++ b/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts @@ -222,6 +222,7 @@ &u2phy_otg { }; =20 &uart0 { + pinctrl-0 =3D <&uart0_xfer>; status =3D "okay"; }; =20 --=20 2.48.1