From nobody Thu Dec 18 16:20:49 2025 Received: from smtp-42ab.mail.infomaniak.ch (smtp-42ab.mail.infomaniak.ch [84.16.66.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9E3B41420DD; Fri, 21 Feb 2025 14:15:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=84.16.66.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740147314; cv=none; b=EZr4s6KxKuWYbqnRYEVKV1f2CxZxnmt5zRuQVTbXNtu6gBfDTySvxntYWaYcg4Ejpp3HYcHS8lgNaPB9ujZM+QeZg/yvvgbLU4Nf7jmRXflLpyETgnr7GIpTWfA8IHO1EjdvGvz2xNQXwmemOZ3yDyRl/z47qJU/k4iDcC9g/u4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740147314; c=relaxed/simple; bh=RXAxhxVzfrqG1qHIsuf8PzuIRfypisrlFp/ZVrBCPRA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=nACeeJBGv2gybvkK/Dayq6Ze5gBmJ7ZLv2ZbZWHj+5F9WI9Mpa/f0FQJxkjTqtmTqnDRckXhQF5qLI3vDbmzcegLXytI3Q3VeT+WhpNbufSjAYlnoAmxpsJoHomWkHm2pbOwAMItb744t/Mylsd/lqiGmzWotUV3bn32FY0ql8c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=0leil.net; spf=pass smtp.mailfrom=0leil.net; arc=none smtp.client-ip=84.16.66.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=0leil.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=0leil.net Received: from smtp-4-0000.mail.infomaniak.ch (unknown [IPv6:2001:1600:7:10:40ca:feff:fe05:0]) by smtp-4-3000.mail.infomaniak.ch (Postfix) with ESMTPS id 4YzsMc4NCDzVD1; Fri, 21 Feb 2025 15:05:00 +0100 (CET) Received: from unknown by smtp-4-0000.mail.infomaniak.ch (Postfix) with ESMTPA id 4YzsMb6vqwzYln; Fri, 21 Feb 2025 15:04:59 +0100 (CET) From: Quentin Schulz Date: Fri, 21 Feb 2025 15:04:33 +0100 Subject: [PATCH v2 1/5] arm64: dts: rockchip: fix pinmux of UART0 for PX30 Ringneck on Haikou Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250221-ringneck-dtbos-v2-1-310c0b9a3909@cherry.de> References: <20250221-ringneck-dtbos-v2-0-310c0b9a3909@cherry.de> In-Reply-To: <20250221-ringneck-dtbos-v2-0-310c0b9a3909@cherry.de> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Quentin Schulz , Farouk Bouabid Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Quentin Schulz , stable@vger.kernel.org X-Mailer: b4 0.14.2 X-Infomaniak-Routing: alpha From: Quentin Schulz UART0 pinmux by default configures GPIO0_B5 in its UART RTS function for UART0. However, by default on Haikou, it is used as GPIO as UART RTS for UART5. Therefore, let's update UART0 pinmux to not configure the pin in that mode, a later commit will make UART5 to request the GPIO pinmux. Fixes: c484cf93f61b ("arm64: dts: rockchip: add PX30-=C2=B5Q7 (Ringneck) So= M with Haikou baseboard") Cc: stable@vger.kernel.org Signed-off-by: Quentin Schulz --- arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts b/arch/a= rm64/boot/dts/rockchip/px30-ringneck-haikou.dts index e4517f47d519cc08ec9ee705a6f51a740687f6df..2321536c553fed20bc02d91f40a= 5d5a6dc20892c 100644 --- a/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts +++ b/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts @@ -222,6 +222,7 @@ &u2phy_otg { }; =20 &uart0 { + pinctrl-0 =3D <&uart0_xfer>; status =3D "okay"; }; =20 --=20 2.48.1 From nobody Thu Dec 18 16:20:49 2025 Received: from smtp-bc0f.mail.infomaniak.ch (smtp-bc0f.mail.infomaniak.ch [45.157.188.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D98A91BCA07 for ; Fri, 21 Feb 2025 14:05:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.157.188.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740146711; cv=none; b=JpaNUoaXFP31iZXOs61QMT8WNIr/LljbRAHDj8apipypXuJDx6O9UMWZvud8afjGXjZpMB3u6fF52Gy+wPP+c1P+9kTX/uGdZYsCjDWw79oD7dQNNwcs4CWLkF+/xOBOoybX1ZBeCiyGGqbENnTfBMYZ+cw6eyOrPVaoiVfD8FU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740146711; c=relaxed/simple; bh=ud9Ewppi6nbTHhEJv90ldubIDs0VF8/bmpXcameaIzg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=MyHx84qXAmQoQEepfV/bC9oDUr9WAWhb/WR+pMlfoFCpPVYrJCewswki1tHxr0/LLW37b1n69wQrvR1r5TcWvZltTs8CwrBo28vWPBhuTdmDWRzIoAQb1tIr97yyyl3h8+4dOAfdvMHJOW6sOGlWxIGaXYP/2JyBcRpUiab+j9I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=0leil.net; spf=pass smtp.mailfrom=0leil.net; arc=none smtp.client-ip=45.157.188.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=0leil.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=0leil.net Received: from smtp-4-0000.mail.infomaniak.ch (unknown [IPv6:2001:1600:7:10:40ca:feff:fe05:0]) by smtp-4-3000.mail.infomaniak.ch (Postfix) with ESMTPS id 4YzsMd2NfgzTCq; Fri, 21 Feb 2025 15:05:01 +0100 (CET) Received: from unknown by smtp-4-0000.mail.infomaniak.ch (Postfix) with ESMTPA id 4YzsMc4HR9zYHX; Fri, 21 Feb 2025 15:05:00 +0100 (CET) From: Quentin Schulz Date: Fri, 21 Feb 2025 15:04:34 +0100 Subject: [PATCH v2 2/5] arm64: dts: rockchip: fix pinmux of UART5 for PX30 Ringneck on Haikou Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250221-ringneck-dtbos-v2-2-310c0b9a3909@cherry.de> References: <20250221-ringneck-dtbos-v2-0-310c0b9a3909@cherry.de> In-Reply-To: <20250221-ringneck-dtbos-v2-0-310c0b9a3909@cherry.de> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Quentin Schulz , Farouk Bouabid Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Quentin Schulz , stable@vger.kernel.org X-Mailer: b4 0.14.2 X-Infomaniak-Routing: alpha From: Quentin Schulz UART5 uses GPIO0_B5 as UART RTS but muxed in its GPIO function, therefore UART5 must request this pin to be muxed in that function, so let's do that. Fixes: 5963d97aa780 ("arm64: dts: rockchip: add rs485 support on uart5 of p= x30-ringneck-haikou") Cc: stable@vger.kernel.org Signed-off-by: Quentin Schulz --- arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts b/arch/a= rm64/boot/dts/rockchip/px30-ringneck-haikou.dts index 2321536c553fed20bc02d91f40a5d5a6dc20892c..e9ebac0f4984a26ec288083f74c= 7e193cdbec326 100644 --- a/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts +++ b/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts @@ -194,6 +194,13 @@ sd_card_led_pin: sd-card-led-pin { <3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; }; }; + + uart { + uart5_rts_pin: uart5-rts-pin { + rockchip,pins =3D + <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; }; =20 &pwm0 { @@ -227,7 +234,7 @@ &uart0 { }; =20 &uart5 { - pinctrl-0 =3D <&uart5_xfer>; + pinctrl-0 =3D <&uart5_xfer &uart5_rts_pin>; rts-gpios =3D <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; status =3D "okay"; }; --=20 2.48.1 From nobody Thu Dec 18 16:20:49 2025 Received: from smtp-bc0b.mail.infomaniak.ch (smtp-bc0b.mail.infomaniak.ch [45.157.188.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C36461EB1B9 for ; Fri, 21 Feb 2025 14:05:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.157.188.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740146712; cv=none; b=oBKPJzLTDRjNVWfrpyv7kHZCbj6GEpIVdSpwZ2LdW2ph0G7yszHftnrRrt0jgu3wleIOyDAIvBM5YYK/+o6uKWtbKtyM2D+u2rdCUoxIrdxt5tRE1iBzk0t6W+90fv+pYVoH7MxAK3oOKWCjEySBt1YdVVFdOavlTUMFhn5eEhI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740146712; c=relaxed/simple; bh=T1iXvRyD29yOzLTQL99Z3lF9EZFdZpHfsWETfDgieRE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Kfzb6VWAl0uOzsYeJl3o4pVgUFWbqdPRlfnjghr7S6Qc18xRaAULUf02kzxLJ7Y31MU2pwxto0hc2vPOr5dNHkfkrWuwtS4QRXu6Z2TVBJ4Xg8v1bF/vZCSqO7B/DlQgOdx7mdXPQomyYxQStmPA6QzYQ3jBU6geYog09Feq8vU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=0leil.net; spf=pass smtp.mailfrom=0leil.net; arc=none smtp.client-ip=45.157.188.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=0leil.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=0leil.net Received: from smtp-4-0000.mail.infomaniak.ch (unknown [IPv6:2001:1600:7:10:40ca:feff:fe05:0]) by smtp-4-3000.mail.infomaniak.ch (Postfix) with ESMTPS id 4YzsMd6d7rzVYM; Fri, 21 Feb 2025 15:05:01 +0100 (CET) Received: from unknown by smtp-4-0000.mail.infomaniak.ch (Postfix) with ESMTPA id 4YzsMd2HNBzYZB; Fri, 21 Feb 2025 15:05:01 +0100 (CET) From: Quentin Schulz Date: Fri, 21 Feb 2025 15:04:35 +0100 Subject: [PATCH v2 3/5] arm64: dts: rockchip: add support for HAIKOU-LVDS-9904379 adapter for PX30 Ringneck Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250221-ringneck-dtbos-v2-3-310c0b9a3909@cherry.de> References: <20250221-ringneck-dtbos-v2-0-310c0b9a3909@cherry.de> In-Reply-To: <20250221-ringneck-dtbos-v2-0-310c0b9a3909@cherry.de> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Quentin Schulz , Farouk Bouabid Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Quentin Schulz X-Mailer: b4 0.14.2 X-Infomaniak-Routing: alpha From: Quentin Schulz The HAIKOU-LVDS-9904379 adapter is an adapter for PX30 Ringneck with the Haikou carrierboard. It is to be inserted in the fake PCIe slot labelled Video Connector. This adapter expects an Admatec 9904379 1024x600 LVDS display with backlight and touchscreen. An EEPROM is also found on the adapter. This adds support for this adapter on PX30 Ringneck when inserted in Haikou carrierboard. Signed-off-by: Quentin Schulz --- arch/arm64/boot/dts/rockchip/Makefile | 5 + .../px30-ringneck-haikou-lvds-9904379.dtso | 130 +++++++++++++++++= ++++ 2 files changed, 135 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/ro= ckchip/Makefile index e4d9c48b95bba204f50697480d06e9a4071e56d3..b40b82bd07223f542c17704e784= 4f002bb31e1c5 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -5,6 +5,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D px30-engicam-px30-core-cto= uch2-of10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D px30-engicam-px30-core-edimm2.2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D px30-firefly-jd4-core-mb.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D px30-ringneck-haikou.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D px30-ringneck-haikou-lvds-9904379.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3308-bpi-p2-pro.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3308-evb.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3308-roc-cc.dtb @@ -191,6 +192,10 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588s-rock-5c.dtb # result of the application of .dtbo and other listed overlays = on top # of .dtb. =20 +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D px30-ringneck-haikou-haikou-lvds-9904379.= dtb +px30-ringneck-haikou-haikou-lvds-9904379-dtbs :=3D px30-ringneck-haikou.dt= b \ + px30-ringneck-haikou-lvds-9904379.dtbo + dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-wolfvision-pf5-vz-2-uhd.dtb rk3568-wolfvision-pf5-vz-2-uhd-dtbs :=3D rk3568-wolfvision-pf5.dtb \ rk3568-wolfvision-pf5-display-vz.dtbo \ diff --git a/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou-lvds-9904379= .dtso b/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou-lvds-9904379.dtso new file mode 100644 index 0000000000000000000000000000000000000000..3fc088a5636a24b40a8536b28a2= 10fce79f6d333 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou-lvds-9904379.dtso @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Cherry Embedded Solutions GmbH + * + * HAIKOU-LVDS-9904379 adapter for PX30 Ringneck and Haikou carrierboard. + * + * This adapter needs to be plugged in the fake PCIe connector called Video + * Connector on Haikou carrierboard. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include + +&{/} { + backlight_lvds: backlight-lvds { + compatible =3D "pwm-backlight"; + brightness-levels =3D <0 255>; + default-brightness-level =3D <255>; + num-interpolated-steps =3D <255>; + power-supply =3D <&vcc3v3_baseboard>; + pwms =3D <&pwm0 0 25000 0>; + }; + + panel { + compatible =3D "admatec,9904379", "panel-lvds"; + backlight =3D <&backlight_lvds>; + data-mapping =3D "vesa-24"; + height-mm =3D <126>; + power-supply =3D <&vcc3v3_baseboard>; + width-mm =3D <224>; + + panel-timing { + clock-frequency =3D <49500000>; + hactive =3D <1024>; + hback-porch =3D <90>; + hfront-porch =3D <90>; + hsync-len =3D <90>; + vactive =3D <600>; + vback-porch =3D <10>; + vfront-porch =3D <10>; + vsync-len =3D <10>; + }; + + port { + panel_in_lvds: endpoint { + remote-endpoint =3D <&lvds_out_panel>; + }; + }; + }; +}; + +&display_subsystem { + status =3D "okay"; +}; + +&dsi_dphy { + status =3D "okay"; +}; + +&i2c1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + /* EEPROM and GT928 are limited to 400KHz */ + clock-frequency =3D <400000>; + + touchscreen@14 { + compatible =3D "goodix,gt928"; + reg =3D <0x14>; + interrupt-parent =3D <&gpio0>; + interrupts =3D ; + irq-gpios =3D <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + reset-gpios =3D <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; + pinctrl-0 =3D <&touch_int &touch_rst>; + pinctrl-names =3D "default"; + touchscreen-inverted-x; + touchscreen-inverted-y; + AVDD28-supply =3D <&vcc3v3_baseboard>; + VDDIO-supply =3D <&vcc3v3_baseboard>; + }; + + eeprom@54 { + reg =3D <0x54>; + compatible =3D "st,24c04", "atmel,24c04"; + pagesize =3D <16>; + size =3D <512>; + vcc-supply =3D <&vcc3v3_baseboard>; + }; +}; + +&lvds { + status =3D "okay"; +}; + +&lvds_out { + lvds_out_panel: endpoint { + remote-endpoint =3D <&panel_in_lvds>; + }; +}; + +&pinctrl { + touch { + touch_int: touch-int { + rockchip,pins =3D <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + touch_rst: touch-rst { + rockchip,pins =3D <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&vopb { + status =3D "okay"; +}; + +&vopb_mmu { + status =3D "okay"; +}; + +&vopl { + status =3D "okay"; +}; + +&vopl_mmu { + status =3D "okay"; +}; --=20 2.48.1 From nobody Thu Dec 18 16:20:49 2025 Received: from smtp-bc0b.mail.infomaniak.ch (smtp-bc0b.mail.infomaniak.ch [45.157.188.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A6B75204C02 for ; Fri, 21 Feb 2025 14:05:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.157.188.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740146712; cv=none; b=IenLOZ4oJTn6isSAJ+VDSZl0ENljRJ/QmNlRZgKwMe2SblLqQ9G/qjpC6hjn1f6UIN0egMuwfbp9AsFm67HZsbuQeEvr+Cw2zU6NioJask4j0X9WylmvMDSjh4cLY83gohG9bCsRySeyW3EoIN0TxmOYJ+KUt2ZSdWIDs/M/xOo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740146712; c=relaxed/simple; bh=+JLjXWKiRg+EQ4ENsImXRR1E80JN9eVBk/Ontn9bJF4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=heW76YQo0HaPH51EttTCX0Tke7fikxTENIRZ+Wajlrh7dvvKxhCS2kxp5EinMOrXMgsuu5mrYYK/NHTMDUrosqDIuoqsBrXzj1/StDTaT8PDvx8lQgmRNprN1gtYTI9Shc3M90wU6UEDEz1PqkJonytJQw6UBxj2J/Xs34iRdDM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=0leil.net; spf=pass smtp.mailfrom=0leil.net; arc=none smtp.client-ip=45.157.188.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=0leil.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=0leil.net Received: from smtp-4-0000.mail.infomaniak.ch (smtp-4-0000.mail.infomaniak.ch [10.7.10.107]) by smtp-4-3000.mail.infomaniak.ch (Postfix) with ESMTPS id 4YzsMf5YhgzRdr; Fri, 21 Feb 2025 15:05:02 +0100 (CET) Received: from unknown by smtp-4-0000.mail.infomaniak.ch (Postfix) with ESMTPA id 4YzsMd6ZDmzX2K; Fri, 21 Feb 2025 15:05:01 +0100 (CET) From: Quentin Schulz Date: Fri, 21 Feb 2025 15:04:36 +0100 Subject: [PATCH v2 4/5] arm64: dts: rockchip: add overlay for PX30 Ringneck Haikou Video Demo adapter Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250221-ringneck-dtbos-v2-4-310c0b9a3909@cherry.de> References: <20250221-ringneck-dtbos-v2-0-310c0b9a3909@cherry.de> In-Reply-To: <20250221-ringneck-dtbos-v2-0-310c0b9a3909@cherry.de> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Quentin Schulz , Farouk Bouabid Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Quentin Schulz X-Mailer: b4 0.14.2 X-Infomaniak-Routing: alpha From: Quentin Schulz This adds support for the video-demo-adapter DEVKIT ADDON CAM-TS-A01 (https://embedded.cherry.de/product/development-kit/) for the Haikou devkit with PX30 Ringneck SoM. The Video Demo adapter is an adapter connected to the fake PCIe slot labeled "Video Connector" on the Haikou devkit. Itss main feature is a Leadtek DSI-display with touchscreen and a camera (that is not supported yet because the expected clock rate by the driver cannot be exactly reached by the clock driver). To drive these components a number of additional regulators are grouped on the adapter as well as a PCA9670 gpio-expander to provide the needed additional gpio-lines. Signed-off-by: Quentin Schulz --- arch/arm64/boot/dts/rockchip/Makefile | 5 + .../rockchip/px30-ringneck-haikou-video-demo.dtso | 190 +++++++++++++++++= ++++ 2 files changed, 195 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/ro= ckchip/Makefile index b40b82bd07223f542c17704e7844f002bb31e1c5..0f7c5c55c8b8be11e3fd7a69995= ce1c17b22c80d 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -6,6 +6,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D px30-engicam-px30-core-edi= mm2.2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D px30-firefly-jd4-core-mb.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D px30-ringneck-haikou.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D px30-ringneck-haikou-lvds-9904379.dtbo +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D px30-ringneck-haikou-video-demo.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3308-bpi-p2-pro.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3308-evb.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3308-roc-cc.dtb @@ -196,6 +197,10 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D px30-ringneck-haikou-= haikou-lvds-9904379.dtb px30-ringneck-haikou-haikou-lvds-9904379-dtbs :=3D px30-ringneck-haikou.dt= b \ px30-ringneck-haikou-lvds-9904379.dtbo =20 +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D px30-ringneck-haikou-haikou-video-demo.dtb +px30-ringneck-haikou-haikou-video-demo-dtbs :=3D px30-ringneck-haikou.dtb \ + px30-ringneck-haikou-video-demo.dtbo + dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-wolfvision-pf5-vz-2-uhd.dtb rk3568-wolfvision-pf5-vz-2-uhd-dtbs :=3D rk3568-wolfvision-pf5.dtb \ rk3568-wolfvision-pf5-display-vz.dtbo \ diff --git a/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou-video-demo.d= tso b/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou-video-demo.dtso new file mode 100644 index 0000000000000000000000000000000000000000..7d9ea5aa598486680191d52e4c8= 7af59f7b0e579 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou-video-demo.dtso @@ -0,0 +1,190 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Cherry Embedded Solutions GmbH + * + * DEVKIT ADDON CAM-TS-A01 + * https://embedded.cherry.de/product/development-kit/ + * + * DT-overlay for the camera / DSI demo appliance for Haikou boards. + * In the flavour for use with a Ringneck system-on-module. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include + +&{/} { + backlight: backlight { + compatible =3D "pwm-backlight"; + power-supply =3D <&dc_12v>; + pwms =3D <&pwm0 0 25000 0>; + }; + + cam_afvdd_2v8: regulator-cam-afvdd-2v8 { + compatible =3D "regulator-fixed"; + gpio =3D <&pca9670 2 GPIO_ACTIVE_LOW>; + regulator-max-microvolt =3D <2800000>; + regulator-min-microvolt =3D <2800000>; + regulator-name =3D "cam-afvdd-2v8"; + vin-supply =3D <&vcc2v8_video>; + }; + + cam_avdd_2v8: regulator-cam-avdd-2v8 { + compatible =3D "regulator-fixed"; + gpio =3D <&pca9670 4 GPIO_ACTIVE_LOW>; + regulator-max-microvolt =3D <2800000>; + regulator-min-microvolt =3D <2800000>; + regulator-name =3D "cam-avdd-2v8"; + vin-supply =3D <&vcc2v8_video>; + }; + + cam_dovdd_1v8: regulator-cam-dovdd-1v8 { + compatible =3D "regulator-fixed"; + gpio =3D <&pca9670 3 GPIO_ACTIVE_LOW>; + regulator-max-microvolt =3D <1800000>; + regulator-min-microvolt =3D <1800000>; + regulator-name =3D "cam-dovdd-1v8"; + vin-supply =3D <&vcc1v8_video>; + }; + + cam_dvdd_1v2: regulator-cam-dvdd-1v2 { + compatible =3D "regulator-fixed"; + enable-active-high; + gpio =3D <&pca9670 5 GPIO_ACTIVE_HIGH>; + regulator-max-microvolt =3D <1200000>; + regulator-min-microvolt =3D <1200000>; + regulator-name =3D "cam-dvdd-1v2"; + vin-supply =3D <&vcc3v3_baseboard>; + }; + + vcc1v8_video: regulator-vcc1v8-video { + compatible =3D "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt =3D <1800000>; + regulator-min-microvolt =3D <1800000>; + regulator-name =3D "vcc1v8-video"; + vin-supply =3D <&vcc3v3_baseboard>; + }; + + vcc2v8_video: regulator-vcc2v8-video { + compatible =3D "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt =3D <2800000>; + regulator-min-microvolt =3D <2800000>; + regulator-name =3D "vcc2v8-video"; + vin-supply =3D <&vcc3v3_baseboard>; + }; + + video-adapter-leds { + compatible =3D "gpio-leds"; + + video-adapter-led { + color =3D ; + gpios =3D <&pca9670 7 GPIO_ACTIVE_HIGH>; + label =3D "video-adapter-led"; + linux,default-trigger =3D "none"; + }; + }; +}; + +&display_subsystem { + status =3D "okay"; +}; + +&dsi { + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "okay"; + + panel@0 { + compatible =3D "leadtek,ltk050h3148w"; + reg =3D <0>; + backlight =3D <&backlight>; + iovcc-supply =3D <&vcc1v8_video>; + reset-gpios =3D <&pca9670 0 GPIO_ACTIVE_LOW>; + vci-supply =3D <&vcc2v8_video>; + + port { + mipi_in_panel: endpoint { + remote-endpoint =3D <&mipi_out_panel>; + }; + }; + }; +}; + +&dsi_dphy { + status =3D "okay"; +}; + +&dsi_out { + mipi_out_panel: endpoint { + remote-endpoint =3D <&mipi_in_panel>; + }; +}; + +&i2c1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + /* OV5675, GT911, DW9714 are limited to 400KHz */ + clock-frequency =3D <400000>; + + touchscreen@14 { + compatible =3D "goodix,gt911"; + reg =3D <0x14>; + interrupt-parent =3D <&gpio0>; + interrupts =3D ; + irq-gpios =3D <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + pinctrl-0 =3D <&touch_int>; + pinctrl-names =3D "default"; + reset-gpios =3D <&pca9670 1 GPIO_ACTIVE_HIGH>; + AVDD28-supply =3D <&vcc2v8_video>; + VDDIO-supply =3D <&vcc3v3_baseboard>; + }; + + pca9670: gpio@27 { + compatible =3D "nxp,pca9670"; + reg =3D <0x27>; + gpio-controller; + #gpio-cells =3D <2>; + pinctrl-0 =3D <&pca9670_resetn>; + pinctrl-names =3D "default"; + reset-gpios =3D <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + pca9670 { + pca9670_resetn: pca9670-resetn { + rockchip,pins =3D <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + touch { + touch_int: touch-int { + rockchip,pins =3D <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&vopb { + status =3D "okay"; +}; + +&vopb_mmu { + status =3D "okay"; +}; + +&vopl { + status =3D "okay"; +}; + +&vopl_mmu { + status =3D "okay"; +}; --=20 2.48.1 From nobody Thu Dec 18 16:20:49 2025 Received: from smtp-190d.mail.infomaniak.ch (smtp-190d.mail.infomaniak.ch [185.125.25.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A033E1F4281 for ; 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dmarc=none (p=none dis=none) header.from=0leil.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=0leil.net Received: from smtp-4-0000.mail.infomaniak.ch (unknown [IPv6:2001:1600:7:10:40ca:feff:fe05:0]) by smtp-4-3000.mail.infomaniak.ch (Postfix) with ESMTPS id 4YzsMg2wt0zRTj; Fri, 21 Feb 2025 15:05:03 +0100 (CET) Received: from unknown by smtp-4-0000.mail.infomaniak.ch (Postfix) with ESMTPA id 4YzsMf5Yy2zYKb; Fri, 21 Feb 2025 15:05:02 +0100 (CET) From: Quentin Schulz Date: Fri, 21 Feb 2025 15:04:37 +0100 Subject: [PATCH v2 5/5] arm64: dts: rockchip: add overlay for RK3399 Puma Haikou Video Demo adapter Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250221-ringneck-dtbos-v2-5-310c0b9a3909@cherry.de> References: <20250221-ringneck-dtbos-v2-0-310c0b9a3909@cherry.de> In-Reply-To: <20250221-ringneck-dtbos-v2-0-310c0b9a3909@cherry.de> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Quentin Schulz , Farouk Bouabid Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Quentin Schulz X-Mailer: b4 0.14.2 X-Infomaniak-Routing: alpha From: Quentin Schulz This adds support for the video-demo-adapter DEVKIT ADDON CAM-TS-A01 (https://embedded.cherry.de/product/development-kit/) for the Haikou devkit with RK3399 Puma SoM. The Video Demo adapter is an adapter connected to the fake PCIe slot labeled "Video Connector" on the Haikou devkit. Its main feature is a Leadtek DSI-display with touchscreen and a camera (that is not supported yet because the expected clock rate by the driver cannot be exactly reached by the clock driver). To drive these components a number of additional regulators are grouped on the adapter as well as a PCA9670 gpio-expander to provide the needed additional gpio-lines. Signed-off-by: Quentin Schulz --- arch/arm64/boot/dts/rockchip/Makefile | 5 + .../rockchip/rk3399-puma-haikou-video-demo.dtso | 166 +++++++++++++++++= ++++ 2 files changed, 171 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/ro= ckchip/Makefile index 0f7c5c55c8b8be11e3fd7a69995ce1c17b22c80d..a46ed20e977aedb7cca1a9c0ad1= 5f5441e4fe177 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -63,6 +63,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3399-orangepi.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3399-pinebook-pro.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3399-pinephone-pro.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3399-puma-haikou.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3399-puma-haikou-video-demo.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3399-roc-pc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3399-roc-pc-mezzanine.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3399-roc-pc-plus.dtb @@ -201,6 +202,10 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D px30-ringneck-haikou-= haikou-video-demo.dtb px30-ringneck-haikou-haikou-video-demo-dtbs :=3D px30-ringneck-haikou.dtb \ px30-ringneck-haikou-video-demo.dtbo =20 +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3399-puma-haikou-haikou-video-demo.dtb +rk3399-puma-haikou-haikou-video-demo-dtbs :=3D rk3399-puma-haikou.dtb \ + rk3399-puma-haikou-video-demo.dtbo + dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-wolfvision-pf5-vz-2-uhd.dtb rk3568-wolfvision-pf5-vz-2-uhd-dtbs :=3D rk3568-wolfvision-pf5.dtb \ rk3568-wolfvision-pf5-display-vz.dtbo \ diff --git a/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou-video-demo.dts= o b/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou-video-demo.dtso new file mode 100644 index 0000000000000000000000000000000000000000..0377ec860d35461b7d2d4ee1f20= bdd4a076a5fe6 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou-video-demo.dtso @@ -0,0 +1,166 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Cherry Embedded Solutions GmbH + * + * DEVKIT ADDON CAM-TS-A01 + * https://embedded.cherry.de/product/development-kit/ + * + * DT-overlay for the camera / DSI demo appliance for Haikou boards. + * In the flavour for use with a Puma system-on-module. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include + +&{/} { + backlight: backlight { + compatible =3D "pwm-backlight"; + power-supply =3D <&dc_12v>; + pwms =3D <&pwm0 0 25000 0>; + }; + + cam_afvdd_2v8: regulator-cam-afvdd-2v8 { + compatible =3D "regulator-fixed"; + gpio =3D <&pca9670 2 GPIO_ACTIVE_LOW>; + regulator-max-microvolt =3D <2800000>; + regulator-min-microvolt =3D <2800000>; + regulator-name =3D "cam-afvdd-2v8"; + vin-supply =3D <&vcc2v8_video>; + }; + + cam_avdd_2v8: regulator-cam-avdd-2v8 { + compatible =3D "regulator-fixed"; + gpio =3D <&pca9670 4 GPIO_ACTIVE_LOW>; + regulator-max-microvolt =3D <2800000>; + regulator-min-microvolt =3D <2800000>; + regulator-name =3D "cam-avdd-2v8"; + vin-supply =3D <&vcc2v8_video>; + }; + + cam_dovdd_1v8: regulator-cam-dovdd-1v8 { + compatible =3D "regulator-fixed"; + gpio =3D <&pca9670 3 GPIO_ACTIVE_LOW>; + regulator-max-microvolt =3D <1800000>; + regulator-min-microvolt =3D <1800000>; + regulator-name =3D "cam-dovdd-1v8"; + vin-supply =3D <&vcc1v8_video>; + }; + + cam_dvdd_1v2: regulator-cam-dvdd-1v2 { + compatible =3D "regulator-fixed"; + enable-active-high; + gpio =3D <&pca9670 5 GPIO_ACTIVE_HIGH>; + regulator-max-microvolt =3D <1200000>; + regulator-min-microvolt =3D <1200000>; + regulator-name =3D "cam-dvdd-1v2"; + vin-supply =3D <&vcc3v3_baseboard>; + }; + + vcc1v8_video: regulator-vcc1v8-video { + compatible =3D "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt =3D <1800000>; + regulator-min-microvolt =3D <1800000>; + regulator-name =3D "vcc1v8-video"; + vin-supply =3D <&vcc3v3_baseboard>; + }; + + vcc2v8_video: regulator-vcc2v8-video { + compatible =3D "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt =3D <2800000>; + regulator-min-microvolt =3D <2800000>; + regulator-name =3D "vcc2v8-video"; + vin-supply =3D <&vcc3v3_baseboard>; + }; + + video-adapter-leds { + compatible =3D "gpio-leds"; + + video-adapter-led { + color =3D ; + gpios =3D <&pca9670 7 GPIO_ACTIVE_HIGH>; + label =3D "video-adapter-led"; + linux,default-trigger =3D "none"; + }; + }; +}; + +&i2c1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + /* OV5675, GT911, DW9714 are limited to 400KHz */ + clock-frequency =3D <400000>; + + touchscreen@14 { + compatible =3D "goodix,gt911"; + reg =3D <0x14>; + interrupt-parent =3D <&gpio1>; + interrupts =3D ; + irq-gpios =3D <&gpio1 RK_PC7 GPIO_ACTIVE_HIGH>; + pinctrl-0 =3D <&touch_int>; + pinctrl-names =3D "default"; + reset-gpios =3D <&pca9670 1 GPIO_ACTIVE_HIGH>; + AVDD28-supply =3D <&vcc2v8_video>; + VDDIO-supply =3D <&vcc3v3_baseboard>; + }; + + pca9670: gpio@27 { + compatible =3D "nxp,pca9670"; + reg =3D <0x27>; + gpio-controller; + #gpio-cells =3D <2>; + pinctrl-0 =3D <&pca9670_resetn>; + pinctrl-names =3D "default"; + reset-gpios =3D <&gpio4 RK_PD6 GPIO_ACTIVE_LOW>; + }; +}; + +&mipi_out { + mipi_out_panel: endpoint { + remote-endpoint =3D <&mipi_in_panel>; + }; +}; + +&mipi_dsi { + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "okay"; + + panel@0 { + compatible =3D "leadtek,ltk050h3148w"; + reg =3D <0>; + backlight =3D <&backlight>; + iovcc-supply =3D <&vcc1v8_video>; + reset-gpios =3D <&pca9670 0 GPIO_ACTIVE_LOW>; + vci-supply =3D <&vcc2v8_video>; + + port { + mipi_in_panel: endpoint { + remote-endpoint =3D <&mipi_out_panel>; + }; + }; + }; +}; + +&pinctrl { + pca9670 { + pca9670_resetn: pca9670-resetn { + rockchip,pins =3D <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + touch { + touch_int: touch-int { + rockchip,pins =3D <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; --=20 2.48.1