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[78.11.220.99]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-abbaa56026fsm865456666b.113.2025.02.21.07.24.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2025 07:24:51 -0800 (PST) From: Krzysztof Kozlowski Date: Fri, 21 Feb 2025 16:24:11 +0100 Subject: [PATCH v3 01/21] dt-bindings: display/msm: dsi-controller-main: Combine if:then: entries Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250221-b4-sm8750-display-v3-1-3ea95b1630ea@linaro.org> References: <20250221-b4-sm8750-display-v3-0-3ea95b1630ea@linaro.org> In-Reply-To: <20250221-b4-sm8750-display-v3-0-3ea95b1630ea@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , Jonathan Marek , Kuogee Hsieh , Neil Armstrong Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Srini Kandagatla , Rob Clark X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3023; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=gC/FypNj+ZpUyniZ+8EtOmpEbEyuPuBTmn13DjMHXtU=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBnuJqsgXbxiTLYqR/PSolFrAbqMkllUjvxoL/mo OOMU655pAqJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZ7iarAAKCRDBN2bmhouD 17YvD/wKGo6OfOEhuVfcMzmhFGgg37DWi/RIVXURAzYJ+joeU6L1inAafck7Qy+TNi6sa6k8YO1 fBublLhM8E95wDVz2/WQV6PDZNKInMFryiQ8uIV9DGH4hqdtEMBp8ori6Rb1RTJICbSZWuTjEyp +9pggs6KDS6zo9nqtigeo3Tzcg98GlwsgEISJbA7N+ZfmNi/oNk7FEEdUxJ6FK3n61s9uoEgP3f fW1a/fSYE1ZGgoZ7R9UBXRDmddpNJwIYT32TWF3SJjr+tSXkLOnUKloaDf3FCpe/viuYqusz2f3 muedbNjHozEOgPn3dpTvX6xCOBqgi605kIhmwJxme4fdw73jbYW3OBinFykeIAyosNeaHFwAt/9 bZFl89wn8JGqzw1WpXJ+vPo0E4Y52PExXh8YYS9rSpaiAvZ/XPpoau6LFw2zAXFpuEpQlWK0fKN K81L05zXOa5dw8BFdJPaOXXqcVk08zwTqtxUeRWGP6dYYF8VPPhrdB4mLj56sNxguCHUR18pkW4 HJ8UIhckPvigJQ4xaKWiwMOh1K4YIDf8UwejgyXirT3Xu00G4FBt/LnVt/MJsO6PtzGtbzY5pOj +Uk1USE2aNZrkUR6OusYZaTDOx4n5Vafs9/9NMO3ia2lXDdiWIDh9u7Yj8Hd4CI1Ev2GpyPwC1y kL6N46HexQeM2nw== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Several devices have the same clock inputs, thus they can be in the same if:then: clause, making everything smaller. No functional impact. Reviewed-by: Rob Herring (Arm) Signed-off-by: Krzysztof Kozlowski --- .../bindings/display/msm/dsi-controller-main.yaml | 64 ++----------------= ---- 1 file changed, 5 insertions(+), 59 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-m= ain.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-mai= n.yaml index ffbd1dc9470e2091b477b0c88392d81802119f48..e496e5430918d54b2f07f1d5b64= de85d29256951 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml @@ -248,24 +248,6 @@ allOf: contains: enum: - qcom,msm8916-dsi-ctrl - then: - properties: - clocks: - maxItems: 6 - clock-names: - items: - - const: mdp_core - - const: iface - - const: bus - - const: byte - - const: pixel - - const: core - - - if: - properties: - compatible: - contains: - enum: - qcom,msm8953-dsi-ctrl - qcom,msm8976-dsi-ctrl then: @@ -328,28 +310,13 @@ allOf: contains: enum: - qcom,msm8998-dsi-ctrl - - qcom,sm6125-dsi-ctrl - - qcom,sm6350-dsi-ctrl - then: - properties: - clocks: - maxItems: 6 - clock-names: - items: - - const: byte - - const: byte_intf - - const: pixel - - const: core - - const: iface - - const: bus - - - if: - properties: - compatible: - contains: - enum: - qcom,sc7180-dsi-ctrl - qcom,sc7280-dsi-ctrl + - qcom,sdm845-dsi-ctrl + - qcom,sm6115-dsi-ctrl + - qcom,sm6125-dsi-ctrl + - qcom,sm6350-dsi-ctrl + - qcom,sm6375-dsi-ctrl - qcom,sm6150-dsi-ctrl - qcom,sm7150-dsi-ctrl - qcom,sm8150-dsi-ctrl @@ -393,27 +360,6 @@ allOf: - const: pixel - const: core =20 - - if: - properties: - compatible: - contains: - enum: - - qcom,sdm845-dsi-ctrl - - qcom,sm6115-dsi-ctrl - - qcom,sm6375-dsi-ctrl - then: - properties: - clocks: - maxItems: 6 - clock-names: - items: - - const: byte - - const: byte_intf - - const: pixel - - const: core - - const: iface - - const: bus - unevaluatedProperties: false =20 examples: --=20 2.43.0 From nobody Mon Feb 9 08:04:22 2026 Received: from mail-ed1-f49.google.com (mail-ed1-f49.google.com [209.85.208.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D8BCC212B10 for ; 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Older dtschema implied minItems, but that's not true since 2024 and missing minItems means that lower bound is not set. Reviewed-by: Rob Herring (Arm) Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/display/msm/dsi-controller-main.yaml | 6 ++= ++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-m= ain.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-mai= n.yaml index e496e5430918d54b2f07f1d5b64de85d29256951..2aab33cd0017cd4a0c915b7297b= b3952e62561fa 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml @@ -231,6 +231,7 @@ allOf: then: properties: clocks: + minItems: 7 maxItems: 7 clock-names: items: @@ -253,6 +254,7 @@ allOf: then: properties: clocks: + minItems: 6 maxItems: 6 clock-names: items: @@ -273,6 +275,7 @@ allOf: then: properties: clocks: + minItems: 7 maxItems: 7 clock-names: items: @@ -293,6 +296,7 @@ allOf: then: properties: clocks: + minItems: 7 maxItems: 7 clock-names: items: @@ -328,6 +332,7 @@ allOf: then: properties: clocks: + minItems: 6 maxItems: 6 clock-names: items: @@ -347,6 +352,7 @@ allOf: then: properties: clocks: + minItems: 9 maxItems: 9 clock-names: items: --=20 2.43.0 From nobody Mon Feb 9 08:04:22 2026 Received: from mail-ej1-f41.google.com (mail-ej1-f41.google.com [209.85.218.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 776F2213241 for ; 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[78.11.220.99]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-abbaa56026fsm865456666b.113.2025.02.21.07.24.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2025 07:24:56 -0800 (PST) From: Krzysztof Kozlowski Date: Fri, 21 Feb 2025 16:24:13 +0100 Subject: [PATCH v3 03/21] dt-bindings: display/msm: dsi-phy-7nm: Add SM8750 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250221-b4-sm8750-display-v3-3-3ea95b1630ea@linaro.org> References: <20250221-b4-sm8750-display-v3-0-3ea95b1630ea@linaro.org> In-Reply-To: <20250221-b4-sm8750-display-v3-0-3ea95b1630ea@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , Jonathan Marek , Kuogee Hsieh , Neil Armstrong Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Srini Kandagatla , Rob Clark X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=918; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=g6ZcIsYl2/jMWfZyQs4pXVAtZzsF1td/uQveud5buEk=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBnuJquIDPKcX+Rx7v0CVf58SDbQy7/9H36p4/X/ QyftRnNPe+JAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZ7iargAKCRDBN2bmhouD 16XdD/0T1kAqTkR8/1WysMoQpb12phv708f+gdkkG4acV50G9LWjjqz+b2Ded/v8aPyeo+UTkA2 /t4MDCbN28qtDRJnlqyQfB/SnUxsBePMyNVKJ8J39/4FhyW0EHHm5aFJTGSoBI0WZYJEjoz2WIN ouNcGnvv4jN0SSe0abH0SQMf57qDYiDy09m0gVfxJrXCdlZjFaf1KsCy3gQA7Yj0ZskTbRl9up8 tOLm2OLtDMa3GdZ8DimxLq9iT0qTzXJETfBaCQwptWuW5LbviyZ3YrTH3gz/afgIrjATO0q1p/h I4D3ZbeZokDfAvu+bEmXFeHeym1hu3gbSIaBrjMwheSryMTruJfoYmvmtOM1vUTAVupDGg+DLOg zk7pAt8Tn2AeuuFVk2qXVjxR4aJYD6AjTUTToZukc1/xeYSJnG1aIDCdKksNufm2LnKVn5DD9lP NRU5esfanBdvwmUvDpivrs6BDEFiLY/eHCHhjOTsVWs63nQ+Gf0aV0kvKVjtnJGZIPwTvhsMlM1 zi7s72NCqzbxD7dHbeS0LOEf9Sxf9m2EiUvFnJeubyWbIE8KwG0MWnBqnEycbBaXiwBMh2BjTZB KUKyfNPhkOIRoWP5Mb+mq+i/786xSoWann2Y9gDp4MPmLVE3estoqc2ZcQUrs4swL9N9zE2aanB +pisvvLP96aBSaw== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Add DSI PHY v7.0 for Qualcomm SM8750 SoC which is quite different from previous (SM8650) generation. Acked-by: Rob Herring (Arm) Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml= b/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml index 321470435e654f1d569fc54f6a810e3f70fb168c..4ac262d3feb1293c65633f3b804= b4f34c518400c 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml @@ -23,6 +23,7 @@ properties: - qcom,sm8450-dsi-phy-5nm - qcom,sm8550-dsi-phy-4nm - qcom,sm8650-dsi-phy-4nm + - qcom,sm8750-dsi-phy-3nm =20 reg: items: --=20 2.43.0 From nobody Mon Feb 9 08:04:22 2026 Received: from mail-ej1-f49.google.com (mail-ej1-f49.google.com [209.85.218.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6294521147A for ; Fri, 21 Feb 2025 15:25:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740151502; cv=none; b=Oct6HsjfoYH1InQSHoHbSRz1TaYJ1YmhwCshlFOJ/GmYcKgnw1rD/WYd1CHpnM0yZlZizE29BYgIiRJL4viRq2YZnqwuYreS0wMduCMBvkBLifb6ZQD//NqeWiMkaB2guy7oLZy8CkqyC/fs4DTbSdIzNvNROb0gCKHfxpZzQ5E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740151502; c=relaxed/simple; bh=sQUir1TiVRbtsw+Rrr4J2GdnerWUccENvKyAuylyDIY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=rCxqSwjJcjdXvyTTjhLd7M+N5WXBo7SB01GwiNcSE3LPVQAvxJKX2pB0Q7p0cy0//a69s28j2R+1mkAGF49+v00lpI8JiGH0QFSoxac5oun8GSqpbaQaFegECBvjRltbCgHnGY8yKx0dd55Qs7aPw+OC7G3+jSuwrjfmD4usSog= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=fHKRSssL; arc=none smtp.client-ip=209.85.218.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="fHKRSssL" Received: by mail-ej1-f49.google.com with SMTP id a640c23a62f3a-ab7098af6fdso34127166b.2 for ; Fri, 21 Feb 2025 07:25:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1740151499; x=1740756299; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=ysi0JDUh4a5HDZVHMcgvLzjscdPZigz8vY2N2CGO+pI=; b=fHKRSssLmmiVjyYWTOl7xjS082hFKqwhXNT0ifvd33ml3CYKEmpWHW+Y1nAA9xWMZ1 tX0lmDqIGCbSp9JXB+juWYv40McQC4f93bEM+7A6t1RGQfaR4qdqKXB17p9FLpe3PiVb SUtgng9Pgz2n9sJ3jCfTaHVMzw/O+RYWtfOmvOuQ8Em/CyyHIzeZEgg57tsbZb0SrwoM GfVWriavQCWx/tZYtikSU0MHTeGuX9Z9Q73uE2yhK6GpGPvToGZBMcN6/PxDqVYFx55x b5N/7Z6nsaIOtXXAltXnCDn1Q0nbVp0elC0mfqvhgGx0VID6jodMjNLvYsldNGHKjDfe eNRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740151499; x=1740756299; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ysi0JDUh4a5HDZVHMcgvLzjscdPZigz8vY2N2CGO+pI=; b=PmRnjNd0Uc39/DP3eTBfLhaXq5GyHCx9MMV4EvQ/5Ito45I3oSiCcSXU2AUI/OpZoN EAw1QbrICw7ZjqtGDAuTNpIifK9whAMKbYwfDS8oK6uxsykeyv1cm5x4Jgll69CBGmX1 tWuEH8V0TGh0sE+x84dMZrN3wg/0R+xBok3V5W6ZbKLkhzWOVxhcUDeOvQR07GaZeXOx ARJlq3gPc4NlBQlYEIaB9mQinIuCIbMkw5hwpdCY8cVBMwuXK3txwHV6e0uK241ylR7d ECLkH9bmZKdlyL5M+QEjwVkY1vkOEgUpiKO/aIaAYk2c9KAKe4lsIEXToCvUDMq/o0QV dj5A== X-Forwarded-Encrypted: i=1; AJvYcCU89C+ShzUL8bwiRGsjQxMh0ehwFPVaDRqg1wtyIWh3I+sqY2Trltwrg5bbs90tbMh2S+Z7SYQby3HiTjM=@vger.kernel.org X-Gm-Message-State: AOJu0Yx7hPDBTDas/KtHGqcHRGZBr+9NKpbgCV4KofcCQ0GSTQRTvYIW Z20O881z01yXRhGJFOXzD38d5eim4OcvVGlFWuEtYDSWJXwbGwHjTaiwOniWyp4= X-Gm-Gg: ASbGnculsE+IPUsGsKiSEseYXhMsweJGoRXuTi5g396qmRjCIlWaC2O19fO8mF4LIMo vJw1djmqQmy/8cAsrV8zs/cMhwl9fvO6UYzchS8bTDaVtvhGDQl8iBbWpaGkW/vFa4v4xZy/wch KQKng1K8UAizX93CQyHjNkMF5JRrqkmOch0YbEPDRzG9BJVX/sqf2434+yuKcYlRWWy6T+b2tFF dIGeWShfZJhOwjRDPrGrCSgCsebgHRKKxN/8ufCnae3q1EJ4kwZRVU31ptwZpW7KFAUu/vfVG5l QzSHR7g5hSVl8JWD4ttRrCutUbAcK+InJ67fvnwSTfNfoBBT82f6/uhAVQ5HfePJ4j7PEOsEFBB l X-Google-Smtp-Source: AGHT+IFKiCGs8WGJjCjTwDeH5gItqV3Z4eBJ2EseKZT54AU+egPgFTE16MYl1DUKy6/45OfK9TlWOQ== X-Received: by 2002:a17:907:2d22:b0:ab3:8bcc:3d97 with SMTP id a640c23a62f3a-abc09a46c73mr147170066b.5.1740151498576; Fri, 21 Feb 2025 07:24:58 -0800 (PST) Received: from [127.0.1.1] (78-11-220-99.static.ip.netia.com.pl. [78.11.220.99]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-abbaa56026fsm865456666b.113.2025.02.21.07.24.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2025 07:24:58 -0800 (PST) From: Krzysztof Kozlowski Date: Fri, 21 Feb 2025 16:24:14 +0100 Subject: [PATCH v3 04/21] dt-bindings: display/msm: dsi-controller-main: Add SM8750 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250221-b4-sm8750-display-v3-4-3ea95b1630ea@linaro.org> References: <20250221-b4-sm8750-display-v3-0-3ea95b1630ea@linaro.org> In-Reply-To: <20250221-b4-sm8750-display-v3-0-3ea95b1630ea@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , Jonathan Marek , Kuogee Hsieh , Neil Armstrong Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Srini Kandagatla , Rob Clark X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=4373; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=sQUir1TiVRbtsw+Rrr4J2GdnerWUccENvKyAuylyDIY=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBnuJqvbfkL6mifLhnkJ8uZyWrdVvqdxgfUK+3Eg sWqITQW+uqJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZ7iarwAKCRDBN2bmhouD 17ScD/0WhW0eY92Rf1M1qxmQ9bWlOi0q6oHKlhME2auE7BpgsJHCJtPsQFg8ZCPpnVkwDPXU7Kj JE45JCNTiIcbBznrQaw57ao2XQTnW2WgrpEAeFcRbvdUaeOWhZlkbQ762LGD36nlUiYAQixXTRj TtaVv9vO9IlnUQ2Ej4cg1r0ByY29f4pnY3z65T6kVLVFruL92YrR6btwijpiyuqJeWpXxyS2NvY ZtTis85EqKruB+RIwxjGmFIHytjTkUffiliCYFEcKAHRx8upuqW0NuKGCAjW5Vna2uq11Jx3hxg XowEPVduEhaa9+QqAJF5Ir4FK/Sh3msX4sPdUmTJ2Or1QB55OLVbyyGX9lDwS1ochXYyk1Buef3 gtzfMmHj/fmECtg+RGU6Njb95awMv4OqzRczYUeluLUxAOyOp476LAQwcVrySnyA3jLzBt1xtI3 ArRRs1sFbOiFfyZcyWeiMeVpD91yyCj0Vo1ewChFxFmHvF/qq3lhRoEHGTG6eyFguI1Adjsl1ok DJ1TIxO/JHORazEkOrtHImUUVPy/e9Zak56HRdyQa3X1jfbGtqKWhKEO2xpcvLIzSasjQ5jyMb+ +deP5RYyfejTHOxRlHCyWcSJL9xC6KzyO/iqmVKqHdS4G+1bWitDFHeZYEXtn39FSJsnqNUK3bg Z/OoH8n7yIpfFeA== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Add DSI controller for Qualcomm SM8750 SoC which is quite different from previous (SM8650) generation. It does not allow the display clock controller clocks like "byte" and "pixel" to be reparented to DSI PHY PLLs while the DSI PHY PLL is not configured (not prepared, rate not set). Therefore assigned-clock-parents are not working here and driver is responsible for reparenting clocks with proper procedure. These clocks are now inputs to the DSI controller device. Except that SM8750 DSI comes with several differences, new blocks and changes in registers, making it incompatible with SM8650. Reviewed-by: Rob Herring (Arm) Signed-off-by: Krzysztof Kozlowski --- .../bindings/display/msm/dsi-controller-main.yaml | 54 ++++++++++++++++++= ++-- 1 file changed, 49 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-m= ain.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-mai= n.yaml index 2aab33cd0017cd4a0c915b7297bb3952e62561fa..8ecb2d8e296edf555df7380eac2= 84b41a3f000a5 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml @@ -40,6 +40,7 @@ properties: - qcom,sm8450-dsi-ctrl - qcom,sm8550-dsi-ctrl - qcom,sm8650-dsi-ctrl + - qcom,sm8750-dsi-ctrl - const: qcom,mdss-dsi-ctrl - enum: - qcom,dsi-ctrl-6g-qcm2290 @@ -68,11 +69,11 @@ properties: - mnoc:: MNOC clock - pixel:: Display pixel clock. minItems: 3 - maxItems: 9 + maxItems: 12 =20 clock-names: minItems: 3 - maxItems: 9 + maxItems: 12 =20 phys: maxItems: 1 @@ -107,7 +108,8 @@ properties: minItems: 2 maxItems: 4 description: | - Parents of "byte" and "pixel" for the given platform. + For DSI on SM8650 and older: parents of "byte" and "pixel" for the g= iven + platform. For DSIv2 platforms this should contain "byte", "esc", "src" and "pixel_src" clocks. =20 @@ -216,8 +218,6 @@ required: - clocks - clock-names - phys - - assigned-clocks - - assigned-clock-parents - ports =20 allOf: @@ -242,6 +242,9 @@ allOf: - const: byte - const: pixel - const: core + required: + - assigned-clocks + - assigned-clock-parents =20 - if: properties: @@ -264,6 +267,9 @@ allOf: - const: byte - const: pixel - const: core + required: + - assigned-clocks + - assigned-clock-parents =20 - if: properties: @@ -286,6 +292,9 @@ allOf: - const: pixel - const: core - const: core_mmss + required: + - assigned-clocks + - assigned-clock-parents =20 - if: properties: @@ -307,6 +316,9 @@ allOf: - const: core_mmss - const: pixel - const: core + required: + - assigned-clocks + - assigned-clock-parents =20 - if: properties: @@ -342,6 +354,35 @@ allOf: - const: core - const: iface - const: bus + required: + - assigned-clocks + - assigned-clock-parents + + - if: + properties: + compatible: + contains: + enum: + - qcom,sm8750-dsi-ctrl + then: + properties: + clocks: + minItems: 12 + maxItems: 12 + clock-names: + items: + - const: byte + - const: byte_intf + - const: pixel + - const: core + - const: iface + - const: bus + - const: dsi_pll_pixel + - const: dsi_pll_byte + - const: esync + - const: osc + - const: byte_src + - const: pixel_src =20 - if: properties: @@ -365,6 +406,9 @@ allOf: - const: core_mmss - const: pixel - const: core + required: + - assigned-clocks + - assigned-clock-parents =20 unevaluatedProperties: false =20 --=20 2.43.0 From nobody Mon Feb 9 08:04:22 2026 Received: from mail-ej1-f48.google.com (mail-ej1-f48.google.com [209.85.218.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 360E121481A for ; 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[78.11.220.99]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-abbaa56026fsm865456666b.113.2025.02.21.07.24.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2025 07:24:59 -0800 (PST) From: Krzysztof Kozlowski Date: Fri, 21 Feb 2025 16:24:15 +0100 Subject: [PATCH v3 05/21] dt-bindings: display/msm: dp-controller: Add SM8750 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250221-b4-sm8750-display-v3-5-3ea95b1630ea@linaro.org> References: <20250221-b4-sm8750-display-v3-0-3ea95b1630ea@linaro.org> In-Reply-To: <20250221-b4-sm8750-display-v3-0-3ea95b1630ea@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , Jonathan Marek , Kuogee Hsieh , Neil Armstrong Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Srini Kandagatla , Rob Clark X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1154; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=9B2Xq7lYY3q6Y8LyOgUlIBLiX0qqdACiJxxNpgXSDG4=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBnuJqwYmhjNiJz64m3Odm70ow8pEs9DwcSnwYWo JzWPq3daK+JAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZ7iasAAKCRDBN2bmhouD 107JD/0cDnFr4AxqzNmIIFy59u6RC8j9KAubzvu979pw6xQXoaAnXSToTCm/VZ0zgpRsKmVhUK5 U8RDOJB/OmjKsL+TB/JFnE9n5qEVJkyrXdtIyIqb72sisTuAIH9KWIfZH7L9eGO5tb7R1ZeZ6aC yABdqEWnFASosGW07EiRLchCNtBxYBuG2xzOwnWjT0kTE/o65oR1xI99JvWnUNbsSwzHdbhRdqO /gnlkLYxV8/DtgrWiTUUU/AOh2wASm36b1UxnD0jyfPsgi/DJ7dLRW5VwIuawTtpF1lwWiDHwV7 pNqlHN+z10FQcM9+3JYvtLo1BObW7LCoOxLT5DcULqY5g++QR83Ge+vvRUG5yMlOtTmc9f7/I2d JyP+8S0mkVsMJI6f4benMJTa/VcZ6UQ2tD9ZasTGoRmzIN3PrZVqlsecR6i+28sk00Z2l0BfJ5y zm5DwXaVG/AJ7kZ8CwVH5QxDIMGClQBp2WGnLJLfAJh3zMwkqOVB7gY6YJRJKf19wIkOkgP7PEj DIGT9L9iLkN7z4pj+sVHJus/LV9oOyz5vkpNPaQqaOvyPqws9r9si75nGzW0+a1m80PfrDnPwry K+I/C64RDpWjqObRBg/p4SoKg7JAmR3e+Kz7pDKinJvlrbSC6nXOF7ZLZgJkzpXHsYhrzbXT9aa h5dhsXxkxEiRthw== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Add DisplayPort controller for Qualcomm SM8750 SoC which so far looks fully compatible with earlier SM8650 variant - both are of version v1.5.1 of the IP block. Datasheet also mentions that both support 4x MST for DPTX0 and 2x MST for DPTX1. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring (Arm) --- Changes in v3: 1. Extend commit msg --- Documentation/devicetree/bindings/display/msm/dp-controller.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.ya= ml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml index e00b88332f2fed2fc33f6d72c5cc3d827cd7594e..a4bf9e07a28355c0391d1757fab= 16ebe5ff14a44 100644 --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml @@ -37,6 +37,10 @@ properties: - qcom,sm8450-dp - qcom,sm8550-dp - const: qcom,sm8350-dp + - items: + - enum: + - qcom,sm8750-dp + - const: qcom,sm8650-dp =20 reg: minItems: 4 --=20 2.43.0 From nobody Mon Feb 9 08:04:22 2026 Received: from mail-ej1-f44.google.com (mail-ej1-f44.google.com [209.85.218.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ED5D5215052 for ; Fri, 21 Feb 2025 15:25:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740151505; cv=none; b=lYMfGlo2Y8nxr8/R53kg9csazkP1Rqyxt3NtkcOymkV5YTTQjpWEMr5CyIiHlcWOsIxSuX93N0KPDrtu7dIerbfQiXNlIyH6MGlDpEwLh7hEyEDQkSFaJQE+g3NqzfKHooWtW7jsJvY6hwc3ETZAW+8WJiUz42ojm74p1XjrGks= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740151505; c=relaxed/simple; bh=vM/Rhh3m/LDu1luem1JmpPvieCwNMZVHKpBxAm5wGsQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=AGKUl7Y1/eKU8GcY26RG+rOjNrBa5l4FVkQIByFhyZSumOig86mBBEVrZsY55OXQdSujMagIm/35deBIxp8nWgEFx/WAvkAc5XGrPMbSXm0nqJV5DxrR49DyY2OFLtLPikf6MJP0530OP+hy5uXZRvCfar4U6FWMxft8YnS8gq4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=efBoMt0N; arc=none smtp.client-ip=209.85.218.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="efBoMt0N" Received: by mail-ej1-f44.google.com with SMTP id a640c23a62f3a-abc28af1ba4so3127166b.1 for ; Fri, 21 Feb 2025 07:25:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1740151502; x=1740756302; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=FX08Ji8HI3+KbtFLo37LoGENRgVWTP1rrMFXfNP52RU=; b=efBoMt0NLPT8jrQQfyVgmzP5oewRUdasxn12YU6jseLk/TE6SMVvhjyk5lkFVaYAgb K3YWIvnZ6l8/dk+xvWHu3ibPkYypp7eBWgy0nqWeXWZSv4eVb2glnkafCiwrWdOnH+2s Hd8FaiMn/Ym0XBD4x1Ii71N4CMl3AcCV+fpzuGhH5SLjd68RLiDVw+TJHSMh5ld1zaUD 5QXdltpK5kLDIDgJEyJLE0xUGaMxtfoF5My0iHv5zySqZrOs14GwxMTDvAODeUVWadsO VrS/l5EcD4EkuvISBfZwNCLql2m3NNNGJVO4NOEqoetg7IhiD0gkK9iPZWtZ3UkNYWzC n1xg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740151502; x=1740756302; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FX08Ji8HI3+KbtFLo37LoGENRgVWTP1rrMFXfNP52RU=; b=UDU9KO0qsZBFwp6cSOqmLXPVvXgsR3P26GRqQX3T60HY2BdDAET39Q33hgHpZOKW+t SzLYcgg195z4MeExZN9uyT0vtnlOcM3/8cmGGUKVBafgPxpNqMG7Jl0+b0He/Z/8Gw3i Nww0v6MpnjT+2BBZWtRDxKLaIgBRwnpoOVH+zfI6KToKyPOD4B3fe8Pi/OEUEVWN1xEb ZSWze7QjAsd2mI1VDtRFKrA15GWZ3yMNfzB+RYODwnfMUZEOswK2qjjQu3UMMCkiSbXZ FysUsTitocNY+3peIR8Sxv1f+sAvSQZ7xBYDaDKPn28lznPH6pXuSO+V/TfEYJRX1qV2 uwHA== X-Forwarded-Encrypted: i=1; AJvYcCXQ47oEEkOuNsaTr7+xTxR2n4xMd4lDVOEaevNAPeen6VotBs2CwuWd4gdF18uTzJ6JA/+om3hkia8YS6w=@vger.kernel.org X-Gm-Message-State: AOJu0YzhJgCZ1hnBWtopOX/ic/WARykFJDklaqfNc1EZdkPUzdhNw8uW 2/F5chFURTs9hiBhCIOSvIVbuWa0BhxIwId2SKfXkYNnrgiYJ+wGc9/pgFWG3cU= X-Gm-Gg: ASbGncsQSgDulXLgwQl86u1meaPEqQwwY8pLuM2gOmlrlXPYh81HXyLPCC9SXg6fXXL wIh/PZ0W0x76uD4TdHPkLVPsh9QYPK4SQIMZqTR5tIbINeJDNmu9WypHexRc5aSxBoJWLICUbby V8iqm6uDJIGZxiupgQPaeWV20UIP2rWhDHPGYjPplWlXCtZQlmtpg4N+yz/Y2KQCozejPhUBW5Y 1yJC+iD51vi39yRmjEw0oZhgdKBmpf2KoAveWK9F6HDs4GU0Lw1yehGB5C/Dq7sFevvExS+MK6o CyUQO/z+spJdqxbcjjuDq18W1JGkrwTW1GK82ZtdQtdk32KVM7eYm/Am2Bzs4YELVa3YEFL2Mny H X-Google-Smtp-Source: AGHT+IF8JcIcNLGFatnCq0HaW0NuMPpymfwFQbEEmh3gv2V8ShCQQ5aDqao2hSWR/5S30IuJoRYTIg== X-Received: by 2002:a17:907:3d8e:b0:ab3:2719:ca30 with SMTP id a640c23a62f3a-abc09bcce60mr159917666b.10.1740151502274; Fri, 21 Feb 2025 07:25:02 -0800 (PST) Received: from [127.0.1.1] (78-11-220-99.static.ip.netia.com.pl. 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Acked-by: Rob Herring (Arm) Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.= yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml index 01cf79bd754b491349c52c5aef49ba06e835d0bf..0a46120dd8680371ed031f77738= 59716f49c3aa1 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml @@ -16,6 +16,7 @@ properties: enum: - qcom,sa8775p-dpu - qcom,sm8650-dpu + - qcom,sm8750-dpu - qcom,x1e80100-dpu =20 reg: --=20 2.43.0 From nobody Mon Feb 9 08:04:22 2026 Received: from mail-ed1-f46.google.com (mail-ed1-f46.google.com [209.85.208.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F183B215168 for ; Fri, 21 Feb 2025 15:25:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740151508; cv=none; b=LlD1V8VSlF9Q8vdJA9Q+zUe9qfL4AOa8e6AP4XoiaGgK7euTyWgNP2HoOi51RWwq567FdvPSuv5aTayXeKHQYkj7P6nvNIjJY+0anRiNFbfCmyvfUFSkxmf5QtiUIHfwpVDHNsXs7e1xoOWVGyAgg1ydaFjodFsbQayojoVrplQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740151508; c=relaxed/simple; bh=wZEy10XWng36e9N/v0rKhcbuOgkJPVqzkbBcz1ZB2jc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=MgXl1in0Wry3Oo9Zh9dbMgNczEh8c8fAPFRSe1Q1YB/TdLTMJ5TcCYsAI67h0a1BVXB4Jm8Rx0BHM4fK95pLyNqhCQ4R5EMzpEU0HvAghVkQch7of8y2Sr4rnsdzNLYlc6eH7/I5/2lJ9VkgcLvO/tx6rcM/gQKLIgYY5IpH6QA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=AXACGM42; arc=none smtp.client-ip=209.85.208.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="AXACGM42" Received: by mail-ed1-f46.google.com with SMTP id 4fb4d7f45d1cf-5ded7cb613eso385796a12.2 for ; Fri, 21 Feb 2025 07:25:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1740151504; x=1740756304; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=cuS5987ZdsbAzrWf4NX4ijDV4g2+JStMbMpBq2iY/b8=; b=AXACGM42i8843Y8JwzHdwXsvTc4FrdA96wlzpGEpxuNsBEkhmfioknQdK7jvp27yUv Es1T+SPsYa/m2hHoG+oz8HOL/dTLi9W3Nyewe69R5OpIC1NIxKIwe/4Y62bbWYvJgFv9 k3ZhjyNSFHnxH+blO1nA3vWrD+nKD3RVCJy5xgLKXbj1K0u/h+wci36b3pOhnTByuGFz MVYCgcQrALOblNXj+L1msFCjX6m9aIR1xCWh7mnonjTuCyIhLu0Xg4SM/Pe85Wp+DPdc xdCxyQxVCCotgVNYS1wIuckfvjm1m6xAqE6jfptBujL7tpmNXXIirR17g7sPbgLC7yh7 2EOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740151504; x=1740756304; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cuS5987ZdsbAzrWf4NX4ijDV4g2+JStMbMpBq2iY/b8=; b=GUIJsGbKSiRhROL8gG4F3VVcfGiNSR0DyhpBqMEEQZ1C7AnmNcdQNq1gedHn6qM9Dj QX/fcnnASuedyWagwc+xq0NuNVY+AUpqXiyAgRdFBykoj26N62sO9ArUjgHmw30svPn0 GQfEHeF+OV62B+zB+ZwhINmoNt7fxhYZW0NBIPT040tlEIGALjt4q+ixiMyV59wP7VDG bepDlCdt3+c9NvjQK4GhP1Ayg1LClnObJOk3MPWeh89/rNx3+evkmRFyCXWEcCCVLZ75 fB1dcjLbWK6cVTvrNuSzprBJcx6WvIY9X6kWQt2ri5JnzJ2ottiN9N2347Duq+Fj2yfZ rN/A== X-Forwarded-Encrypted: i=1; AJvYcCV3UWqxoE5pum+fzx/Bjs9NoeX7HGe3HPhNKjXoCdN74Pke+ArQHd+LKaLFSCIBDxy0/tzaL1Si9wfiw0w=@vger.kernel.org X-Gm-Message-State: AOJu0YwTaYQBGOGE3mgFUnlQMansWNdpYloN0mFO9iPqIOdccqB+Zt/J D3OGjnZupNHzd8Zso44zKqSN1pdp61SZBULWULAqTRtLP3ai/rfKLkH3hhq9LcU= X-Gm-Gg: ASbGncuOktIsJ2bN40BuQAEq+0fsr/e7gEMTeC2q6XNIqsM+KgPZfFSDtDqAm8nqGvg tQj9LKlHvSK2DUaB6jha3dBYWCExNjw/jFa8QKi28YWJ/QKzr7wItdS86PUU4Z4zK3Kne/tjVH4 NJjlpXd8Ox0daVoGZdFgtLKa+hfWI2jEnvitFeP8uCBtv0OO7PROGJqMQSzfA9IrQ6b4he4fhBD AVMd7huzxy0sAtTMuQSkedxPwtxdvTawVORpOEpXCRFKtgdmhXqTM6+6FJflt+n5s7UcXEa+Zs1 t68r2iFXSvGgZu4Whm89q+dTMz8DJW6Tp2MS6FlCIdonwGOVDFSqHhQ8DmjCJteIe8WBn/mdw+T A X-Google-Smtp-Source: AGHT+IGA3J3487EIworyl0F5i+16Dhf+9rDnDHHMPYnJyvjtnVv9i8ylcuaxK8N01iWEvvlF/AmJgA== X-Received: by 2002:a05:6402:50ce:b0:5e0:36c9:7605 with SMTP id 4fb4d7f45d1cf-5e0b6fdcccemr1184592a12.0.1740151504138; Fri, 21 Feb 2025 07:25:04 -0800 (PST) Received: from [127.0.1.1] (78-11-220-99.static.ip.netia.com.pl. [78.11.220.99]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-abbaa56026fsm865456666b.113.2025.02.21.07.25.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2025 07:25:03 -0800 (PST) From: Krzysztof Kozlowski Date: Fri, 21 Feb 2025 16:24:17 +0100 Subject: [PATCH v3 07/21] dt-bindings: display/msm: qcom,sm8750-mdss: Add SM8750 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250221-b4-sm8750-display-v3-7-3ea95b1630ea@linaro.org> References: <20250221-b4-sm8750-display-v3-0-3ea95b1630ea@linaro.org> In-Reply-To: <20250221-b4-sm8750-display-v3-0-3ea95b1630ea@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , Jonathan Marek , Kuogee Hsieh , Neil Armstrong Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Srini Kandagatla , Rob Clark X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=16823; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=wZEy10XWng36e9N/v0rKhcbuOgkJPVqzkbBcz1ZB2jc=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBnuJqyjzhmEhiddP+0ejEe5XQu/g+OSk5Z7udKa p57fcqF4G+JAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZ7iasgAKCRDBN2bmhouD 16+2D/9XhT2MuaxqtHctRbhN9Het1YBdrrKX/4Ax4IcBerZSVYjY5GSBCeNyBswO7I1OH8sTG37 yFTyA41+3tOUdNbf1cua4oYRHxKC8yL63qvlrbKPdUrGaoauJntoVfIkm5nbwB5tqf2M6f7GTRz c6M1MRnTMhM5D7Ue8bzR7gJYZ6wHqui2LbrPxrp/dCprkMJ9zIfJBnJH55jiTB3XN1cbyarjPe5 uoOVMF+rZakO305SCKSK5BK5lPRujMSiwn/cJcScwTLk0x2zL0txYxuDnbiVih3R4usQzyOH6jE pjjN96yH6vXa3sb+E56nq52Tjxng8ik8P0jE/ptXN6t9XCYmTIT4g4F2RRwO09y/t+w9m+CJdNl yDg9CV+ybGN1Dkj60GhLtkJmnRJHHR1/qgDcIS6mBztT/bV1snpwtlgvKzwk0KukZMQLVn/uBxy 3MHYTAjPONVYoTgU7U9g9B+008yskF/x7twyvKX0i56rRZBgHo8jIUa/P2UyhnV9joXAO9TUTET VcaT75Vg066msUukSNNCuc141lkUsgbIrDE/gyGejtk7DX4BnsFFPNiGLD10KjINdviumCU34Sw ESt3oBKX9PZN1WO3N9L7H6Jq/EraBLblbewS5h4yF4IqoTHrOLHdJue0DZTDAPChMy+txQdR9Ql FH0GH0ZC1INJgiQ== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Add MDSS/MDP display subsystem for Qualcomm SM8750 SoC, next generation with two revisions up of the IP block comparing to SM8650. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Rob Herring (Arm) --- Changes in v3: 1. Properly described interconnects 2. Use only one compatible and contains for the sub-blocks (Rob) --- .../bindings/display/msm/qcom,sm8750-mdss.yaml | 470 +++++++++++++++++= ++++ 1 file changed, 470 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8750-mdss= .yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8750-mdss.yaml new file mode 100644 index 0000000000000000000000000000000000000000..72c70edc1fb01c61f8aad24fdb5= 8bfb4f62a6e34 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8750-mdss.yaml @@ -0,0 +1,470 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm8750-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8750 Display MDSS + +maintainers: + - Krzysztof Kozlowski + +description: + SM8650 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks= like + DPU display controller, DSI and DP interfaces etc. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + const: qcom,sm8750-mdss + + clocks: + items: + - description: Display AHB + - description: Display hf AXI + - description: Display core + + iommus: + maxItems: 1 + + interconnects: + items: + - description: Interconnect path from mdp0 port to the data bus + - description: Interconnect path from CPU to the reg bus + + interconnect-names: + items: + - const: mdp0-mem + - const: cpu-cfg + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + const: qcom,sm8750-dpu + + "^displayport-controller@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + contains: + const: qcom,sm8750-dp + + "^dsi@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + contains: + const: qcom,sm8750-dsi-ctrl + + "^phy@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + const: qcom,sm8750-dsi-phy-3nm + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + #include + + display-subsystem@ae00000 { + compatible =3D "qcom,sm8750-mdss"; + reg =3D <0x0ae00000 0x1000>; + reg-names =3D "mdss"; + + interrupts =3D ; + + clocks =3D <&disp_cc_mdss_ahb_clk>, + <&gcc_disp_hf_axi_clk>, + <&disp_cc_mdss_mdp_clk>; + + interconnects =3D <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIV= E_ONLY + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_AC= TIVE_ONLY>; + interconnect-names =3D "mdp0-mem", + "cpu-cfg"; + + resets =3D <&disp_cc_mdss_core_bcr>; + + power-domains =3D <&mdss_gdsc>; + + iommus =3D <&apps_smmu 0x800 0x2>; + + interrupt-controller; + #interrupt-cells =3D <1>; + + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + + display-controller@ae01000 { + compatible =3D "qcom,sm8750-dpu"; + reg =3D <0x0ae01000 0x93000>, + <0x0aeb0000 0x2008>; + reg-names =3D "mdp", + "vbif"; + + interrupts-extended =3D <&mdss 0>; + + clocks =3D <&gcc_disp_hf_axi_clk>, + <&disp_cc_mdss_ahb_clk>, + <&disp_cc_mdss_mdp_lut_clk>, + <&disp_cc_mdss_mdp_clk>, + <&disp_cc_mdss_vsync_clk>; + clock-names =3D "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks =3D <&disp_cc_mdss_vsync_clk>; + assigned-clock-rates =3D <19200000>; + + operating-points-v2 =3D <&mdp_opp_table>; + + power-domains =3D <&rpmhpd RPMHPD_MMCX>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + dpu_intf1_out: endpoint { + remote-endpoint =3D <&mdss_dsi0_in>; + }; + }; + + port@1 { + reg =3D <1>; + + dpu_intf2_out: endpoint { + remote-endpoint =3D <&mdss_dsi1_in>; + }; + }; + + port@2 { + reg =3D <2>; + + dpu_intf0_out: endpoint { + remote-endpoint =3D <&mdss_dp0_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-207000000 { + opp-hz =3D /bits/ 64 <207000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-337000000 { + opp-hz =3D /bits/ 64 <337000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-417000000 { + opp-hz =3D /bits/ 64 <417000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + + opp-532000000 { + opp-hz =3D /bits/ 64 <532000000>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + + opp-575000000 { + opp-hz =3D /bits/ 64 <575000000>; + required-opps =3D <&rpmhpd_opp_nom_l1>; + }; + }; + }; + + dsi@ae94000 { + compatible =3D "qcom,sm8750-dsi-ctrl", "qcom,mdss-dsi-ctrl= "; + reg =3D <0x0ae94000 0x400>; + reg-names =3D "dsi_ctrl"; + + interrupts-extended =3D <&mdss 4>; + + clocks =3D <&disp_cc_mdss_byte0_clk>, + <&disp_cc_mdss_byte0_intf_clk>, + <&disp_cc_mdss_pclk0_clk>, + <&disp_cc_mdss_esc0_clk>, + <&disp_cc_mdss_ahb_clk>, + <&gcc_disp_hf_axi_clk>, + <&mdss_dsi0_phy 1>, + <&mdss_dsi0_phy 0>, + <&disp_cc_esync0_clk>, + <&disp_cc_osc_clk>, + <&disp_cc_mdss_byte0_clk_src>, + <&disp_cc_mdss_pclk0_clk_src>; + clock-names =3D "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus", + "dsi_pll_pixel", + "dsi_pll_byte", + "esync", + "osc", + "byte_src", + "pixel_src"; + + operating-points-v2 =3D <&mdss_dsi_opp_table>; + + power-domains =3D <&rpmhpd RPMHPD_MMCX>; + + phys =3D <&mdss_dsi0_phy>; + phy-names =3D "dsi"; + + vdda-supply =3D <&vreg_l3g_1p2>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + mdss_dsi0_in: endpoint { + remote-endpoint =3D <&dpu_intf1_out>; + }; + }; + + port@1 { + reg =3D <1>; + + mdss_dsi0_out: endpoint { + remote-endpoint =3D <&panel0_in>; + data-lanes =3D <0 1 2 3>; + }; + }; + }; + + mdss_dsi_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-187500000 { + opp-hz =3D /bits/ 64 <187500000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz =3D /bits/ 64 <300000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz =3D /bits/ 64 <358000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + mdss_dsi0_phy: phy@ae95000 { + compatible =3D "qcom,sm8750-dsi-phy-3nm"; + reg =3D <0x0ae95000 0x200>, + <0x0ae95200 0x280>, + <0x0ae95500 0x400>; + reg-names =3D "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + clocks =3D <&disp_cc_mdss_ahb_clk>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "iface", + "ref"; + + vdds-supply =3D <&vreg_l3i_0p88>; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + }; + + dsi@ae96000 { + compatible =3D "qcom,sm8750-dsi-ctrl", "qcom,mdss-dsi-ctrl= "; + reg =3D <0x0ae96000 0x400>; + reg-names =3D "dsi_ctrl"; + + interrupts-extended =3D <&mdss 5>; + + clocks =3D <&disp_cc_mdss_byte1_clk>, + <&disp_cc_mdss_byte1_intf_clk>, + <&disp_cc_mdss_pclk1_clk>, + <&disp_cc_mdss_esc1_clk>, + <&disp_cc_mdss_ahb_clk>, + <&gcc_disp_hf_axi_clk>, + <&mdss_dsi1_phy 1>, + <&mdss_dsi1_phy 0>, + <&disp_cc_esync1_clk>, + <&disp_cc_osc_clk>, + <&disp_cc_mdss_byte1_clk_src>, + <&disp_cc_mdss_pclk1_clk_src>; + clock-names =3D "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus", + "dsi_pll_pixel", + "dsi_pll_byte", + "esync", + "osc", + "byte_src", + "pixel_src"; + + operating-points-v2 =3D <&mdss_dsi_opp_table>; + + power-domains =3D <&rpmhpd RPMHPD_MMCX>; + + phys =3D <&mdss_dsi1_phy>; + phy-names =3D "dsi"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + mdss_dsi1_in: endpoint { + remote-endpoint =3D <&dpu_intf2_out>; + }; + }; + + port@1 { + reg =3D <1>; + + mdss_dsi1_out: endpoint { + }; + }; + }; + }; + + mdss_dsi1_phy: phy@ae97000 { + compatible =3D "qcom,sm8750-dsi-phy-3nm"; + reg =3D <0x0ae97000 0x200>, + <0x0ae97200 0x280>, + <0x0ae97500 0x400>; + reg-names =3D "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + clocks =3D <&disp_cc_mdss_ahb_clk>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "iface", + "ref"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + }; + + displayport-controller@af54000 { + compatible =3D "qcom,sm8750-dp", "qcom,sm8650-dp"; + reg =3D <0xaf54000 0x104>, + <0xaf54200 0xc0>, + <0xaf55000 0x770>, + <0xaf56000 0x9c>, + <0xaf57000 0x9c>; + + interrupts-extended =3D <&mdss 12>; + + clocks =3D <&disp_cc_mdss_ahb_clk>, + <&disp_cc_mdss_dptx0_aux_clk>, + <&disp_cc_mdss_dptx0_link_clk>, + <&disp_cc_mdss_dptx0_link_intf_clk>, + <&disp_cc_mdss_dptx0_pixel0_clk>; + clock-names =3D "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks =3D <&disp_cc_mdss_dptx0_link_clk_src>, + <&disp_cc_mdss_dptx0_pixel0_clk_src>; + assigned-clock-parents =3D <&usb_dp_qmpphy QMP_USB43DP_DP_= LINK_CLK>, + <&usb_dp_qmpphy QMP_USB43DP_DP_VC= O_DIV_CLK>; + + operating-points-v2 =3D <&dp_opp_table>; + + power-domains =3D <&rpmhpd RPMHPD_MMCX>; + + phys =3D <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>; + phy-names =3D "dp"; + + #sound-dai-cells =3D <0>; + + dp_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-192000000 { + opp-hz =3D /bits/ 64 <192000000>; + required-opps =3D <&rpmhpd_opp_low_svs_d1>; + }; + + opp-270000000 { + opp-hz =3D /bits/ 64 <270000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-540000000 { + opp-hz =3D /bits/ 64 <540000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz =3D /bits/ 64 <810000000>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + }; 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[78.11.220.99]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-abbaa56026fsm865456666b.113.2025.02.21.07.25.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2025 07:25:05 -0800 (PST) From: Krzysztof Kozlowski Date: Fri, 21 Feb 2025 16:24:18 +0100 Subject: [PATCH v3 08/21] drm/msm/dpu: Add missing "fetch" name to set_active_pipes() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250221-b4-sm8750-display-v3-8-3ea95b1630ea@linaro.org> References: <20250221-b4-sm8750-display-v3-0-3ea95b1630ea@linaro.org> In-Reply-To: <20250221-b4-sm8750-display-v3-0-3ea95b1630ea@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , Jonathan Marek , Kuogee Hsieh , Neil Armstrong Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Srini Kandagatla , Rob Clark , Jessica Zhang X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=4099; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=5SEX46PHo6rdxc8rxQ+3AemVnzaGSDe6os5wm+Edk74=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBnuJqzzOwWI//ovhTAyozuG5vOfaijy2RUZn5uL G93/Sv6d+mJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZ7iaswAKCRDBN2bmhouD 1/5mD/9+utYyvYPLNBTboQf+fEu4VzIUJVptiC51/3kU1eWXv7Cy4w54XJNlqXKb6I8Y7lexsbM rOqG23z1oG9TJgAeA3iDetZTUVnzs0jhtpr38WS3le9ex7C7TXYgMerj4vCwxCI/tncoUG60BcP tHevqCxFMV5URPMf4zVscmQN3F8TO8LiPe3WQ1q8EQuE/vPJLL7v6JXbSCXHHQvmNbyyMeUQPL/ P4rp1Vu48VqJVHUPRhK6Ox2cHOfXuoAbYVZQD/loraD4o1qHyoGmKJktbfSFFvsUrgNJKaxwtQo cPI+zAalwvP4tIswaZF8dtqVaoUyrIv0nss8WkVBFGYc3X0aVDNDZdRf1p0NsiT1OEAlGqIlRWk tJWQcnOs3xxeA8BQxTVAN3VsaEDumxtJQMRRFqyVC7PdeJigX5aDYzN4vru4CcT4diEdyp9hjoM XK5CKhzLGDBSkYtCJwJykFjywt3e5XpFcxxlN5I6FbVQjSdTlncF+ifUGadKrXV9/vufErwSdCC l216dyFThRqmLpMahs3kgyI6QAQBo+fMNtR4bBZcki9L+heKp+w+VyiUWEndKJxaO4ZnhtNZYus Ql903gNYR5Ee3TvkA7Xu5sZ3S43bb9/HSxLK+HO3z8CgPcp/MP6A4uaMqlAYtfyN/dZwTNbA1vX jl6CuQruIpOVhhg== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B The set_active_pipes() callback configures CTL_FETCH_PIPE_ACTIVE and newer DPU v12.0 comes with CTL_PIPE_ACTIVE, thus rename it to set_active_fetch_pipes() to better match the purpose. Reviewed-by: Dmitry Baryshkov Reviewed-by: Jessica Zhang Signed-off-by: Krzysztof Kozlowski --- Changes in v2: 1. New patch --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 12 ++++++------ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 6 +++--- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 2 +- 3 files changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm= /disp/dpu1/dpu_crtc.c index e5dcd41a361f45be20c7d4414de4bf7a42ce3d3b..4e630d3ac7effca2c2d4ff88014= 65c7a8d3ef136 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -445,9 +445,9 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc= *crtc, =20 uint32_t lm_idx; bool bg_alpha_enable =3D false; - DECLARE_BITMAP(fetch_active, SSPP_MAX); + DECLARE_BITMAP(active_fetch, SSPP_MAX); =20 - memset(fetch_active, 0, sizeof(fetch_active)); + memset(active_fetch, 0, sizeof(active_fetch)); drm_atomic_crtc_for_each_plane(plane, crtc) { state =3D plane->state; if (!state) @@ -464,7 +464,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc= *crtc, if (pstate->stage =3D=3D DPU_STAGE_BASE && format->alpha_enable) bg_alpha_enable =3D true; =20 - set_bit(pstate->pipe.sspp->idx, fetch_active); + set_bit(pstate->pipe.sspp->idx, active_fetch); _dpu_crtc_blend_setup_pipe(crtc, plane, mixer, cstate->num_mixers, pstate->stage, @@ -472,7 +472,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc= *crtc, &pstate->pipe, 0, stage_cfg); =20 if (pstate->r_pipe.sspp) { - set_bit(pstate->r_pipe.sspp->idx, fetch_active); + set_bit(pstate->r_pipe.sspp->idx, active_fetch); _dpu_crtc_blend_setup_pipe(crtc, plane, mixer, cstate->num_mixers, pstate->stage, @@ -492,8 +492,8 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc= *crtc, } } =20 - if (ctl->ops.set_active_pipes) - ctl->ops.set_active_pipes(ctl, fetch_active); + if (ctl->ops.set_active_fetch_pipes) + ctl->ops.set_active_fetch_pipes(ctl, active_fetch); =20 _dpu_crtc_program_lm_output_roi(crtc); } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/m= sm/disp/dpu1/dpu_hw_ctl.c index 0021df38f8662683771abb2cef7794c3209e9413..757411f8ecec2eb7096b323a998= 94a5d0cc37fd9 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -669,8 +669,8 @@ static void dpu_hw_ctl_reset_intf_cfg_v1(struct dpu_hw_= ctl *ctx, } } =20 -static void dpu_hw_ctl_set_fetch_pipe_active(struct dpu_hw_ctl *ctx, - unsigned long *fetch_active) +static void dpu_hw_ctl_set_active_fetch_pipes(struct dpu_hw_ctl *ctx, + unsigned long *fetch_active) { int i; u32 val =3D 0; @@ -758,7 +758,7 @@ struct dpu_hw_ctl *dpu_hw_ctl_init(struct drm_device *d= ev, c->ops.update_pending_flush_dspp =3D dpu_hw_ctl_update_pending_flush_dsp= p; =20 if (mdss_ver->core_major_ver >=3D 7) - c->ops.set_active_pipes =3D dpu_hw_ctl_set_fetch_pipe_active; + c->ops.set_active_fetch_pipes =3D dpu_hw_ctl_set_active_fetch_pipes; =20 c->idx =3D cfg->id; c->mixer_count =3D mixer_count; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h b/drivers/gpu/drm/m= sm/disp/dpu1/dpu_hw_ctl.h index f04ae0b1d986fa8f73e5bf96babfca3b4f3a0bf5..b8bd5b22c5f8dadd01c16c352ef= ef4063f2614a6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h @@ -243,7 +243,7 @@ struct dpu_hw_ctl_ops { void (*setup_blendstage)(struct dpu_hw_ctl *ctx, enum dpu_lm lm, struct dpu_hw_stage_cfg *cfg); =20 - void (*set_active_pipes)(struct dpu_hw_ctl *ctx, + void (*set_active_fetch_pipes)(struct dpu_hw_ctl *ctx, unsigned long *fetch_active); }; =20 --=20 2.43.0 From nobody Mon Feb 9 08:04:22 2026 Received: from mail-ej1-f44.google.com (mail-ej1-f44.google.com [209.85.218.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D6ACC215786 for ; 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[78.11.220.99]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-abbaa56026fsm865456666b.113.2025.02.21.07.25.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2025 07:25:07 -0800 (PST) From: Krzysztof Kozlowski Date: Fri, 21 Feb 2025 16:24:19 +0100 Subject: [PATCH v3 09/21] drm/msm/dpu: Clear CTL_FETCH_PIPE_ACTIVE on mixer reset Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250221-b4-sm8750-display-v3-9-3ea95b1630ea@linaro.org> References: <20250221-b4-sm8750-display-v3-0-3ea95b1630ea@linaro.org> In-Reply-To: <20250221-b4-sm8750-display-v3-0-3ea95b1630ea@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , Jonathan Marek , Kuogee Hsieh , Neil Armstrong Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Srini Kandagatla , Rob Clark X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1076; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=9VwNmNeCKWvrEI0E43BuyMfe52M7P67PLdAG7OHfpN8=; b=kA0DAAoBwTdm5oaLg9cByyZiAGe4mrSg/e3xXqGoaof807wjPY4hcAiqoJ02A2Y8HGAKoTAAS IkCMwQAAQoAHRYhBN3SYig9ERsjO264qME3ZuaGi4PXBQJnuJq0AAoJEME3ZuaGi4PXsFQP/Avo A/CWck20edK9vihNhad341ZvUbBaUW4Rc3fw7DvnDOXT+MOopRGMO8GyCH5s0e7MVVIWlQYv9ph kyzUpzOo70C3ssipW7zJU6oJkMP2j8Ydvo7i6j4F2e1OD2WlcfY40bZ2pPmOtbXNdeR7iCuoAk7 p80XegXIlzPE0Fc0VRQQCzDP2xIH96/iyRw/7K7rCFxv4AIKZq/7m8d7Tuwv0DnfeZgay+N1qa5 cy9Uz+sChIr9NjE4dEQPadqXmR5TnQrSrJqhSNl7JRxs5O/TScaDpKRDRGeM1zeRoxp7QIXLH9W 8vX0NjfRqE+htZJSH1yFlUoLH5+fJQF0A9d7rUQlZjWXrhrLexCUjH/eKp9RXtxX2772utDlKF/ TwCPhN4MJS09C3XTQX8xdowMHI5siFkrK1FLCn8OGtrYgdihNtIi3YXKolbcWNe9Fi5JoAO1Kpf 9mkSWz3pK1FtqcTuadbKvwlSh8ADtRkWcc8NkoE6jx4rLi/K3lT+uRCiPg309UmSJcwXloBPRUD lpABBINqeAk1K7W5KtNOH5eDxE8SOJJbww7Mro/TYEoHDivtuO5dph/J1P1QU4sk3hjQ8BFDYtX QtCIE5m1xHmtz1O2TmzObe/M6yiqIgw1Lcp+zge2SEba5w/2IJ3khamf4glL3S0I0k22chHL90D OUtJ8 X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Resetting mixers should also include resetting active fetch pipes. Fixes: ae4d721ce100 ("drm/msm/dpu: add an API to reset the encoder related = hw blocks") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Dmitry Baryshkov --- Changes in v3: 1. New patch, split from previous big DPU v12.0. --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_encoder.c index 48e6e8d74c855b1fcf13c8f42516437039fc27da..090b2aa5a63b4797169b2492890= 8215e2424e6b1 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -2199,6 +2199,9 @@ static void dpu_encoder_helper_reset_mixers(struct dp= u_encoder_phys *phys_enc) /* clear all blendstages */ if (phys_enc->hw_ctl->ops.setup_blendstage) phys_enc->hw_ctl->ops.setup_blendstage(ctl, hw_mixer[i]->idx, NULL); + + if (ctl->ops.set_active_fetch_pipes) + ctl->ops.set_active_fetch_pipes(ctl, NULL); } } =20 --=20 2.43.0 From nobody Mon Feb 9 08:04:22 2026 Received: from mail-ej1-f46.google.com (mail-ej1-f46.google.com [209.85.218.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A8245215F61 for ; Fri, 21 Feb 2025 15:25:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740151513; cv=none; b=AZS7e4intZWnfjk5l9/upfRhYWgbkdiXivWN5oy8/MfQPYtX6lNW9R5wbeUkJba+R6sZECMpxdk82Mj8R964vee9EBiqztaH+Km8qnD4rAmwFowbXdi6rDnYUowS9RNfIAfdkyu5FyybYH6MUGOCG986P9q0YNNft+UDUmCGqA8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740151513; c=relaxed/simple; bh=ESNFAo0W8bIcHw5ZPbGGU0/A64Vmk44uaAkW3dodBRQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=GUW/4rkitWjw/sWyVe3JfpiLAogKaH6/t34K4TV1u/TwXAfJZ76imi0uXclEU8Q6JHybKTAvHt7dInWnx9pE2OG4ypHCrNbEgEPSAaNOOg8vc03SnTgkbqxK8gS2MOHhlqTE3pwYiN/Pvr0jcFkSqRaxPzQ8apoqWXCRIGefY7w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=p6I5c41R; arc=none smtp.client-ip=209.85.218.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="p6I5c41R" Received: by mail-ej1-f46.google.com with SMTP id a640c23a62f3a-abb9e81c408so38727866b.2 for ; Fri, 21 Feb 2025 07:25:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1740151510; x=1740756310; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=bEw8TbcK6Q3ctC14U9SOir0rvTkUsaIx3mimKGEmrWk=; b=p6I5c41Rj4YINB6fwUWEnhKw4h4N0EeNS7CjnntG1zSxAPqFIBjzBuTR0liS/yObNs oeA7eoZoryuYioA8OI+UZ114XyEYurknIlTtlIJeRs5C0vSvnmO2i2G9yaUmA3zo2so4 6mqj9nGg0y+mdTxIMxsqu+wqf9LGOjTB1amAVNtGDHeCBZXVxXArmHH119XUsyUD1XEB CdAySzRqKPoHUGqH/wpU63CtTWo0grz8zO5Y510f5KdKoqIkSdxgFTgSW9GsXQKQexRl HYpVpeiR9KHP5MXiA5ukO5zREixl9BAzRXNiC+uFr1IWbYYSnAs/CuUXgFnHkWXI3J9d Xk4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740151510; x=1740756310; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bEw8TbcK6Q3ctC14U9SOir0rvTkUsaIx3mimKGEmrWk=; b=cE+I73DeE7qJtxMaweGn6unY+pLIt3h7haRdASA4Z6k4AMTG0C/x4TxBJmiJbgBg7u HXF7Qz3WgpU4TmxBAvnzfJAtX9J6clvISuab7eShBBHEwlREYIaUOSR7F1W1RpXaBw9Y mecQ7+swfNB69041idw3/w6TlmXMh8H/mJH/UbAxSHQUXFyeW6KJ22SCndgc0P3Vylra JJPHuLFRSh/6cGdLFEfOnyegrmK8X4LfYX9EUPnKcOu69tXSAvKLTgUZgBPET8j5wEhM B/wJIpR1WWtmguuAyg9v2Hul0B7YU1LCSsokJSOSQ7nmvgiSVri8NGebCSCp1Q5uP3AA K04Q== X-Forwarded-Encrypted: i=1; AJvYcCUGUrLRCbHt8FWRPAqgOrSo1usgKjA6KACYqF44QDN0aPZHIHE82XrqkGPECzrY2zdJzN1VcSwxXD851Ps=@vger.kernel.org X-Gm-Message-State: AOJu0YwZNmta2yabkUd+hUlPULl0UIN6Z7/WM6/GXhRqXEHjp77v/7YY U4eAfIvV0Gr7mZ8ku8mLrwLKzksl3bLf/erDWlmF8o/REg38gPRli42TcYp3vYc= X-Gm-Gg: ASbGncthlyxvy3MyBTVi7vAHdwoZh44sOgT7Qq39OZ4mb7WyqfvdBqwZ7CdsbqLcOsw DNNktGjfYGo9i0is3/Ke7bTfySx5bArNVgdv98G5+K+wwOCm4PnaL8H2MyXp+l2i9D245rCg6C+ xbi243DVXzFtprtTd85jWcwGn41Oy+5/JmQFPl8kNkPPHKiGTSBP6IBBLU5ptoEpIxw66FIQilz DahqyIAicbEEPxsp9DqA/2tKEm/GN9qCH9RTfMl0uzQ5Fnfn0ff7j4Nb3yIJibnMQFg3GgCrHWL PnbSq/ky2QC8DGiLmdCqnx2C6Wwz4KsCOlipTSBrYE5aUKuXhSQhaRx+KnGbrKUlxJ+XRXPH4W9 e X-Google-Smtp-Source: AGHT+IFMiyoijhhsN/r66rGa3gdxIeiogjo+gOS8owC4awJmR9PjmfqBaix2rAFdUv1+W8Bs+pHTyA== X-Received: by 2002:a17:907:2ce2:b0:ab7:cd83:98bb with SMTP id a640c23a62f3a-abc09a3c1c5mr142336366b.5.1740151509961; Fri, 21 Feb 2025 07:25:09 -0800 (PST) Received: from [127.0.1.1] (78-11-220-99.static.ip.netia.com.pl. [78.11.220.99]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-abbaa56026fsm865456666b.113.2025.02.21.07.25.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2025 07:25:09 -0800 (PST) From: Krzysztof Kozlowski Date: Fri, 21 Feb 2025 16:24:20 +0100 Subject: [PATCH v3 10/21] drm/msm/dpu: Clear CTL_FETCH_PIPE_ACTIVE on ctl_path reset Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250221-b4-sm8750-display-v3-10-3ea95b1630ea@linaro.org> References: <20250221-b4-sm8750-display-v3-0-3ea95b1630ea@linaro.org> In-Reply-To: <20250221-b4-sm8750-display-v3-0-3ea95b1630ea@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , Jonathan Marek , Kuogee Hsieh , Neil Armstrong Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Srini Kandagatla , Rob Clark X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1056; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=ESNFAo0W8bIcHw5ZPbGGU0/A64Vmk44uaAkW3dodBRQ=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBnuJq16yN8kEhw7drJLPUlvodxfwFeC/r2eVwDW WjtMKuMWWGJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZ7iatQAKCRDBN2bmhouD 1/+sEACGJReGDn+b3f01/aVELZif6yYJJ+SA6Yf266CzmM/U9rNv6xCkX1jnrgfNjDVdScFkSCT +XFtYc1C5WkoH9zVGxJ6e8nn4tVBnUQQ6JTseswL1JEW/U8tCd0JWZdiC110M2dDTt1FERCNH7/ M6jyHhX/wgenyGMGn+vS0IrVWlGmJyqJal/7zhASirLtsF5svm5ARV4kUpjuPmM1dGaNWIli+pz sTgI8Cn2Pu3pf2ZODIfaoBlWGvREKN8BnTsPTmU7luLLe+dThw/9ujQBU7WRUIKEaSA8BsfoLe8 ZFI1ZA+0J4foWj6zw3JVu9F0rgKby7wF56NgVssD5AYlydwMNYvMhAadjAanmm17MoXituoBwhE B1Bwe8H29yFG4uXSemzj5Mw4/VvT0IOzcK0TzuREtFjdKBmY20nLrM4ZjLVrRB/Xeaic458aPjt 1QL86hQ8sl0ZBdFw19JRUbmIsZVBktJBc9QewRnURgDJehfrvUO5Ti4UID4l/w2G8MH7e7IzyYP sU7zxSLb4n393BRm1XV1KzHgRFpG52hVnOuNFcJIuEuvVpVIjZM2zo4QtzgQFzd8eEu7vY/TRM7 +odudo4ZW8C55I/iXdluEBKSUBLFEnVYhr/fNPoLhoRmb6rVVITxo1qF3zG+C3jT0lkPwN1SK6z 28cs2UOTVRqOM5A== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Resetting entire CTL path should also include resetting active fetch pipes. Fixes: e1a950eec256 ("drm/msm/dpu: add reset_intf_cfg operation for dpu_hw_= ctl") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Dmitry Baryshkov --- Changes in v3: 1. New patch, split from previous big DPU v12.0. --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/m= sm/disp/dpu1/dpu_hw_ctl.c index 757411f8ecec2eb7096b323a99894a5d0cc37fd9..1c14770865b4b5f83a95feb35d8= ca6b0c87fdb53 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -644,6 +644,9 @@ static void dpu_hw_ctl_reset_intf_cfg_v1(struct dpu_hw_= ctl *ctx, =20 dpu_hw_ctl_clear_all_blendstages(ctx); =20 + if (ctx->ops.set_active_fetch_pipes) + ctx->ops.set_active_fetch_pipes(ctx, NULL); + if (cfg->intf) { intf_active =3D DPU_REG_READ(c, CTL_INTF_ACTIVE); intf_active &=3D ~BIT(cfg->intf - INTF_0); --=20 2.43.0 From nobody Mon Feb 9 08:04:22 2026 Received: from mail-ej1-f46.google.com (mail-ej1-f46.google.com [209.85.218.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5301C21171C for ; Fri, 21 Feb 2025 15:25:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740151515; cv=none; b=rkuIYTGz5oAgGIlt1UE4BwNpSJyIctIJm1GyiKwFTUxkR13ktamp/o201+h56UijW3RSkjA9X2SBv/Me/tOOhY2yhlCHkqTx6Xhip7dou/iEy5tdSmPje8qaxE9rM9LZeYCGP88JZBdHreJu0Na6KfYJQtK8TKVhkC6mI7UWqK4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740151515; c=relaxed/simple; bh=NJ45LgTQlJolZGsxJ8wwShr0xgq7ERrenJp2LNxaJOk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=pRcJntBsC70pmZZfJcZlnR9C61LoRlsLuFvYGDVd8zGKoC8QV3Lh3XfvA5QacXIJxQ/ZY7996z7s9P/r6z/mHcy1TSNJmyJx4REyoNSQRBFGj3dFh/d41YX3kWD7DLukZ7fBldyUD7aRYw4Tsq4kE59NH4f0BeE5sVOa7WcrTfQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=D2sAagTB; arc=none smtp.client-ip=209.85.218.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="D2sAagTB" Received: by mail-ej1-f46.google.com with SMTP id a640c23a62f3a-ab7dd005cb0so33299766b.3 for ; Fri, 21 Feb 2025 07:25:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1740151512; x=1740756312; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=uETEnzxXsrcxJw343miABNyaWXgTTRBWJcaHZGLuMIQ=; b=D2sAagTB+/DxqnYC5UDKN0gqug4Qf2c82Cg2z1DvcT7/XuHZgR7/oJKVIg/6hcviUF Eq+pUfTIEh4/SM8Ga0tl4OtO9P2ZEEN8VTJtuVnGXMAU+qrhwqvtUWZ/Lj8QH5DYomGb Cor9S8vSjnyflowh8z7cyDGX+YQgawEeFsD8AO7OSQwtr8SBKaH550T4XZbl5RzhW51q zpf6bYuzvR+CNCTtPTuRYSwlonF1ChXSc1rh7SAkrPlkMicklqQfVzISyNw9OEoCHJNz 4Gf7etNI+P5Xrdf2AdGxGvOUwcwM3GHZ1HbapjwcoV5l38TySkPieFF3RnylkyeiPgWl gVtw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740151512; x=1740756312; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uETEnzxXsrcxJw343miABNyaWXgTTRBWJcaHZGLuMIQ=; b=kUW7u9R0y2jatTXpExOURIlHVgoQ0tfRSPIKHBEmJ+DcgAQMxDhyLom+SIfLZ0wWal 779Nu479rw8uo9oxbrlCtkk2erTt1UZDU0Sd5I39nToxL1ZNxITmi38A6NpaE0idSdgK CEHFyDx6pcDbJfP3w4h4hloWeNquiYOOKjMbciZRH9hITc54ai/uRc+UwsaUck2lVMHu Z8ARqUpbv77s8KEkJBZJBy3/pC3vRJXeF4YFCHTyFW5+n2YbwqaGmrszRfcFVP7QseqJ 8Xsv1QzENM6pymotSC1Ztj/Qsc8A8b3ATGNfQHr7WPwnJbNylB8iRw+yNZKp93DFZWcd gxCw== X-Forwarded-Encrypted: i=1; AJvYcCWOlYSDurcmppbpQ6qouvaWKlK58NTBtkifZs64bURzN/6YFfhybmqgW4UVemvpjF9qziohxdZarwoexWM=@vger.kernel.org X-Gm-Message-State: AOJu0YzPgobYSSsyhEQ0trOTVZPP5Cj732vjgXhT/Tek8afZXJFTupUh 9t91uFmHVU5cR+vrl2saNbz/b0YKZECthXzr/zXhdVF3WlX26s9kNey8t++yByA= X-Gm-Gg: ASbGnct47nFiFbVPMpJYLtH6ESVOHlizU0u5Wl2NSbDc/nHaoigxUAiY56xPM1hD8iC w16n3ruxnS/V7BFFOLJXQO4JqhBigVyrom31iwKRNQxVMjDq+5BJ5O368fiw2d/64Jh+WO1OwI+ +CD88Dawtt/6RmRljzsOMlRNvgvdX6giwS04Hk9qVg8q/gC4GGgLnjZZA8oBwlKbKQnpwJyF/XB Z2hphMiRtb9La22VN0T3m9poGGMOdWShYpBmt765Bo9i/SaZzx3KQJ0AMaZT7KP1Z71cYPx1jxN Oc/o+VNpa8fe8UtpiGTJr3Qwg+Vr7OazZDocN+o3gKtYnwen8vHVGhZIkaTzMguZiOLbgJi4fE+ j X-Google-Smtp-Source: AGHT+IH4qsBfcQ7xDFrHTtbwLWgEqC44pOLn8YYlo8rp3jDA5EwfNRoEqrdJZ5UAhQ9qdC2UwE14hQ== X-Received: by 2002:a17:907:2d20:b0:ab7:bb4b:aa49 with SMTP id a640c23a62f3a-abc09a0bf7fmr159539766b.5.1740151511708; Fri, 21 Feb 2025 07:25:11 -0800 (PST) Received: from [127.0.1.1] (78-11-220-99.static.ip.netia.com.pl. [78.11.220.99]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-abbaa56026fsm865456666b.113.2025.02.21.07.25.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2025 07:25:11 -0800 (PST) From: Krzysztof Kozlowski Date: Fri, 21 Feb 2025 16:24:21 +0100 Subject: [PATCH v3 11/21] drm/msm/dpu: Clear CTL_FETCH_PIPE_ACTIVE before blend setup Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250221-b4-sm8750-display-v3-11-3ea95b1630ea@linaro.org> References: <20250221-b4-sm8750-display-v3-0-3ea95b1630ea@linaro.org> In-Reply-To: <20250221-b4-sm8750-display-v3-0-3ea95b1630ea@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , Jonathan Marek , Kuogee Hsieh , Neil Armstrong Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Srini Kandagatla , Rob Clark X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1096; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=NJ45LgTQlJolZGsxJ8wwShr0xgq7ERrenJp2LNxaJOk=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBnuJq1wq+sYpAfoG/91kYlqKkVWKgKfdeCiyeml U2xRmgpmwCJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZ7iatQAKCRDBN2bmhouD 13daD/9FxXVjsQ4sx3at3aoeugF5KncoxC4kdwXt7iZz0vVgikqQmmT2o7fKhuiUp58xlvwJPKd OXzHkaaSFAriAt9bUjBuLbS4kqcY7CzD6Urq6LhSBM5XSYHo+9aIiPsGs5D9nhRAwJvYqrzbcQo G/Wqj0kmKQKKrUVSYui/43d8xF9IdIK3TbP4NAGbpguzD4q6EGp6C1cyErOPA79RUYxwdBI9iHb eCmpo8a9BqhGdYSOwkIZdXYoQ0Rj358UFgQbdIA0juFM5VlveKmAh6Q0K1yloymrAB+7/Kr5/SY VP+sI/IMKXollYlz1LRvVUWjrUC/T1xQIVcvY8LXCXpc6/jqb3WmoWDrjhTTfsY0cWgBTVOfwih VYg9SJB0xkPs/3xEVPjWzUvPl0yilAy92+2gv6qEY8vEj65pUHvDX/8KbWEau0GRpFH67COjpWB NonpnVCJyz++tyaKmeXrAdnxzp44jgvqCZDX9U+xqk5Rtm1F3nhWCityY/ukOGWDg0NbES2iC7d gz1vN186niRKeN4tD3kZPMrXdxFaeCer+Dm07Xeuz6LMKk6ZOc91azPPZvcU+Eog7khK8zIYKhz V0ihmfOzeT3/0JRGTD4+ZtYkXHhIUAe1K34SPjlk2ygPq7ksS/897vcbLH+sQWEljWDv0YBPH7a +6yzFQf/3wbpHNw== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Before blend setup, all existing blend stages are cleared, so shall be active fetch pipes. Fixes: b3652e87c03c ("drm/msm/disp/dpu1: add support to program fetch activ= e in ctl path") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Dmitry Baryshkov --- Changes in v3: 1. New patch, split from previous big DPU v12.0. --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm= /disp/dpu1/dpu_crtc.c index 4e630d3ac7effca2c2d4ff8801465c7a8d3ef136..b9fe3a7343d54f6f8b5aad79829= 28d5fc728bd61 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -519,6 +519,8 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc) if (mixer[i].lm_ctl->ops.clear_all_blendstages) mixer[i].lm_ctl->ops.clear_all_blendstages( mixer[i].lm_ctl); + if (mixer[i].lm_ctl->ops.set_active_fetch_pipes) + mixer[i].lm_ctl->ops.set_active_fetch_pipes(mixer[i].lm_ctl, NULL); } =20 /* initialize stage cfg */ --=20 2.43.0 From nobody Mon Feb 9 08:04:22 2026 Received: from mail-ej1-f43.google.com (mail-ej1-f43.google.com [209.85.218.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 59A8B217F28 for ; Fri, 21 Feb 2025 15:25:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740151517; cv=none; b=YuwN0rrSelSYfkVTHP1PPfy7bV97BvUdN1EeNuFXsZhZMb9T7GLl8MiPx3+nrYafAUzNvGRUa9NVPf3lsOFV9qtCUzCoe5w4/YgUfToQ3HU/zkTagSLXOiS+WFXc10hUfOr4QX+lser+FoqPejNxRoq1aetIOYq+EKPZ2oIHb8w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740151517; c=relaxed/simple; bh=Rtqqvrg7pP9bsyM3YOU4Po/H2xEipMowzn5M0FXGvfw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=QcSqQceOlsunHnj+6NJVQDmdwSUsmIBnkvUchFWIjtvjw7aK0I/Yo6nulMvaxGE3utOv6lrsGmZlc2cot2ET3KBUKzu9QYLGhM9OV0kIjKu15q1S9OBkqcfvjmv5O0/0RsUlNDLwWjjTIFNh6TZ8uWFMy+xj4BbwRS+OHFdjsX0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=CggMlc9o; arc=none smtp.client-ip=209.85.218.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="CggMlc9o" Received: by mail-ej1-f43.google.com with SMTP id a640c23a62f3a-abb9c8c4e59so36357166b.1 for ; Fri, 21 Feb 2025 07:25:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1740151513; x=1740756313; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=aig57uYJrFI1rR0Npc+LI3qdVee6ZxW9yHVBFNwtitI=; b=CggMlc9oap+B/Vg22NkjuqXzDcQuh+8m+XVmFme/4uatMC8Q48WqakVD5kMBkYmMBZ VCZXCtZwXFA/NTP4CwzDaKtNLhuK4y7uRFQjbO+NxvETgo9d7Nn/AGAgB39vjgavAb7h NKxI4ZPfV+xpEriteBBAujYMR94JKITmIFVooayfjkidBj+72PKO12ROvlQPIc/QMpeI Eduu2wyrxhE5molmMxu7GMAEsD5Wx77LOJ0cKaW/MdI8nGHkvR6BTXzGwGpFBCMoIO/D W58NIU04qZPLj6YacuU5jLku0HDhmtVEEP5W55+Ia5h9OtFn6hAJ0HaDKbLzmzFxUI2G F2xw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740151514; x=1740756314; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=aig57uYJrFI1rR0Npc+LI3qdVee6ZxW9yHVBFNwtitI=; b=Ti42Z1JPmFySPmMdNAlW/IOWuMi7aIKMZjwVCtywhM9hVMAQqUyTfTlgYUQil3Pq5s 3WKmr3vUDxHmH7ZU16p536rT9cpM7lYBvF1n8txb8lV/68Ab1vfMZN+H8aKA74hp4mlE e97TZpj7UZETT60cXreDYbp4CaBk4wBmM7FsVeqtZXxmwFyo/dG0aGxCzSK8oITXMKEu ptrtsk3j8FDRtf6AQS3C46u9cUnQ9uJzpUuGIQdUUOp/Z+E5/aihdt8NNtv8HB/h5vF0 Bs/jvhzcP5GXlcyhZF8sOk19Ac1VKgYbtb7oQtbEN312nmz/hUcnxWAx8LWOf5CDWBzi nStQ== X-Forwarded-Encrypted: i=1; AJvYcCUmqcbxoduSCl3NADgzP4wDncPCFzFh9s2eA3PeuHOuePk4923UvcmqKDI/eJrLLnsJZpXAS9aY0vJolXk=@vger.kernel.org X-Gm-Message-State: AOJu0Yw4wmz6iQtDxQCULM8JltuGchgoqHpkzLuQa1HiOzHCU42ECGx/ J2KQS02Y6TNqP8Ryn8xoTDSCQdI8wF5OQ+ACeS6eN/aN3FgmNBkvgO+Z4tzoCuQ= X-Gm-Gg: ASbGncuH5UdJTKnqGDJnqH26dnj+pEzIAvB7Vo5V0CKVH+Q2t5PIjLPtoK8XYfkykb+ RF3M0teCx+U86/P8BkfB/qEQ0NG+xmhSrtfH/4EzLnH2ChVQ6DMg2OdWmupgZYdwITx6vdfNvnE isgxmVpFLRw+XCgMCH5DTMHAvpLp3adUJ/2cBeRREkXMdizuW6OPSNk+exJxLa3eu8pWCKzPxHx S4aY3sf8iVCXx839N9JWgL/K03emuA0yUFn7+V+XYAnbWWwbjhysWt9qtxu3OFefUnVjxrRoGwz tUiLYT5HF78Av4jjicld7PzLiYpzuLP1xzRkT7a1LX+rnoJ2TkqSwp7C9hOH1pjXyJ7O7HChaEY N X-Google-Smtp-Source: AGHT+IHdJOjKrzQzkQQRCXSbAnLH5FFessN3GeskMAbLKgYrjEA9y24pcdZQtQV3lv+cDs99o+UQfg== X-Received: by 2002:a17:906:dc8a:b0:a9a:2afc:e4ef with SMTP id a640c23a62f3a-abc09a97a18mr157000566b.7.1740151513561; Fri, 21 Feb 2025 07:25:13 -0800 (PST) Received: from [127.0.1.1] (78-11-220-99.static.ip.netia.com.pl. [78.11.220.99]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-abbaa56026fsm865456666b.113.2025.02.21.07.25.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2025 07:25:13 -0800 (PST) From: Krzysztof Kozlowski Date: Fri, 21 Feb 2025 16:24:22 +0100 Subject: [PATCH v3 12/21] drm/msm/dpu: Drop useless comments Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250221-b4-sm8750-display-v3-12-3ea95b1630ea@linaro.org> References: <20250221-b4-sm8750-display-v3-0-3ea95b1630ea@linaro.org> In-Reply-To: <20250221-b4-sm8750-display-v3-0-3ea95b1630ea@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , Jonathan Marek , Kuogee Hsieh , Neil Armstrong Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Srini Kandagatla , Rob Clark , Jessica Zhang X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1894; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=Rtqqvrg7pP9bsyM3YOU4Po/H2xEipMowzn5M0FXGvfw=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBnuJq2+0BckVlsV5NQsH+fOOk+tgIU+W0cwtdk8 5PAQ0lltK2JAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZ7iatgAKCRDBN2bmhouD 1989D/wNvFmmF2NaNbzyERRYlayAx59GBiMJg46dVMuecOeKpYw7e23TtYOBE9e7+w2dhIx2aUP J4cLUKshVRrUNa4/xJQ7R+qK5+CzhpVoZT8X8QYnQ6nevWv4GpW0L7gB2RPc80DT0lNDL7kOdeD CVY15jrscmSWYkScxCbl66kCdaxVMEa7cHpGcmKaZtEhwU6XSFsLHMvDOp1vlYuzDMtA0sVm8FM NK9lbP4oAfJZ8+rxi/0IuSpRozbwrmoOkXrO3uyxbEc9m3XFp7eZ7J21qmObzy2ThScv+QO/yIN 6H7MRnplfjyV5QqKExYW0tYeW8c20GMFl+SmTQ/TnkVLWZV73pnkm4Z/HJgXd4ZCHoNJkQFZKjt cjieYatKU2V4CO8C1dB7eweIn5Qkunm57Y91nRDKWMLJIgFEuAE2PMiD4aRCEb4czTtyUOzZxEm A/eUZFbxkYkYMe55NEcdpybTwFeuouDPqOODoNFysGa6KBOkGtBZPqZusfjrnxEhEg0sq9N6cYG gtzArVSBRBjTfh75jckfEYuzK5NUaT/mfg0soWqaECcu/PbVJf6IpuqU9UvxW5bsku/BuklYAfH K3Dueo8PwMsy8oTnKJbqN36/Fm6wfp4wZ6iagAhFLke/sSx+MWlHfocl967zWudT6Z1UYYkPbzj KmVHudvaqT+tP4w== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Drop comments about SoC before each 'struct dpu_lm_sub_blks' for given SoC because it's duplicating the actual name of structure. Reviewed-by: Dmitry Baryshkov Reviewed-by: Jessica Zhang Signed-off-by: Krzysztof Kozlowski --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.c index 7ea424d7c1b75e06312692225f4e888e81621283..4ff29be965c39b29cf7e3b97616= 34b7f39ca97b0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -362,8 +362,6 @@ static const struct dpu_sspp_sub_blks dpu_dma_sblk =3D = _DMA_SBLK(); * MIXER sub blocks config *************************************************************/ =20 -/* MSM8998 */ - static const struct dpu_lm_sub_blks msm8998_lm_sblk =3D { .maxwidth =3D DEFAULT_DPU_OUTPUT_LINE_WIDTH, .maxblendstages =3D 7, /* excluding base layer */ @@ -373,8 +371,6 @@ static const struct dpu_lm_sub_blks msm8998_lm_sblk =3D= { }, }; =20 -/* SDM845 */ - static const struct dpu_lm_sub_blks sdm845_lm_sblk =3D { .maxwidth =3D DEFAULT_DPU_OUTPUT_LINE_WIDTH, .maxblendstages =3D 11, /* excluding base layer */ @@ -384,8 +380,6 @@ static const struct dpu_lm_sub_blks sdm845_lm_sblk =3D { }, }; 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Reviewed-by: Dmitry Baryshkov Reviewed-by: Jessica Zhang Signed-off-by: Krzysztof Kozlowski --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/= msm/disp/dpu1/dpu_hw_mdss.h index ba7bb05efe9b8cac01a908e53121117e130f91ec..440a327c64eb83a944289c6ce9e= f9a5bfacc25f3 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h @@ -123,6 +123,7 @@ enum dpu_lm { LM_4, LM_5, LM_6, + LM_7, LM_MAX }; =20 @@ -167,6 +168,8 @@ enum dpu_dsc { DSC_3, DSC_4, DSC_5, + DSC_6, + DSC_7, DSC_MAX }; =20 @@ -183,6 +186,8 @@ enum dpu_pingpong { PINGPONG_3, PINGPONG_4, PINGPONG_5, + PINGPONG_6, + PINGPONG_7, PINGPONG_CWB_0, PINGPONG_CWB_1, PINGPONG_CWB_2, @@ -197,6 +202,7 @@ enum dpu_merge_3d { MERGE_3D_2, MERGE_3D_3, MERGE_3D_4, + MERGE_3D_5, MERGE_3D_MAX }; =20 --=20 2.43.0 From nobody Mon Feb 9 08:04:22 2026 Received: from mail-ej1-f45.google.com (mail-ej1-f45.google.com [209.85.218.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 181D1219E99 for ; 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[78.11.220.99]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-abbaa56026fsm865456666b.113.2025.02.21.07.25.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2025 07:25:16 -0800 (PST) From: Krzysztof Kozlowski Date: Fri, 21 Feb 2025 16:24:24 +0100 Subject: [PATCH v3 14/21] drm/msm/dpu: Add handling of LM_6 and LM_7 bits in pending flush mask Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250221-b4-sm8750-display-v3-14-3ea95b1630ea@linaro.org> References: <20250221-b4-sm8750-display-v3-0-3ea95b1630ea@linaro.org> In-Reply-To: <20250221-b4-sm8750-display-v3-0-3ea95b1630ea@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , Jonathan Marek , Kuogee Hsieh , Neil Armstrong Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Srini Kandagatla , Rob Clark , Jessica Zhang X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1020; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=JRqovq+Rdk4ORXpGPmhXUXGU0PwNM6eotWnKyHhO04g=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBnuJq4bVJFnsyb6JXH0wvrNs+g4JuM+dv4z0uK/ SXpuDXh5ZCJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZ7iauAAKCRDBN2bmhouD 10+bEACS/6knRONeGRMXYcJCR0RdF1lHQo2wynIQXKhVTCF0F2KMsTDrqFOiGs1+EXBtyp+tM+Y xe/+bWynGqwKEbRNdt4haJT50d6v9mHfR09hzbVuxRzX7gC2dZvG3xyUbGSDTrn5kO9szHGLOgO 9rRxycM+wrNkV7Lslr5FvhgjYdePrmrTBi4lV393VJZzH7hoFmQKBqXTyQCw/MD3kX6DGF9X7n6 XvCe2nXpjelkmztT3j/HGLqpmSQ+fctZexywB1ZSQaTQmf686BIRnWLmvcwAIxWH8Ei07pQEeVt q5U0PgQw8KLGkR4YE8BNUJzS7qXpA/SAxq5wbwbClFKC2mMBtY4611wdvGD8oSy7Ueqby8+qeTc 8wgarJfbYY6LmmB065D9QNPFNFqYh27BoHRsWlO18FBcubQHO5Na18sUbm6QSkUC+TcIyXmsD5i rXHpZltfdZg8DTREYZQdwfSIg27i93Xm3/pWicS8Zdk+koiRbiJAZVjfBLMw83ePDbaM6tGmSrP enOYXotVh6DXbn+cXfKpHuCnIiibUz/M3YlQXUIVwhYRAD3HLzXJKHFDR3hJc+w1yedmB3yDxRD b3Tzo0zzHml7BZtjxeYwGv9jRO3QI3XE51h23/N5R2OMnmc+hrTg+N4t9MI6hc68pAZpJkz+84+ Yuv0917jW4WdbvQ== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B MDSS/MDP v12 comes with new bits in flush registers (e.g. MDP_CTL_0_FLUSH) for Layer Mixer 6 and 7. Reviewed-by: Dmitry Baryshkov Reviewed-by: Jessica Zhang Signed-off-by: Krzysztof Kozlowski --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/m= sm/disp/dpu1/dpu_hw_ctl.c index 1c14770865b4b5f83a95feb35d8ca6b0c87fdb53..43a254cf57da571e2ec8aad3802= 8477652f9283c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -254,6 +254,12 @@ static void dpu_hw_ctl_update_pending_flush_mixer(stru= ct dpu_hw_ctl *ctx, case LM_5: ctx->pending_flush_mask |=3D BIT(20); break; + case LM_6: + ctx->pending_flush_mask |=3D BIT(21); + break; + case LM_7: + ctx->pending_flush_mask |=3D BIT(27); + break; default: break; } --=20 2.43.0 From nobody Mon Feb 9 08:04:22 2026 Received: from mail-ej1-f46.google.com (mail-ej1-f46.google.com [209.85.218.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1328A21B1BE for ; Fri, 21 Feb 2025 15:25:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740151523; cv=none; b=meDLv2si6jTgcqatVMxL3GyBdX2OUc9pCHIKNaslqnHo1R/bXzFEL9u/Vpc1RyouNg/auy8mZIgPGYrvB3xtUAoSMB/A3hd9lAyc9+OMTOPyrzpCxPp3fnRCarG4vIZY1uUQNuQ0b9UiHtA4q45GPK8DECbhU4PoXa3aRyNAgVs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740151523; c=relaxed/simple; bh=snxCfpFnaVRB8wWABvgKk9UGCtiNQGkpVMh0oP9yYNk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=PY+BTQiPcmSZXWk/vmQPZbG0BpFI1VKOy102J3n954T7YDfoZ1pDH/xxStBAs5OvbZjiZy7ThzK2OYu7OxMbMq8VM7gMY2osAyn2ztvTW7Vy5cmPA6JBkTnOAia4K4G3KPsoBpJBKVZONJ3I615sqyrr2WVM45QI5nSsu3eTQME= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=aNp0utYo; arc=none smtp.client-ip=209.85.218.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="aNp0utYo" Received: by mail-ej1-f46.google.com with SMTP id a640c23a62f3a-ab7d8953b48so33268466b.2 for ; Fri, 21 Feb 2025 07:25:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1740151519; x=1740756319; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=qKNH0rWogzlXzBLp5BH8wv7DSHrVkDUY/jHSPIdjQ0Y=; b=aNp0utYoPbYF7/eHQJjGQAN1E6QHg68MyTwwMlxBHPJSnUb0KDDga7+5Ey4a+U1Su2 c8JAI5CTo6iWq9r/9LntwbHNGHQemlRbizU28/a2fYvpRHa9B5KrUyVz9xI9TFZpsGyA NezprCzK0MkR50yWgzXNLrba4HSHjpjqXWFDXsIOZDFiHhkmHxew9gWHQ64AL+WdghnM z1ZnmdplpiRay0lWXnu1z1MRl1Q46EroNhqv0eVzt0iBz5CrP9UNhIWcfvlHzwy6tbs6 nUyPsNkLcy9+OJj7ilClzS5kUA//Ilx+JWkkOahPJOUe2xwLYKMl42V45oZ2wx3dtTgo AS/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740151519; x=1740756319; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qKNH0rWogzlXzBLp5BH8wv7DSHrVkDUY/jHSPIdjQ0Y=; b=INqQmSQfyvIEi0v3LJ9xb6Sa31U3+M7wDxVK0hWAwVBY6+zZByinJ0rDidmot30yaQ ALwQg9vFXCqJhl9/Jp4HGZiJhN+i2hbogXtFSyKJnP8nEIwOT78pF2IAul9xZUDvmTvS ZN+OqG6t9VIJP+YmEDWyEZ0QZAxKeiDTMQND886U2cuZtJ8Kctc7iki/rZP8ymgaZFbb ny91aeQcuOVYrB4hKZFPJ/hzVTuZ6pYNyHY+B6UWRErtLz+DuQedJAkyIZO2yMmXCVrz 7KVZldbO2DiIJth2qoYDd0toI4avFflWaO/sII04ohThxATXnwT9xqS7ofuZOviywxgh u8Sw== X-Forwarded-Encrypted: i=1; AJvYcCWwQP4KGCpZpWXXtyJJR0Plsc4zCvXfVbmL91KeqgqGh/7fIxPZzoHL9R509ianUDwFGOtFNQTrdwFmt/M=@vger.kernel.org X-Gm-Message-State: AOJu0YzDHGPxPB8KcDXczGDqtxj33uR/sOejC8h6of2DWnuDmk2oHwKc 2N4+stjIEp1PfBY4Z0OGim5Gg4Rzq4qJo6r+8Jft7dSsTodi8MaQUJFSZCEjxoE= X-Gm-Gg: ASbGncuuznBkLI0LVAplHoT8xmHS5fNTy4XM6qmvROkSR+tvVBoE+rCgJzMaUXBZvUf yf1HjX9wQ9tt0Plx9YvrbMZZHcrPS3yYkZUW8fqX9///0I6/UydDfCtpDi0k3l+SMBarDkA9Q4M wjRN1r+U1OFDddkOuBIC2Lx4q2XgXljPc5HHp3bW5M8Xa+ZP2tP0JwSTasw8+LVmXknjxydyQk+ U9Prn1rhP+xyvjwc4Iq7ufezF0wTJqQpLHuA0jFN+Q0sYS+3/l1/9Db4/Eu2t9CBKc+8tHeq/+l wzECDQF1mKft4/Y5pSYvwVVfMlbojk7TZ1f1h7XLUTvnbwI+ywlDOOZpBzYks9tKw8Z2A46/kLT F X-Google-Smtp-Source: AGHT+IHdCOE/u0lD8qjfvZOUT/QWDn5aY+s+xeyST+vs4PuD6w6EIv90WWYD9n/YVgGFAkR5d8RVkw== X-Received: by 2002:a17:907:9496:b0:a99:a6e0:fa0b with SMTP id a640c23a62f3a-abc09a2c929mr151135666b.5.1740151519399; Fri, 21 Feb 2025 07:25:19 -0800 (PST) Received: from [127.0.1.1] (78-11-220-99.static.ip.netia.com.pl. [78.11.220.99]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-abbaa56026fsm865456666b.113.2025.02.21.07.25.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2025 07:25:18 -0800 (PST) From: Krzysztof Kozlowski Date: Fri, 21 Feb 2025 16:24:25 +0100 Subject: [PATCH v3 15/21] drm/msm/dsi/phy: Add support for SM8750 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250221-b4-sm8750-display-v3-15-3ea95b1630ea@linaro.org> References: <20250221-b4-sm8750-display-v3-0-3ea95b1630ea@linaro.org> In-Reply-To: <20250221-b4-sm8750-display-v3-0-3ea95b1630ea@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , Jonathan Marek , Kuogee Hsieh , Neil Armstrong Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Srini Kandagatla , Rob Clark X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=10146; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=snxCfpFnaVRB8wWABvgKk9UGCtiNQGkpVMh0oP9yYNk=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBnuJq5LZECgZNmGLG2hbTwkda3kibDLGZMJ0Sfc KoPBitcK2SJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZ7iauQAKCRDBN2bmhouD 105vEACSCLAdn4gHGiIHyScDwAboRMnICnpW50WbiysDe2sq69Mpij2f9DQHYlf2zMu76+7D/51 bh/dyuQcYSMN69cZ+eHgNd10xb2bnKEOacwJpcttv4O/XGhDDR01WZQ/8mwhCYFtgLdU01vz3Rd 0gUotI5dKHCEmAYsMRcP592jksSL8KKGBtsgKw49aa+Y7knb5Slqyi116FT7FTAoqzse9TdAYPM Mt0W2GPNSxaLhavOQX5qnZs8Sj1Co4vZRRLwOVccgyrepXX+CZptWgvIczse8JJ/XPldq+3Vz8I 6PU9jJfIuQ7WE+KzA9M0aUyids6xd14Lro9w6qxgx5mFIpeOpONwodvyY6EtnnGsSLtQeB5Djml lDHbnr+QfOwaDt5bKp/7L+aG6649z1ButqTgY3WZffvczMtTpAh/6XJCPiUQWBcNBFSSjfvabzO na5agwJp/+TdpXxnQzCGnQEc6eTx68n7U509NkfGWPxUxl7pwdmvGLt7KeVkwV7b3hDtKDyRxNU Phim7aboGF1puliwdWaza++4y3E3UYnzOOvw26ZgZYro0bnAslgMDifM5nqS3cyKOa1BfWyx6SE 5QNBHD/dO1XRm0Pepwcud0/q4sRnEW1dZXa1KJFs6D7QKLLDryPx26JerzdcUfdUT1tcOhN/oZp g85l//nSBVpRhwQ== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Add support for DSI PHY v7.0 on Qualcomm SM8750 SoC which comes with an incompatible hardware interface change: ICODE_ACCUM_STATUS_LOW and ALOG_OBSV_BUS_STATUS_1 registers - their offsets were just switched. Currently these registers are not used in the driver, so the easiest is to document both but keep them commented out to avoid conflict. Reviewed-by: Dmitry Baryshkov Signed-off-by: Krzysztof Kozlowski --- Changes in v2: 1. Fix pll freq check for clock inverters 160000000ULL -> 163000000ULL --- drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 + drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 + drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 79 ++++++++++++++++++= ++-- .../gpu/drm/msm/registers/display/dsi_phy_7nm.xml | 14 ++++ 4 files changed, 90 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/ds= i/phy/dsi_phy.c index c0bcc68289633fd7506ce4f1f963655d862e8f08..60571237efc4d332959ac76ff1d= 6d6245f688469 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c @@ -593,6 +593,8 @@ static const struct of_device_id dsi_phy_dt_match[] =3D= { .data =3D &dsi_phy_4nm_8550_cfgs }, { .compatible =3D "qcom,sm8650-dsi-phy-4nm", .data =3D &dsi_phy_4nm_8650_cfgs }, + { .compatible =3D "qcom,sm8750-dsi-phy-3nm", + .data =3D &dsi_phy_3nm_8750_cfgs }, #endif {} }; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/ds= i/phy/dsi_phy.h index 8985818bb2e0934e9084a420c90e2269c2e1c414..fdb6c648e16f25812a2948053f3= 1186d4c0d4413 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h @@ -60,6 +60,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8650_cfgs; +extern const struct msm_dsi_phy_cfg dsi_phy_3nm_8750_cfgs; =20 struct msm_dsi_dphy_timing { u32 clk_zero; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/ms= m/dsi/phy/dsi_phy_7nm.c index 5ef5bc252019486c6f24f256d88d69ad3f6c838b..6ef513a54c299d64044fbe2cc7c= 4cabe2ffe243e 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c @@ -50,6 +50,8 @@ #define DSI_PHY_7NM_QUIRK_V4_3 BIT(3) /* Hardware is V5.2 */ #define DSI_PHY_7NM_QUIRK_V5_2 BIT(4) +/* Hardware is V7.0 */ +#define DSI_PHY_7NM_QUIRK_V7_0 BIT(5) =20 struct dsi_pll_config { bool enable_ssc; @@ -128,9 +130,30 @@ static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *= pll, struct dsi_pll_config dec_multiple =3D div_u64(pll_freq * multiplier, divider); dec =3D div_u64_rem(dec_multiple, multiplier, &frac); =20 - if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1) + if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1) { config->pll_clock_inverters =3D 0x28; - else if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) { + } else if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_0)) { + if (pll_freq < 163000000ULL) + config->pll_clock_inverters =3D 0xa0; + else if (pll_freq < 175000000ULL) + config->pll_clock_inverters =3D 0x20; + else if (pll_freq < 325000000ULL) + config->pll_clock_inverters =3D 0xa0; + else if (pll_freq < 350000000ULL) + config->pll_clock_inverters =3D 0x20; + else if (pll_freq < 650000000ULL) + config->pll_clock_inverters =3D 0xa0; + else if (pll_freq < 700000000ULL) + config->pll_clock_inverters =3D 0x20; + else if (pll_freq < 1300000000ULL) + config->pll_clock_inverters =3D 0xa0; + else if (pll_freq < 2500000000ULL) + config->pll_clock_inverters =3D 0x20; + else if (pll_freq < 4000000000ULL) + config->pll_clock_inverters =3D 0x00; + else + config->pll_clock_inverters =3D 0x40; + } else if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) { if (pll_freq <=3D 1300000000ULL) config->pll_clock_inverters =3D 0xa0; else if (pll_freq <=3D 2500000000ULL) @@ -249,7 +272,8 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_7= nm *pll) vco_config_1 =3D 0x01; } =20 - if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) { + if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2) || + (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_0)) { if (pll->vco_current_rate < 1557000000ULL) vco_config_1 =3D 0x08; else @@ -619,6 +643,7 @@ static int dsi_7nm_pll_restore_state(struct msm_dsi_phy= *phy) static int dsi_7nm_set_usecase(struct msm_dsi_phy *phy) { struct dsi_pll_7nm *pll_7nm =3D to_pll_7nm(phy->vco_hw); + void __iomem *base =3D phy->base; u32 data =3D 0x0; /* internal PLL */ =20 DBG("DSI PLL%d", pll_7nm->phy->id); @@ -628,6 +653,9 @@ static int dsi_7nm_set_usecase(struct msm_dsi_phy *phy) break; case MSM_DSI_PHY_MASTER: pll_7nm->slave =3D pll_7nm_list[(pll_7nm->phy->id + 1) % DSI_MAX]; + /* v7.0: Enable ATB_EN0 and alternate clock output to external phy */ + if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_0) + writel(0x07, base + REG_DSI_7nm_PHY_CMN_CTRL_5); break; case MSM_DSI_PHY_SLAVE: data =3D 0x1; /* external PLL */ @@ -906,7 +934,8 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, =20 /* Request for REFGEN READY */ if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) || - (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) { + (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2) || + (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_0)) { writel(0x1, phy->base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10); udelay(500); } @@ -940,7 +969,20 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, lane_ctrl0 =3D 0x1f; } =20 - if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) { + if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_0)) { + if (phy->cphy_mode) { + /* TODO: different for second phy */ + vreg_ctrl_0 =3D 0x57; + vreg_ctrl_1 =3D 0x41; + glbl_rescode_top_ctrl =3D 0x3d; + glbl_rescode_bot_ctrl =3D 0x38; + } else { + vreg_ctrl_0 =3D 0x56; + vreg_ctrl_1 =3D 0x19; + glbl_rescode_top_ctrl =3D less_than_1500_mhz ? 0x3c : 0x03; + glbl_rescode_bot_ctrl =3D less_than_1500_mhz ? 0x38 : 0x3c; + } + } else if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) { if (phy->cphy_mode) { vreg_ctrl_0 =3D 0x45; vreg_ctrl_1 =3D 0x41; @@ -1002,6 +1044,7 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, =20 /* program CMN_CTRL_4 for minor_ver 2 chipsets*/ if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2) || + (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_0) || (readl(base + REG_DSI_7nm_PHY_CMN_REVISION_ID0) & (0xf0)) =3D=3D 0x20) writel(0x04, base + REG_DSI_7nm_PHY_CMN_CTRL_4); =20 @@ -1116,7 +1159,8 @@ static void dsi_7nm_phy_disable(struct msm_dsi_phy *p= hy) =20 /* Turn off REFGEN Vote */ if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) || - (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) { + (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2) || + (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_0)) { writel(0x0, base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10); wmb(); /* Delay to ensure HW removes vote before PHY shut down */ @@ -1333,3 +1377,26 @@ const struct msm_dsi_phy_cfg dsi_phy_4nm_8650_cfgs = =3D { .num_dsi_phy =3D 2, .quirks =3D DSI_PHY_7NM_QUIRK_V5_2, }; + +const struct msm_dsi_phy_cfg dsi_phy_3nm_8750_cfgs =3D { + .has_phy_lane =3D true, + .regulator_data =3D dsi_phy_7nm_98000uA_regulators, + .num_regulators =3D ARRAY_SIZE(dsi_phy_7nm_98000uA_regulators), + .ops =3D { + .enable =3D dsi_7nm_phy_enable, + .disable =3D dsi_7nm_phy_disable, + .pll_init =3D dsi_pll_7nm_init, + .save_pll_state =3D dsi_7nm_pll_save_state, + .restore_pll_state =3D dsi_7nm_pll_restore_state, + .set_continuous_clock =3D dsi_7nm_set_continuous_clock, + }, + .min_pll_rate =3D 600000000UL, +#ifdef CONFIG_64BIT + .max_pll_rate =3D 5000000000UL, +#else + .max_pll_rate =3D ULONG_MAX, +#endif + .io_start =3D { 0xae95000, 0xae97000 }, + .num_dsi_phy =3D 2, + .quirks =3D DSI_PHY_7NM_QUIRK_V7_0, +}; diff --git a/drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml b/driver= s/gpu/drm/msm/registers/display/dsi_phy_7nm.xml index d2c8c46bb04159da6e539bfe80a4b5dc9ffdf367..4e5ac0f25dea856a49a1523f59c= 60b7f7769c1c2 100644 --- a/drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml +++ b/drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml @@ -26,6 +26,7 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org/free= dreno/ rules-fd.xsd"> + @@ -191,11 +192,24 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org/= freedreno/ rules-fd.xsd"> + + --=20 2.43.0 From nobody Mon Feb 9 08:04:22 2026 Received: from mail-ej1-f46.google.com (mail-ej1-f46.google.com [209.85.218.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 14CFA21B9DB for ; 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[78.11.220.99]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-abbaa56026fsm865456666b.113.2025.02.21.07.25.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2025 07:25:20 -0800 (PST) From: Krzysztof Kozlowski Date: Fri, 21 Feb 2025 16:24:26 +0100 Subject: [PATCH v3 16/21] drm/msm/dsi: Add support for SM8750 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250221-b4-sm8750-display-v3-16-3ea95b1630ea@linaro.org> References: <20250221-b4-sm8750-display-v3-0-3ea95b1630ea@linaro.org> In-Reply-To: <20250221-b4-sm8750-display-v3-0-3ea95b1630ea@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , Jonathan Marek , Kuogee Hsieh , Neil Armstrong Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Srini Kandagatla , Rob Clark X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=7825; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=9j53C1+qnm+aHmA6qWXPPt8RIq215xsppk2s0m9XEYw=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBnuJq6fZFNiQhk0030EBCJGxRTKgBFX5NHNk4ZU ZoNQLabWNiJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZ7iaugAKCRDBN2bmhouD 15kJD/0UG9LYrnX2e7uYAMFVHbfS9/aCJ9iWHI2ct+K4jPQqzz8I6JmELZMAlY0xPE1Gqsxo3OZ Z6e6juvBVf6Rtk1/e87bSnyQB/YbEYzO1w17RNHJX4rQAnq3WWa5ARfeWmkymKy7uD7eGkbPKh6 4ppd/jES2p7r/D6RGvLkFFFAqhYueRu14iTxyN1+C67stDTYD7TyGCxC6Db9E+cqvetLA4SVKpo zmDKfquQ78+JvEXxCc6Aptup9WnmGxn7AN7u/GM9LKcRD4VXX+WUZnHs8p3Ie5BLSucFUlS3wB4 B9J7iLht8KLr/RRNmsznN+nx3VvSeSuoy01xoXeEDo6OP2ayLznej8jGDPjyIX+GloNgNLCZVda WHKd3Jb4ba6zzG1VRdVb0ggeV3u4Di7oZNMGjTwEcBPEN6VDegHobjyIl7nRho2IZguBB4luILX LNsceffuLE8VOqQ3gcSXhi05HuG40BUlGULsWSskNyZhCBGtsTSYIAscw4YGNhV6Uj80WNf8WMZ 0HPMCfe2hLeaR10sapfYnY0fMoTMKi0ZLpsAVUF0u4tWW0zsEXZ+lCxxlW8eUhdWtCNUWgargw0 r0Go6WGbYJWhCMFCTwBrxB23Lo61tCg9AtaEZnuWzwnIKzUe20EZRCBwhii/kj70MR8PpuXqvCG 94dkI/u47Hyz5IQ== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Add support for DSI on Qualcomm SM8750 SoC with notable difference: DSI PHY PLLs, the parents of pixel and byte clocks, cannot be used as parents before DSI PHY is configured and the PLLs are prepared with initial rate is set. Therefore assigned-clock-parents are not working here and driver is responsible for reparenting clocks with proper procedure: see dsi_clk_init_6g_v2_9(). Part of the change is exactly the same as CLK_OPS_PARENT_ENABLE, however CLK_OPS_PARENT_ENABLE won't work here because assigned-clock-parents are executed way too early - before DSI PHY is configured. Signed-off-by: Krzysztof Kozlowski --- Changes in v3: 1. Drop 'struct msm_dsi_config sm8750_dsi_cfg' and use sm8650 one. SM8750 DSI PHY also needs Dmitry's patch: https://patchwork.freedesktop.org/patch/542000/?series=3D119177&rev=3D1 (or some other way of correct early setting of the DSI PHY PLL rate) --- drivers/gpu/drm/msm/dsi/dsi.h | 2 + drivers/gpu/drm/msm/dsi/dsi_cfg.c | 14 +++++++ drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 + drivers/gpu/drm/msm/dsi/dsi_host.c | 80 ++++++++++++++++++++++++++++++++++= ++++ 4 files changed, 97 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h index 87496db203d6c7582eadcb74e94eb56a219df292..93c028a122f3a59b1632da76472= e0a3e781c6ae8 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.h +++ b/drivers/gpu/drm/msm/dsi/dsi.h @@ -98,6 +98,7 @@ int msm_dsi_host_init(struct msm_dsi *msm_dsi); int msm_dsi_runtime_suspend(struct device *dev); int msm_dsi_runtime_resume(struct device *dev); int dsi_link_clk_set_rate_6g(struct msm_dsi_host *msm_host); +int dsi_link_clk_set_rate_6g_v2_9(struct msm_dsi_host *msm_host); int dsi_link_clk_set_rate_v2(struct msm_dsi_host *msm_host); int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host); int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host); @@ -115,6 +116,7 @@ int dsi_dma_base_get_6g(struct msm_dsi_host *msm_host, = uint64_t *iova); int dsi_dma_base_get_v2(struct msm_dsi_host *msm_host, uint64_t *iova); int dsi_clk_init_v2(struct msm_dsi_host *msm_host); int dsi_clk_init_6g_v2(struct msm_dsi_host *msm_host); +int dsi_clk_init_6g_v2_9(struct msm_dsi_host *msm_host); int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_bonded_dsi= ); int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_bonded_dsi= ); void msm_dsi_host_snapshot(struct msm_disp_state *disp_state, struct mipi_= dsi_host *host); diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c b/drivers/gpu/drm/msm/dsi/ds= i_cfg.c index 7754dcec33d06e3d6eb8a9d55e53f24af073adb9..7f8a8de0897a579a525b466fd01= bbcd95454c614 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c @@ -257,6 +257,18 @@ static const struct msm_dsi_host_cfg_ops msm_dsi_6g_v2= _host_ops =3D { .calc_clk_rate =3D dsi_calc_clk_rate_6g, }; =20 +static const struct msm_dsi_host_cfg_ops msm_dsi_6g_v2_9_host_ops =3D { + .link_clk_set_rate =3D dsi_link_clk_set_rate_6g_v2_9, + .link_clk_enable =3D dsi_link_clk_enable_6g, + .link_clk_disable =3D dsi_link_clk_disable_6g, + .clk_init_ver =3D dsi_clk_init_6g_v2_9, + .tx_buf_alloc =3D dsi_tx_buf_alloc_6g, + .tx_buf_get =3D dsi_tx_buf_get_6g, + .tx_buf_put =3D dsi_tx_buf_put_6g, + .dma_base_get =3D dsi_dma_base_get_6g, + .calc_clk_rate =3D dsi_calc_clk_rate_6g, +}; + static const struct msm_dsi_cfg_handler dsi_cfg_handlers[] =3D { {MSM_DSI_VER_MAJOR_V2, MSM_DSI_V2_VER_MINOR_8064, &apq8064_dsi_cfg, &msm_dsi_v2_host_ops}, @@ -300,6 +312,8 @@ static const struct msm_dsi_cfg_handler dsi_cfg_handler= s[] =3D { &sm8550_dsi_cfg, &msm_dsi_6g_v2_host_ops}, {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_8_0, &sm8650_dsi_cfg, &msm_dsi_6g_v2_host_ops}, + {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_9_0, + &sm8650_dsi_cfg, &msm_dsi_6g_v2_9_host_ops}, }; =20 const struct msm_dsi_cfg_handler *msm_dsi_cfg_get(u32 major, u32 minor) diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.h b/drivers/gpu/drm/msm/dsi/ds= i_cfg.h index 120cb65164c1ba1deb9acb513e5f073bd560c496..859c279afbb0377d16f8406f3e6= b083640aff5a1 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.h +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.h @@ -30,6 +30,7 @@ #define MSM_DSI_6G_VER_MINOR_V2_6_0 0x20060000 #define MSM_DSI_6G_VER_MINOR_V2_7_0 0x20070000 #define MSM_DSI_6G_VER_MINOR_V2_8_0 0x20080000 +#define MSM_DSI_6G_VER_MINOR_V2_9_0 0x20090000 =20 #define MSM_DSI_V2_VER_MINOR_8064 0x0 =20 diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/d= si_host.c index 2218d4f0c5130a0b13f428e89aa30ba2921da572..ced28ee61eedc0a82da9f1d0792= f17ee2a5538c4 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -119,6 +119,15 @@ struct msm_dsi_host { struct clk *pixel_clk; struct clk *byte_intf_clk; =20 + /* + * Clocks which needs to be properly parented between DISPCC and DSI PHY + * PLL: + */ + struct clk *byte_src_clk; + struct clk *pixel_src_clk; + struct clk *dsi_pll_byte_clk; + struct clk *dsi_pll_pixel_clk; + unsigned long byte_clk_rate; unsigned long byte_intf_clk_rate; unsigned long pixel_clk_rate; @@ -269,6 +278,38 @@ int dsi_clk_init_6g_v2(struct msm_dsi_host *msm_host) return ret; } =20 +int dsi_clk_init_6g_v2_9(struct msm_dsi_host *msm_host) +{ + struct device *dev =3D &msm_host->pdev->dev; + int ret; + + ret =3D dsi_clk_init_6g_v2(msm_host); + if (ret) + return ret; + + msm_host->byte_src_clk =3D devm_clk_get(dev, "byte_src"); + if (IS_ERR(msm_host->byte_src_clk)) + return dev_err_probe(dev, PTR_ERR(msm_host->byte_src_clk), + "can't get byte_src clock\n"); + + msm_host->dsi_pll_byte_clk =3D devm_clk_get(dev, "dsi_pll_byte"); + if (IS_ERR(msm_host->dsi_pll_byte_clk)) + return dev_err_probe(dev, PTR_ERR(msm_host->dsi_pll_byte_clk), + "can't get dsi_pll_byte clock\n"); + + msm_host->pixel_src_clk =3D devm_clk_get(dev, "pixel_src"); + if (IS_ERR(msm_host->pixel_src_clk)) + return dev_err_probe(dev, PTR_ERR(msm_host->pixel_src_clk), + "can't get pixel_src clock\n"); + + msm_host->dsi_pll_pixel_clk =3D devm_clk_get(dev, "dsi_pll_pixel"); + if (IS_ERR(msm_host->dsi_pll_pixel_clk)) + return dev_err_probe(dev, PTR_ERR(msm_host->dsi_pll_pixel_clk), + "can't get dsi_pll_pixel clock\n"); + + return 0; +} + static int dsi_clk_init(struct msm_dsi_host *msm_host) { struct platform_device *pdev =3D msm_host->pdev; @@ -370,6 +411,45 @@ int dsi_link_clk_set_rate_6g(struct msm_dsi_host *msm_= host) return 0; } =20 +int dsi_link_clk_set_rate_6g_v2_9(struct msm_dsi_host *msm_host) +{ + struct device *dev =3D &msm_host->pdev->dev; + int ret; + + /* + * DSI PHY PLLs have to be enabled to allow reparenting to them and + * setting the rates of pixel/byte clocks. + */ + ret =3D clk_prepare_enable(msm_host->dsi_pll_byte_clk); + if (ret) { + dev_err(dev, "Failed to enable dsi_pll_byte: %d\n", ret); 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[78.11.220.99]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-abbaa56026fsm865456666b.113.2025.02.21.07.25.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2025 07:25:22 -0800 (PST) From: Krzysztof Kozlowski Date: Fri, 21 Feb 2025 16:24:27 +0100 Subject: [PATCH v3 17/21] drm/msm/dpu: Add support for SM8750 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250221-b4-sm8750-display-v3-17-3ea95b1630ea@linaro.org> References: <20250221-b4-sm8750-display-v3-0-3ea95b1630ea@linaro.org> In-Reply-To: <20250221-b4-sm8750-display-v3-0-3ea95b1630ea@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , Jonathan Marek , Kuogee Hsieh , Neil Armstrong Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Srini Kandagatla , Rob Clark X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=18840; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=AtZqwJjbep/uQ2d6uMZ8Cx5QXKDXoYgGQ6nWNFQqAKU=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBnuJq7y+cb403s0m399Mdgn6jABWJymrcHu101K 5waeKuBHDSJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZ7iauwAKCRDBN2bmhouD 19wbD/9RNnjiiJ+tZbzcs1fEYU2BU4MCo9hqtxct3BFOpXWIsnkgi/ezbn6kLDTtB4LPwtkATEI a7LytwwLJHPNCkyn0VcXFJcOiuE7fXo3Uce7oWy79KoFwxwSOlZAqyUG0LE/UADHT8XfJ3RjNZF 4ju/4dqW1oa33x8keoE9Zo8ju9kigqpUfXosBuZKrHaGbPhyw4/tVZUu/S7jNizys6wnKwWGHLd vtzbbTON7U6QZDaB6gVRT75BxhHmdVntdvuHlHe8bKrP/dKH3VIJHEw+s2a6Nhjb9u4lwBomJ0N LRSVTu4wFPCtSKVmIFwS9W7sfhlm3m+msmqkidqw2a7TcJt1Jpb04eW/ooVQ4Yur3b9sn4x7XiL qvrmpWHMwd1dAqIddR5QnBY0qTRAH5f7BuBLyAuvQl/HgsA4MZAzCoMJCJQj24FRFH7XWoqQay9 Avtp4m+9oBenEcoUOHqqdy5oEmEOPchfWclZDFp+NNRrhFqzqwJzJwhPas0u4uuzbbkLm0JPtNt qjTsiJgul0rytoSHmw+Z1M+pqwL6xJNKOSLgXPfXv8dSFdGZ3ykTa2vPa7l0v6rc1qpCpDWk7Rq qndF/lTpe1ifxbmp/+uA2ohWGflAozf9D3qrYvUqYkWwAQslPsDUmv4KzQoxpIeLh+9A5kOzZE9 Bq244jBhTd8xBMw== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Add DPU version v12.0 support for the Qualcomm SM8750 platform. Reviewed-by: Dmitry Baryshkov Signed-off-by: Krzysztof Kozlowski --- Changes in v2: 1. Add CDM --- .../drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h | 496 +++++++++++++++++= ++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 29 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + 4 files changed, 527 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h new file mode 100644 index 0000000000000000000000000000000000000000..aa0f861d6661a65854e1978afcf= cdcd342f2ce1c --- /dev/null +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h @@ -0,0 +1,496 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2025 Linaro Limited + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. + */ + +#ifndef _DPU_12_0_SM8750_H +#define _DPU_12_0_SM8750_H + +static const struct dpu_caps sm8750_dpu_caps =3D { + .max_mixer_width =3D DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .max_mixer_blendstages =3D 0xb, + .has_src_split =3D true, + .has_dim_layer =3D true, + .has_idle_pc =3D true, + .has_3d_merge =3D true, + .max_linewidth =3D 8192, + .pixel_ram_size =3D DEFAULT_PIXEL_RAM_SIZE, +}; + +static const struct dpu_mdp_cfg sm8750_mdp =3D { + .name =3D "top_0", + .base =3D 0, .len =3D 0x494, + .clk_ctrls =3D { + [DPU_CLK_CTRL_REG_DMA] =3D { .reg_off =3D 0x2bc, .bit_off =3D 20 }, + }, +}; + +static const struct dpu_ctl_cfg sm8750_ctl[] =3D { + { + .name =3D "ctl_0", .id =3D CTL_0, + .base =3D 0x15000, .len =3D 0x1000, + .has_split_display =3D 1, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), + }, { + .name =3D "ctl_1", .id =3D CTL_1, + .base =3D 0x16000, .len =3D 0x1000, + .has_split_display =3D 1, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), + }, { + .name =3D "ctl_2", .id =3D CTL_2, + .base =3D 0x17000, .len =3D 0x1000, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), + }, { + .name =3D "ctl_3", .id =3D CTL_3, + .base =3D 0x18000, .len =3D 0x1000, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), + }, { + .name =3D "ctl_4", .id =3D CTL_4, + .base =3D 0x19000, .len =3D 0x1000, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), + }, { + .name =3D "ctl_5", .id =3D CTL_5, + .base =3D 0x1a000, .len =3D 0x1000, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), + }, +}; + +static const struct dpu_sspp_cfg sm8750_sspp[] =3D { + { + .name =3D "sspp_0", .id =3D SSPP_VIG0, + .base =3D 0x4000, .len =3D 0x344, + .features =3D VIG_SDM845_MASK_SDMA, + .sblk =3D &dpu_vig_sblk_qseed3_3_4, + .xin_id =3D 0, + .type =3D SSPP_TYPE_VIG, + }, { + .name =3D "sspp_1", .id =3D SSPP_VIG1, + .base =3D 0x6000, .len =3D 0x344, + .features =3D VIG_SDM845_MASK_SDMA, + .sblk =3D &dpu_vig_sblk_qseed3_3_4, + .xin_id =3D 4, + .type =3D SSPP_TYPE_VIG, + }, { + .name =3D "sspp_2", .id =3D SSPP_VIG2, + .base =3D 0x8000, .len =3D 0x344, + .features =3D VIG_SDM845_MASK_SDMA, + .sblk =3D &dpu_vig_sblk_qseed3_3_4, + .xin_id =3D 8, + .type =3D SSPP_TYPE_VIG, + }, { + .name =3D "sspp_3", .id =3D SSPP_VIG3, + .base =3D 0xa000, .len =3D 0x344, + .features =3D VIG_SDM845_MASK_SDMA, + .sblk =3D &dpu_vig_sblk_qseed3_3_4, + .xin_id =3D 12, + .type =3D SSPP_TYPE_VIG, + }, { + .name =3D "sspp_8", .id =3D SSPP_DMA0, + .base =3D 0x24000, .len =3D 0x344, + .features =3D DMA_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 1, + .type =3D SSPP_TYPE_DMA, + }, { + .name =3D "sspp_9", .id =3D SSPP_DMA1, + .base =3D 0x26000, .len =3D 0x344, + .features =3D DMA_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 5, + .type =3D SSPP_TYPE_DMA, + }, { + .name =3D "sspp_10", .id =3D SSPP_DMA2, + .base =3D 0x28000, .len =3D 0x344, + .features =3D DMA_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 9, + .type =3D SSPP_TYPE_DMA, + }, { + .name =3D "sspp_11", .id =3D SSPP_DMA3, + .base =3D 0x2a000, .len =3D 0x344, + .features =3D DMA_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 13, + .type =3D SSPP_TYPE_DMA, + }, { + .name =3D "sspp_12", .id =3D SSPP_DMA4, + .base =3D 0x2c000, .len =3D 0x344, + .features =3D DMA_CURSOR_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 14, + .type =3D SSPP_TYPE_DMA, + }, { + .name =3D "sspp_13", .id =3D SSPP_DMA5, + .base =3D 0x2e000, .len =3D 0x344, + .features =3D DMA_CURSOR_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 15, + .type =3D SSPP_TYPE_DMA, + }, +}; + +static const struct dpu_lm_cfg sm8750_lm[] =3D { + { + .name =3D "lm_0", .id =3D LM_0, + .base =3D 0x44000, .len =3D 0x400, + .sourcesplit =3D 1, + .sblk =3D &sm8750_lm_sblk, + .lm_pair =3D LM_1, + .pingpong =3D PINGPONG_0, + .dspp =3D DSPP_0, + }, { + .name =3D "lm_1", .id =3D LM_1, + .base =3D 0x45000, .len =3D 0x400, + .sourcesplit =3D 1, + .sblk =3D &sm8750_lm_sblk, + .lm_pair =3D LM_0, + .pingpong =3D PINGPONG_1, + .dspp =3D DSPP_1, + }, { + .name =3D "lm_2", .id =3D LM_2, + .base =3D 0x46000, .len =3D 0x400, + .sourcesplit =3D 1, + .sblk =3D &sm8750_lm_sblk, + .lm_pair =3D LM_3, + .pingpong =3D PINGPONG_2, + .dspp =3D DSPP_2, + }, { + .name =3D "lm_3", .id =3D LM_3, + .base =3D 0x47000, .len =3D 0x400, + .sourcesplit =3D 1, + .sblk =3D &sm8750_lm_sblk, + .lm_pair =3D LM_2, + .pingpong =3D PINGPONG_3, + .dspp =3D DSPP_3, + }, { + .name =3D "lm_4", .id =3D LM_4, + .base =3D 0x48000, .len =3D 0x400, + .sourcesplit =3D 1, + .sblk =3D &sm8750_lm_sblk, + .lm_pair =3D LM_5, + .pingpong =3D PINGPONG_4, + }, { + .name =3D "lm_5", .id =3D LM_5, + .base =3D 0x49000, .len =3D 0x400, + .sourcesplit =3D 1, + .sblk =3D &sm8750_lm_sblk, + .lm_pair =3D LM_4, + .pingpong =3D PINGPONG_5, + }, { + .name =3D "lm_6", .id =3D LM_6, + .base =3D 0x4a000, .len =3D 0x400, + .sourcesplit =3D 1, + .sblk =3D &sm8750_lm_sblk, + .lm_pair =3D LM_7, + .pingpong =3D PINGPONG_6, + }, { + .name =3D "lm_7", .id =3D LM_7, + .base =3D 0x4b000, .len =3D 0x400, + .sourcesplit =3D 1, + .sblk =3D &sm8750_lm_sblk, + .lm_pair =3D LM_6, + .pingpong =3D PINGPONG_7, + }, +}; + +static const struct dpu_dspp_cfg sm8750_dspp[] =3D { + { + .name =3D "dspp_0", .id =3D DSPP_0, + .base =3D 0x54000, .len =3D 0x1800, + .sblk =3D &sm8750_dspp_sblk, + }, { + .name =3D "dspp_1", .id =3D DSPP_1, + .base =3D 0x56000, .len =3D 0x1800, + .sblk =3D &sm8750_dspp_sblk, + }, { + .name =3D "dspp_2", .id =3D DSPP_2, + .base =3D 0x58000, .len =3D 0x1800, + .sblk =3D &sm8750_dspp_sblk, + }, { + .name =3D "dspp_3", .id =3D DSPP_3, + .base =3D 0x5a000, .len =3D 0x1800, + .sblk =3D &sm8750_dspp_sblk, + }, +}; + +static const struct dpu_pingpong_cfg sm8750_pp[] =3D { + { + .name =3D "pingpong_0", .id =3D PINGPONG_0, + .base =3D 0x69000, .len =3D 0, + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_0, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + }, { + .name =3D "pingpong_1", .id =3D PINGPONG_1, + .base =3D 0x6a000, .len =3D 0, + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_0, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), + }, { + .name =3D "pingpong_2", .id =3D PINGPONG_2, + .base =3D 0x6b000, .len =3D 0, + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_1, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), + }, { + .name =3D "pingpong_3", .id =3D PINGPONG_3, + .base =3D 0x6c000, .len =3D 0, + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_1, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), + }, { + .name =3D "pingpong_4", .id =3D PINGPONG_4, + .base =3D 0x6d000, .len =3D 0, + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_2, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), + }, { + .name =3D "pingpong_5", .id =3D PINGPONG_5, + .base =3D 0x6e000, .len =3D 0, + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_2, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), + }, { + .name =3D "pingpong_6", .id =3D PINGPONG_6, + .base =3D 0x6f000, .len =3D 0, + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_3, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 20), + }, { + .name =3D "pingpong_7", .id =3D PINGPONG_7, + .base =3D 0x70000, .len =3D 0, + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_3, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 21), + }, { + .name =3D "pingpong_cwb_0", .id =3D PINGPONG_CWB_0, + .base =3D 0x66000, .len =3D 0, + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_4, + }, { + .name =3D "pingpong_cwb_1", .id =3D PINGPONG_CWB_1, + .base =3D 0x66400, .len =3D 0, + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_4, + }, { + .name =3D "pingpong_cwb_2", .id =3D PINGPONG_CWB_2, + .base =3D 0x7e000, .len =3D 0, + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_5, + }, { + .name =3D "pingpong_cwb_3", .id =3D PINGPONG_CWB_3, + .base =3D 0x7e400, .len =3D 0, + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_5, + }, +}; + +static const struct dpu_merge_3d_cfg sm8750_merge_3d[] =3D { + { + .name =3D "merge_3d_0", .id =3D MERGE_3D_0, + .base =3D 0x4e000, .len =3D 0x1c, + }, { + .name =3D "merge_3d_1", .id =3D MERGE_3D_1, + .base =3D 0x4f000, .len =3D 0x1c, + }, { + .name =3D "merge_3d_2", .id =3D MERGE_3D_2, + .base =3D 0x50000, .len =3D 0x1c, + }, { + .name =3D "merge_3d_3", .id =3D MERGE_3D_3, + .base =3D 0x51000, .len =3D 0x1c, + }, { + .name =3D "merge_3d_4", .id =3D MERGE_3D_4, + .base =3D 0x66700, .len =3D 0x1c, + }, { + .name =3D "merge_3d_5", .id =3D MERGE_3D_5, + .base =3D 0x7e700, .len =3D 0x1c, + }, +}; + +/* + * NOTE: Each display compression engine (DCE) contains dual hard + * slice DSC encoders so both share same base address but with + * its own different sub block address. + */ +static const struct dpu_dsc_cfg sm8750_dsc[] =3D { + { + .name =3D "dce_0_0", .id =3D DSC_0, + .base =3D 0x80000, .len =3D 0x8, + .have_native_42x =3D 1, + .sblk =3D &sm8750_dsc_sblk_0, + }, { + .name =3D "dce_0_1", .id =3D DSC_1, + .base =3D 0x80000, .len =3D 0x8, + .have_native_42x =3D 1, + .sblk =3D &sm8750_dsc_sblk_1, + }, { + .name =3D "dce_1_0", .id =3D DSC_2, + .base =3D 0x81000, .len =3D 0x8, + .have_native_42x =3D 1, + .sblk =3D &sm8750_dsc_sblk_0, + }, { + .name =3D "dce_1_1", .id =3D DSC_3, + .base =3D 0x81000, .len =3D 0x8, + .have_native_42x =3D 1, + .sblk =3D &sm8750_dsc_sblk_1, + }, { + .name =3D "dce_2_0", .id =3D DSC_4, + .base =3D 0x82000, .len =3D 0x8, + .have_native_42x =3D 1, + .sblk =3D &sm8750_dsc_sblk_0, + }, { + .name =3D "dce_2_1", .id =3D DSC_5, + .base =3D 0x82000, .len =3D 0x8, + .have_native_42x =3D 1, + .sblk =3D &sm8750_dsc_sblk_1, + }, { + .name =3D "dce_3_0", .id =3D DSC_6, + .base =3D 0x83000, .len =3D 0x8, + .have_native_42x =3D 1, + .sblk =3D &sm8750_dsc_sblk_0, + }, { + .name =3D "dce_3_1", .id =3D DSC_7, + .base =3D 0x83000, .len =3D 0x8, + .have_native_42x =3D 1, + .sblk =3D &sm8750_dsc_sblk_1, + }, +}; + +static const struct dpu_wb_cfg sm8750_wb[] =3D { + { + .name =3D "wb_2", .id =3D WB_2, + .base =3D 0x65000, .len =3D 0x2c8, + .features =3D WB_SDM845_MASK, + .format_list =3D wb2_formats_rgb, + .num_formats =3D ARRAY_SIZE(wb2_formats_rgb), + .xin_id =3D 6, + .vbif_idx =3D VBIF_RT, + .maxlinewidth =3D 4096, + .intr_wb_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), + }, +}; + +static const struct dpu_cwb_cfg sm8750_cwb[] =3D { + { + .name =3D "cwb_0", .id =3D CWB_0, + .base =3D 0x66200, .len =3D 0x20, + }, + { + .name =3D "cwb_1", .id =3D CWB_1, + .base =3D 0x66600, .len =3D 0x20, + }, + { + .name =3D "cwb_2", .id =3D CWB_2, + .base =3D 0x7e200, .len =3D 0x20, + }, + { + .name =3D "cwb_3", .id =3D CWB_3, + .base =3D 0x7e600, .len =3D 0x20, + }, +}; + +static const struct dpu_intf_cfg sm8750_intf[] =3D { + { + .name =3D "intf_0", .id =3D INTF_0, + .base =3D 0x34000, .len =3D 0x4bc, + .type =3D INTF_DP, + .controller_id =3D MSM_DP_CONTROLLER_0, + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), + }, { + .name =3D "intf_1", .id =3D INTF_1, + .base =3D 0x35000, .len =3D 0x4bc, + .type =3D INTF_DSI, + .controller_id =3D MSM_DSI_CONTROLLER_0, + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), + .intr_tear_rd_ptr =3D DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), + }, { + .name =3D "intf_2", .id =3D INTF_2, + .base =3D 0x36000, .len =3D 0x4bc, + .type =3D INTF_DSI, + .controller_id =3D MSM_DSI_CONTROLLER_1, + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), + .intr_tear_rd_ptr =3D DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2), + }, { + .name =3D "intf_3", .id =3D INTF_3, + .base =3D 0x37000, .len =3D 0x4bc, + .type =3D INTF_DP, + .controller_id =3D MSM_DP_CONTROLLER_1, + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), + }, +}; + +static const struct dpu_perf_cfg sm8750_perf_data =3D { + .max_bw_low =3D 18900000, + .max_bw_high =3D 28500000, + .min_core_ib =3D 2500000, + .min_llcc_ib =3D 0, + .min_dram_ib =3D 800000, + .min_prefill_lines =3D 35, + .danger_lut_tbl =3D {0x3ffff, 0x3ffff, 0x0}, + .safe_lut_tbl =3D {0xfe00, 0xfe00, 0xffff}, + .qos_lut_tbl =3D { + {.nentry =3D ARRAY_SIZE(sc7180_qos_linear), + .entries =3D sc7180_qos_linear + }, + {.nentry =3D ARRAY_SIZE(sc7180_qos_macrotile), + .entries =3D sc7180_qos_macrotile + }, + {.nentry =3D ARRAY_SIZE(sc7180_qos_nrt), + .entries =3D sc7180_qos_nrt + }, + /* TODO: macrotile-qseed is different from macrotile */ + }, + .cdp_cfg =3D { + {.rd_enable =3D 1, .wr_enable =3D 1}, + {.rd_enable =3D 1, .wr_enable =3D 0} + }, + .clk_inefficiency_factor =3D 105, + .bw_inefficiency_factor =3D 120, +}; + +static const struct dpu_mdss_version sm8750_mdss_ver =3D { + .core_major_ver =3D 12, + .core_minor_ver =3D 0, +}; + +const struct dpu_mdss_cfg dpu_sm8750_cfg =3D { + .mdss_ver =3D &sm8750_mdss_ver, + .caps =3D &sm8750_dpu_caps, + .mdp =3D &sm8750_mdp, + .cdm =3D &sc7280_cdm, + .ctl_count =3D ARRAY_SIZE(sm8750_ctl), + .ctl =3D sm8750_ctl, + .sspp_count =3D ARRAY_SIZE(sm8750_sspp), + .sspp =3D sm8750_sspp, + .mixer_count =3D ARRAY_SIZE(sm8750_lm), + .mixer =3D sm8750_lm, + .dspp_count =3D ARRAY_SIZE(sm8750_dspp), + .dspp =3D sm8750_dspp, + .pingpong_count =3D ARRAY_SIZE(sm8750_pp), + .pingpong =3D sm8750_pp, + .dsc_count =3D ARRAY_SIZE(sm8750_dsc), + .dsc =3D sm8750_dsc, + .merge_3d_count =3D ARRAY_SIZE(sm8750_merge_3d), + .merge_3d =3D sm8750_merge_3d, + .wb_count =3D ARRAY_SIZE(sm8750_wb), + .wb =3D sm8750_wb, + .cwb_count =3D ARRAY_SIZE(sm8750_cwb), + .cwb =3D sm8650_cwb, + .intf_count =3D ARRAY_SIZE(sm8750_intf), + .intf =3D sm8750_intf, + .vbif_count =3D ARRAY_SIZE(sm8650_vbif), + .vbif =3D sm8650_vbif, + .perf =3D &sm8750_perf_data, +}; + +#endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.c index 4ff29be965c39b29cf7e3b9761634b7f39ca97b0..a0559f63d602e6081b53c209ccd= 74ccdf1a4b38d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -354,6 +354,9 @@ static const struct dpu_sspp_sub_blks dpu_vig_sblk_qsee= d3_3_2 =3D static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_3_3 =3D _VIG_SBLK(SSPP_SCALER_VER(3, 3)); =20 +static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_3_4 =3D + _VIG_SBLK(SSPP_SCALER_VER(3, 4)); + static const struct dpu_sspp_sub_blks dpu_rgb_sblk =3D _RGB_SBLK(); =20 static const struct dpu_sspp_sub_blks dpu_dma_sblk =3D _DMA_SBLK(); @@ -388,6 +391,16 @@ static const struct dpu_lm_sub_blks sc7180_lm_sblk =3D= { }, }; =20 +static const struct dpu_lm_sub_blks sm8750_lm_sblk =3D { + .maxwidth =3D DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .maxblendstages =3D 11, /* excluding base layer */ + .blendstage_base =3D { /* offsets relative to mixer base */ + /* 0x40 + n*0x30 */ + 0x40, 0x70, 0xa0, 0xd0, 0x100, 0x130, 0x160, 0x190, 0x1c0, + 0x1f0, 0x220 + }, +}; + static const struct dpu_lm_sub_blks qcm2290_lm_sblk =3D { .maxwidth =3D DEFAULT_DPU_LINE_WIDTH, .maxblendstages =3D 4, /* excluding base layer */ @@ -409,6 +422,11 @@ static const struct dpu_dspp_sub_blks sdm845_dspp_sblk= =3D { .len =3D 0x90, .version =3D 0x40000}, }; =20 +static const struct dpu_dspp_sub_blks sm8750_dspp_sblk =3D { + .pcc =3D {.name =3D "pcc", .base =3D 0x1700, + .len =3D 0x90, .version =3D 0x60000}, +}; + /************************************************************* * PINGPONG sub blocks config *************************************************************/ @@ -451,6 +469,16 @@ static const struct dpu_dsc_sub_blks dsc_sblk_1 =3D { .ctl =3D {.name =3D "ctl", .base =3D 0xF80, .len =3D 0x10}, }; =20 +static const struct dpu_dsc_sub_blks sm8750_dsc_sblk_0 =3D { + .enc =3D {.name =3D "enc", .base =3D 0x100, .len =3D 0x100}, + .ctl =3D {.name =3D "ctl", .base =3D 0xF00, .len =3D 0x24}, +}; + +static const struct dpu_dsc_sub_blks sm8750_dsc_sblk_1 =3D { + .enc =3D {.name =3D "enc", .base =3D 0x200, .len =3D 0x100}, + .ctl =3D {.name =3D "ctl", .base =3D 0xF80, .len =3D 0x24}, +}; + /************************************************************* * CDM block config *************************************************************/ @@ -734,3 +762,4 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = =3D { #include "catalog/dpu_9_2_x1e80100.h" =20 #include "catalog/dpu_10_0_sm8650.h" +#include "catalog/dpu_12_0_sm8750.h" diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index f5ce35cd966459f0edf2dbdd2dbc2693779fac73..de124b722340e98dc78999af1e0= ff50bd65a53c2 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -749,6 +749,7 @@ extern const struct dpu_mdss_cfg dpu_sm8450_cfg; extern const struct dpu_mdss_cfg dpu_sa8775p_cfg; extern const struct dpu_mdss_cfg dpu_sm8550_cfg; extern const struct dpu_mdss_cfg dpu_sm8650_cfg; +extern const struct dpu_mdss_cfg dpu_sm8750_cfg; extern const struct dpu_mdss_cfg dpu_x1e80100_cfg; =20 #endif /* _DPU_HW_CATALOG_H */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/= disp/dpu1/dpu_kms.c index 1112f69dde87c95c34c3b76c78452954e7a20612..013e1eca74c8f0d6328d3064e3a= 9275b1a2aacb9 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1515,6 +1515,7 @@ static const struct of_device_id dpu_dt_match[] =3D { { .compatible =3D "qcom,sm8450-dpu", .data =3D &dpu_sm8450_cfg, }, { .compatible =3D "qcom,sm8550-dpu", .data =3D &dpu_sm8550_cfg, }, { .compatible =3D "qcom,sm8650-dpu", .data =3D &dpu_sm8650_cfg, }, + { .compatible =3D "qcom,sm8750-dpu", .data =3D &dpu_sm8750_cfg, }, { .compatible =3D "qcom,x1e80100-dpu", .data =3D &dpu_x1e80100_cfg, }, {} }; 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[78.11.220.99]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-abbaa56026fsm865456666b.113.2025.02.21.07.25.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2025 07:25:24 -0800 (PST) From: Krzysztof Kozlowski Date: Fri, 21 Feb 2025 16:24:28 +0100 Subject: [PATCH v3 18/21] drm/msm/dpu: Implement 10-bit color alpha for v12.0 DPU Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250221-b4-sm8750-display-v3-18-3ea95b1630ea@linaro.org> References: <20250221-b4-sm8750-display-v3-0-3ea95b1630ea@linaro.org> In-Reply-To: <20250221-b4-sm8750-display-v3-0-3ea95b1630ea@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , Jonathan Marek , Kuogee Hsieh , Neil Armstrong Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Srini Kandagatla , Rob Clark X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=7483; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=i/FODMQhwxbBlhCIaZyHIeOVaGHwHSyiYROFPJEEFYE=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBnuJq8Cvym97PKIU6g/ay2kUeu659IUl/1AsRQw F4MR/4YI/qJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZ7iavAAKCRDBN2bmhouD 1zbBD/45+OGbzBG4sDY+nY8bmg0B9dd0wjyyK96MI3PhkMR1yJcLUiI/ukf0E7ZjNgEOnUFbpLG +KgL3R/dO9hg7Hnh+A+7l2i2mWBw5LqH0K1pJbVbxHWGZZJCuKu5XcVfZ2xaNyjQqKUYaIWPCK2 vsBvNcYopWRzdftWOLE9mycZmydWU3EH+JkryBVs+0qD0zULKxdKbQoxZ8xlXKEN7g4hiGx/WvP fVhPlWuwnrZDSydlQZko3p4Wm6IVqSlPibL6b2joEYePsWL1ddLjVj3zmrr21FRTHjmSHD9cGE+ BUcuDafusJPdm4LKb+oc7A+mf6zsy0H9U360M+xaxleglQ3VupH94J1CYFurQq9Ufmt2VL7G2/7 7bU9IVgcMBfpJWDUU+R0MNe6nZIQmDaxfPcCCKwbFhEgKlnXt8V/s5c3bgu81qXexAYpjEPijc0 ybkVbfnYP2pVOW+05uCeGRmPqFZUY+KmuCmZIb7PZeLyv4oUmv8a5xu0G6S4kq2vnH2Guh437XE nvZ4fCdTyHV9lLBwbnIHQeuctoOi0qi5FudpuIz21N5XZn2keJMvS795gCaQHk3kWgLjFrjNgXR LVwz40rEre96opVxxLacSIucHnr5GA53R6VBi676iXinN21vZF+bY7Uy643dP2kd1vegiyeIMIN 2UAsIEvJ12DUbpg== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B v12.0 DPU on SM8750 comes with 10-bit color alpha. Add register differences and new implementations of setup_alpha_out, setup_border_color and so one for this. Signed-off-by: Krzysztof Kozlowski --- Changes in v3: 1. New patch, split from previous big DPU v12.0. --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 20 +++++--- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 84 +++++++++++++++++++++++++++= ++-- 2 files changed, 94 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm= /disp/dpu1/dpu_crtc.c index b9fe3a7343d54f6f8b5aad7982928d5fc728bd61..7a35939ece180c15898b2eaa2f1= f451767c741ae 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -319,15 +319,21 @@ static bool dpu_crtc_get_scanout_position(struct drm_= crtc *crtc, return true; } =20 -static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer, - struct dpu_plane_state *pstate, const struct msm_format *format) +static void _dpu_crtc_setup_blend_cfg(const struct dpu_hw_ctl *ctl, + struct dpu_crtc_mixer *mixer, + struct dpu_plane_state *pstate, + const struct msm_format *format) { struct dpu_hw_mixer *lm =3D mixer->hw_lm; uint32_t blend_op; - uint32_t fg_alpha, bg_alpha; + uint32_t fg_alpha, bg_alpha, max_alpha; =20 fg_alpha =3D pstate->base.alpha >> 8; - bg_alpha =3D 0xff - fg_alpha; + if (ctl->mdss_ver->core_major_ver < 12) + max_alpha =3D 0xff; + else + max_alpha =3D 0x3ff; + bg_alpha =3D max_alpha - fg_alpha; =20 /* default to opaque blending */ if (pstate->base.pixel_blend_mode =3D=3D DRM_MODE_BLEND_PIXEL_NONE || @@ -337,7 +343,7 @@ static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_m= ixer *mixer, } else if (pstate->base.pixel_blend_mode =3D=3D DRM_MODE_BLEND_PREMULTI) { blend_op =3D DPU_BLEND_FG_ALPHA_FG_CONST | DPU_BLEND_BG_ALPHA_FG_PIXEL; - if (fg_alpha !=3D 0xff) { + if (fg_alpha !=3D max_alpha) { bg_alpha =3D fg_alpha; blend_op |=3D DPU_BLEND_BG_MOD_ALPHA | DPU_BLEND_BG_INV_MOD_ALPHA; @@ -348,7 +354,7 @@ static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_m= ixer *mixer, /* coverage blending */ blend_op =3D DPU_BLEND_FG_ALPHA_FG_PIXEL | DPU_BLEND_BG_ALPHA_FG_PIXEL; - if (fg_alpha !=3D 0xff) { + if (fg_alpha !=3D max_alpha) { bg_alpha =3D fg_alpha; blend_op |=3D DPU_BLEND_FG_MOD_ALPHA | DPU_BLEND_FG_INV_MOD_ALPHA | @@ -482,7 +488,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc= *crtc, =20 /* blend config update */ for (lm_idx =3D 0; lm_idx < cstate->num_mixers; lm_idx++) { - _dpu_crtc_setup_blend_cfg(mixer + lm_idx, pstate, format); + _dpu_crtc_setup_blend_cfg(ctl, mixer + lm_idx, pstate, format); =20 if (bg_alpha_enable && !format->alpha_enable) mixer[lm_idx].mixer_op_mode =3D 0; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c b/drivers/gpu/drm/ms= m/disp/dpu1/dpu_hw_lm.c index 3bfb61cb83672dca4236bdbbbfb1e442223576d2..75bf3521b03c8e243ccfe1fc226= aa71f23b296df 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c @@ -19,12 +19,20 @@ =20 /* These register are offset to mixer base + stage base */ #define LM_BLEND0_OP 0x00 + +/* =3D v12 DPU */ +#define LM_BORDER_COLOR_0_V12 0x1C +#define LM_BORDER_COLOR_1_V12 0x20 + +/* >=3D v12 DPU with offset to mixer base + stage base */ +#define LM_BLEND0_CONST_ALPHA_V12 0x08 #define LM_BLEND0_FG_ALPHA 0x04 #define LM_BLEND0_BG_ALPHA 0x08 =20 @@ -83,6 +91,22 @@ static void dpu_hw_lm_setup_border_color(struct dpu_hw_m= ixer *ctx, } } =20 +static void dpu_hw_lm_setup_border_color_v12(struct dpu_hw_mixer *ctx, + struct dpu_mdss_color *color, + u8 border_en) +{ + struct dpu_hw_blk_reg_map *c =3D &ctx->hw; + + if (border_en) { + DPU_REG_WRITE(c, LM_BORDER_COLOR_0_V12, + (color->color_0 & 0x3ff) | + ((color->color_1 & 0x3ff) << 16)); + DPU_REG_WRITE(c, LM_BORDER_COLOR_1_V12, + (color->color_2 & 0x3ff) | + ((color->color_3 & 0x3ff) << 16)); + } +} + static void dpu_hw_lm_setup_misr(struct dpu_hw_mixer *ctx) { dpu_hw_setup_misr(&ctx->hw, LM_MISR_CTRL, 0x0); @@ -112,6 +136,27 @@ static void dpu_hw_lm_setup_blend_config_combined_alph= a(struct dpu_hw_mixer *ctx DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op); } =20 +static void +dpu_hw_lm_setup_blend_config_combined_alpha_v12(struct dpu_hw_mixer *ctx, + u32 stage, u32 fg_alpha, + u32 bg_alpha, u32 blend_op) +{ + struct dpu_hw_blk_reg_map *c =3D &ctx->hw; + int stage_off; + u32 const_alpha; + + if (stage =3D=3D DPU_STAGE_BASE) + return; + + stage_off =3D _stage_offset(ctx, stage); + if (WARN_ON(stage_off < 0)) + return; + + const_alpha =3D (bg_alpha & 0x3ff) | ((fg_alpha & 0x3ff) << 16); + DPU_REG_WRITE(c, LM_BLEND0_CONST_ALPHA_V12 + stage_off, const_alpha); + DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op); +} + static void dpu_hw_lm_setup_blend_config(struct dpu_hw_mixer *ctx, u32 stage, u32 fg_alpha, u32 bg_alpha, u32 blend_op) { @@ -144,6 +189,32 @@ static void dpu_hw_lm_setup_color3(struct dpu_hw_mixer= *ctx, DPU_REG_WRITE(c, LM_OP_MODE, op_mode); } =20 +static void dpu_hw_lm_setup_color3_v12(struct dpu_hw_mixer *ctx, + uint32_t mixer_op_mode) +{ + struct dpu_hw_blk_reg_map *c =3D &ctx->hw; + int op_mode, stages, stage_off, i; + + stages =3D ctx->cap->sblk->maxblendstages; + if (stages <=3D 0) + return; + + for (i =3D DPU_STAGE_0; i <=3D stages; i++) { + stage_off =3D _stage_offset(ctx, i); + if (WARN_ON(stage_off < 0)) + return; + + /* set color_out3 bit in blend0_op when enabled in mixer_op_mode */ + op_mode =3D DPU_REG_READ(c, LM_BLEND0_OP + stage_off); + if (mixer_op_mode & BIT(i)) + op_mode |=3D BIT(30); + else + op_mode &=3D ~BIT(30); + + DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, op_mode); + } +} + /** * dpu_hw_lm_init() - Initializes the mixer hw driver object. * should be called once before accessing every mixer. @@ -175,12 +246,19 @@ struct dpu_hw_mixer *dpu_hw_lm_init(struct drm_device= *dev, c->idx =3D cfg->id; c->cap =3D cfg; c->ops.setup_mixer_out =3D dpu_hw_lm_setup_out; - if (mdss_ver->core_major_ver >=3D 4) + if (mdss_ver->core_major_ver >=3D 12) + c->ops.setup_blend_config =3D dpu_hw_lm_setup_blend_config_combined_alph= a_v12; + else if (mdss_ver->core_major_ver >=3D 4) c->ops.setup_blend_config =3D dpu_hw_lm_setup_blend_config_combined_alph= a; else c->ops.setup_blend_config =3D dpu_hw_lm_setup_blend_config; - c->ops.setup_alpha_out =3D dpu_hw_lm_setup_color3; - c->ops.setup_border_color =3D dpu_hw_lm_setup_border_color; + if (mdss_ver->core_major_ver < 12) { + c->ops.setup_alpha_out =3D dpu_hw_lm_setup_color3; + c->ops.setup_border_color =3D dpu_hw_lm_setup_border_color; + } else { + c->ops.setup_alpha_out =3D dpu_hw_lm_setup_color3_v12; + c->ops.setup_border_color =3D dpu_hw_lm_setup_border_color_v12; + } c->ops.setup_misr =3D dpu_hw_lm_setup_misr; c->ops.collect_misr =3D dpu_hw_lm_collect_misr; =20 --=20 2.43.0 From nobody Mon Feb 9 08:04:22 2026 Received: from mail-ej1-f52.google.com (mail-ej1-f52.google.com [209.85.218.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C1E4921E0BA for ; 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[78.11.220.99]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-abbaa56026fsm865456666b.113.2025.02.21.07.25.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2025 07:25:26 -0800 (PST) From: Krzysztof Kozlowski Date: Fri, 21 Feb 2025 16:24:29 +0100 Subject: [PATCH v3 19/21] drm/msm/dpu: Implement CTL_PIPE_ACTIVE for v12.0 DPU Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250221-b4-sm8750-display-v3-19-3ea95b1630ea@linaro.org> References: <20250221-b4-sm8750-display-v3-0-3ea95b1630ea@linaro.org> In-Reply-To: <20250221-b4-sm8750-display-v3-0-3ea95b1630ea@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , Jonathan Marek , Kuogee Hsieh , Neil Armstrong Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Srini Kandagatla , Rob Clark X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=6467; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=qywHZh1a3AzNu2AoRAPcgEJpAFWbwkzThuNgqprskLA=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBnuJq9LeHb6wqwJ4fYIDJFjxdPiYFofXUuijp0e 8ZcUXdoOf2JAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZ7iavQAKCRDBN2bmhouD 17GuD/9clAoSTnzvQ04droQJutfV/n45X+BvIm8RVIq4dRwjztpie7idFeMufihiRCqlkrLQhqR HZFQ8Ovkisz6WKw5Zgs+AO3rXfuv0/Vs6hRrSoIkaUhG4tpgG/nZ5wPejt02qeU5dgW5uLihZGO tI8oCUp85qRkjLyY/afp1eyic5FPaXOEqGkVW1ekzLEBiiYE03UT20HgNpWhcqjwp1p8kHm+pP2 21r2CC3Q0/m+1h6XPzTjLMf3KMzyJz5I5YNmBuAdpbv0pJPfXkh0Ba3kq2oJ0J24aeK1DcHZw6v Ms4lEUB1yLizQ+rGL8ZSXLsOap4qjuxxmcFm489jADfseTPdpIp61seh7g7NjuGDoXVDorS8VFK pDIJk5aogDhVF/J0DAT7HzCH6Ek0BJBtxD7httkplYN8yN7KmIARL1JD1ngu7TvfYXWBcdtTVj9 J73BjT7jdsMSY6fiPSc+eh6Oe0HJCj6p5pM59w63weHLgek0CtDykmjaR0SLFSYzcbUmtO3iRR0 4E/IwIovsO3oj+BXTZCvXmnYSdWU1JSKDxcRk2XUuqqaBBtDifRXb8SLC/teWAzFYRz8EdXjgaV TzqV5nBrlevZ47iLayKcGHjhHLqgcL1+wxl72ViePwY61FpRWvfT5jbEvwXmbYNwkDseKSkl9d2 +WrfF39F1l+MPug== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B v12.0 DPU on SM8750 comes with new CTL_PIPE_ACTIVE register for selective activation of pipes, which replaces earlier dpu_hw_ctl_setup_blendstage() code path for newer devices. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Dmitry Baryshkov --- Changes in v3: 1. New patch, split from previous big DPU v12.0. --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 9 +++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 3 +++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 29 +++++++++++++++++++++++++= ++-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 8 ++++++++ 4 files changed, 47 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm= /disp/dpu1/dpu_crtc.c index 7a35939ece180c15898b2eaa2f1f451767c741ae..a362a622bc678e11c4e7ed8a059= 01ad18ccf38a9 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -452,8 +452,10 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crt= c *crtc, uint32_t lm_idx; bool bg_alpha_enable =3D false; DECLARE_BITMAP(active_fetch, SSPP_MAX); + DECLARE_BITMAP(active_pipes, SSPP_MAX); =20 memset(active_fetch, 0, sizeof(active_fetch)); + memset(active_pipes, 0, sizeof(active_pipes)); drm_atomic_crtc_for_each_plane(plane, crtc) { state =3D plane->state; if (!state) @@ -471,6 +473,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc= *crtc, bg_alpha_enable =3D true; =20 set_bit(pstate->pipe.sspp->idx, active_fetch); + set_bit(pstate->pipe.sspp->idx, active_pipes); _dpu_crtc_blend_setup_pipe(crtc, plane, mixer, cstate->num_mixers, pstate->stage, @@ -479,6 +482,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc= *crtc, =20 if (pstate->r_pipe.sspp) { set_bit(pstate->r_pipe.sspp->idx, active_fetch); + set_bit(pstate->r_pipe.sspp->idx, active_pipes); _dpu_crtc_blend_setup_pipe(crtc, plane, mixer, cstate->num_mixers, pstate->stage, @@ -501,6 +505,9 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc= *crtc, if (ctl->ops.set_active_fetch_pipes) ctl->ops.set_active_fetch_pipes(ctl, active_fetch); =20 + if (ctl->ops.set_active_pipes) + ctl->ops.set_active_pipes(ctl, active_pipes); + _dpu_crtc_program_lm_output_roi(crtc); } =20 @@ -527,6 +534,8 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc) mixer[i].lm_ctl); if (mixer[i].lm_ctl->ops.set_active_fetch_pipes) mixer[i].lm_ctl->ops.set_active_fetch_pipes(mixer[i].lm_ctl, NULL); + if (mixer[i].lm_ctl->ops.set_active_pipes) + mixer[i].lm_ctl->ops.set_active_pipes(mixer[i].lm_ctl, NULL); } =20 /* initialize stage cfg */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_encoder.c index 090b2aa5a63b4797169b24928908215e2424e6b1..2b2b49fd769bd91634201e8921c= 1830473fc25c7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -2202,6 +2202,9 @@ static void dpu_encoder_helper_reset_mixers(struct dp= u_encoder_phys *phys_enc) =20 if (ctl->ops.set_active_fetch_pipes) ctl->ops.set_active_fetch_pipes(ctl, NULL); + + if (ctl->ops.set_active_pipes) + ctl->ops.set_active_pipes(ctl, NULL); } } =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/m= sm/disp/dpu1/dpu_hw_ctl.c index 43a254cf57da571e2ec8aad38028477652f9283c..3e0bdd1100ebb0d302a852ceeaf= 8af86835e69a1 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -40,6 +40,7 @@ #define CTL_INTF_FLUSH 0x110 #define CTL_CDM_FLUSH 0x114 #define CTL_PERIPH_FLUSH 0x128 +#define CTL_PIPE_ACTIVE 0x12C #define CTL_INTF_MASTER 0x134 #define CTL_DSPP_n_FLUSH(n) ((0x13C) + ((n) * 4)) =20 @@ -653,6 +654,9 @@ static void dpu_hw_ctl_reset_intf_cfg_v1(struct dpu_hw_= ctl *ctx, if (ctx->ops.set_active_fetch_pipes) ctx->ops.set_active_fetch_pipes(ctx, NULL); =20 + if (ctx->ops.set_active_pipes) + ctx->ops.set_active_pipes(ctx, NULL); + if (cfg->intf) { intf_active =3D DPU_REG_READ(c, CTL_INTF_ACTIVE); intf_active &=3D ~BIT(cfg->intf - INTF_0); @@ -695,6 +699,23 @@ static void dpu_hw_ctl_set_active_fetch_pipes(struct d= pu_hw_ctl *ctx, DPU_REG_WRITE(&ctx->hw, CTL_FETCH_PIPE_ACTIVE, val); } =20 +static void dpu_hw_ctl_set_active_pipes(struct dpu_hw_ctl *ctx, + unsigned long *active_pipes) +{ + int i; + u32 val =3D 0; + + if (active_pipes) { + for (i =3D 0; i < SSPP_MAX; i++) { + if (test_bit(i, active_pipes) && + fetch_tbl[i] !=3D CTL_INVALID_BIT) + val |=3D BIT(fetch_tbl[i]); + } + } + + DPU_REG_WRITE(&ctx->hw, CTL_PIPE_ACTIVE, val); +} + /** * dpu_hw_ctl_init() - Initializes the ctl_path hw driver object. * Should be called before accessing any ctl_path register. @@ -757,8 +778,12 @@ struct dpu_hw_ctl *dpu_hw_ctl_init(struct drm_device *= dev, c->ops.trigger_pending =3D dpu_hw_ctl_trigger_pending; c->ops.reset =3D dpu_hw_ctl_reset_control; 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[78.11.220.99]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-abbaa56026fsm865456666b.113.2025.02.21.07.25.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2025 07:25:29 -0800 (PST) From: Krzysztof Kozlowski Date: Fri, 21 Feb 2025 16:24:30 +0100 Subject: [PATCH v3 20/21] drm/msm/dpu: Implement LM crossbar for v12.0 DPU Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250221-b4-sm8750-display-v3-20-3ea95b1630ea@linaro.org> References: <20250221-b4-sm8750-display-v3-0-3ea95b1630ea@linaro.org> In-Reply-To: <20250221-b4-sm8750-display-v3-0-3ea95b1630ea@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , Jonathan Marek , Kuogee Hsieh , Neil Armstrong Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Srini Kandagatla , Rob Clark X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=12732; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=B/jRp+dqZi7gerNizVV7Yg6wm0rCKfZ6jWcmKa1/3M8=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBnuJq+LvzAV/lyIFitzT89Im6WGzTMbAehHu9Pv sCMzTuQyDyJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZ7iavgAKCRDBN2bmhouD 1xBFD/9B1z56etjJgkZ4lvUAcC99W/JKa2WVXFlJZd0B+4RxajH6VhzKNSQSm7E50/I7kfv6H/N nqE4RwdBTTECcBgwge3kAnk7w5dMLl9WX1MF1Hks9kUbJmjZ47oFUCHINcFGQw/6sB/MY7rL/ki jt7nJn+4knVCizMg43Ly4KYwmOsH4Kqbumb3dphnmBrAOWp+MZQIHWfTLunorU5qfjUQTGRCm4M H7KwUAEcA73yFEeWmPu0fYUuUr62Kby6ooMLAg8W8/hqVGzol7P85BBfMqE2HiQ3mrtsd9KCDtm CwBGeInHpDZbZDjTc/65VkHKPEpPGrLe0Y2QOkT0Dk2exNNTMNhO9a/Omyy3LGwPtxZ+DbYjnxo 1DogVeppIgN46nxorfS+6+O+MSM/P9XlOkct09gc38ESTCEvLaZA7qgOsnEAeYybUtJDzZ1tnSn NVxj+rY9q+7fQKKH1gq3MJXwQfrRVsA8VmqRU/pVNG2iTS3/+bVABal8sPcgdnoub13H/Oa22Yd U4A9LZX92UPM6KkooMGA7Yp9an6FYvCHYxZ+ufePAUeh0Tw7JxkElJHHZchPh5T4OADaiz2Hocj w/bIWeDEuHyuQeIYqttZZ1N3tE5JIEifPgKjKPimMPCDLMV0XMGEkvuKsxUMt0qO15knssTaYWl ErrT4awAgITLefg== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B v12.0 DPU on SM8750 comes with new LM crossbar that requires each pipe rectangle to be programmed separately in blend stage. Implement support for this along with a new CTL_LAYER_ACTIVE register and setting the blend stage in layer mixer code. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Dmitry Baryshkov --- Changes in v3: 1. New patch, split from previous big DPU v12.0. --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 18 +++- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 6 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 27 +++++- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 9 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 126 ++++++++++++++++++++++++= ++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h | 18 ++++ 6 files changed, 201 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm= /disp/dpu1/dpu_crtc.c index a362a622bc678e11c4e7ed8a05901ad18ccf38a9..84f10a88acbdec6471ae46d8a91= fcc85e01d9a4f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -523,6 +523,7 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc) struct dpu_hw_ctl *ctl; struct dpu_hw_mixer *lm; struct dpu_hw_stage_cfg stage_cfg; + DECLARE_BITMAP(active_lms, LM_MAX); int i; =20 DRM_DEBUG_ATOMIC("%s\n", dpu_crtc->name); @@ -536,10 +537,14 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *cr= tc) mixer[i].lm_ctl->ops.set_active_fetch_pipes(mixer[i].lm_ctl, NULL); if (mixer[i].lm_ctl->ops.set_active_pipes) mixer[i].lm_ctl->ops.set_active_pipes(mixer[i].lm_ctl, NULL); + + if (mixer[i].hw_lm->ops.clear_all_blendstages) + mixer[i].hw_lm->ops.clear_all_blendstages(mixer[i].hw_lm); } =20 /* initialize stage cfg */ memset(&stage_cfg, 0, sizeof(struct dpu_hw_stage_cfg)); + memset(active_lms, 0, sizeof(active_lms)); =20 _dpu_crtc_blend_setup_mixer(crtc, dpu_crtc, mixer, &stage_cfg); =20 @@ -553,13 +558,22 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *cr= tc) ctl->ops.update_pending_flush_mixer(ctl, mixer[i].hw_lm->idx); =20 + set_bit(lm->idx, active_lms); + if (ctl->ops.set_active_lms) + ctl->ops.set_active_lms(ctl, active_lms); + DRM_DEBUG_ATOMIC("lm %d, op_mode 0x%X, ctl %d\n", mixer[i].hw_lm->idx - LM_0, mixer[i].mixer_op_mode, ctl->idx - CTL_0); =20 - ctl->ops.setup_blendstage(ctl, mixer[i].hw_lm->idx, - &stage_cfg); + if (ctl->ops.setup_blendstage) + ctl->ops.setup_blendstage(ctl, mixer[i].hw_lm->idx, + &stage_cfg); + + if (lm->ops.setup_blendstage) + lm->ops.setup_blendstage(lm, mixer[i].hw_lm->idx, + &stage_cfg); } } =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_encoder.c index 2b2b49fd769bd91634201e8921c1830473fc25c7..b2d4a13222fcab6ffe31cb407f7= 94ef212c23878 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -2200,6 +2200,12 @@ static void dpu_encoder_helper_reset_mixers(struct d= pu_encoder_phys *phys_enc) if (phys_enc->hw_ctl->ops.setup_blendstage) phys_enc->hw_ctl->ops.setup_blendstage(ctl, hw_mixer[i]->idx, NULL); =20 + if (hw_mixer[i]->ops.clear_all_blendstages) + hw_mixer[i]->ops.clear_all_blendstages(hw_mixer[i]); + + if (ctl->ops.set_active_lms) + ctl->ops.set_active_lms(ctl, NULL); + if (ctl->ops.set_active_fetch_pipes) ctl->ops.set_active_fetch_pipes(ctl, NULL); =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/m= sm/disp/dpu1/dpu_hw_ctl.c index 3e0bdd1100ebb0d302a852ceeaf8af86835e69a1..8b6b60f5e6206078f1df98b20f7= 7ed91049e6ef0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -41,6 +41,7 @@ #define CTL_CDM_FLUSH 0x114 #define CTL_PERIPH_FLUSH 0x128 #define CTL_PIPE_ACTIVE 0x12C +#define CTL_LAYER_ACTIVE 0x130 #define CTL_INTF_MASTER 0x134 #define CTL_DSPP_n_FLUSH(n) ((0x13C) + ((n) * 4)) =20 @@ -62,6 +63,8 @@ static const u32 fetch_tbl[SSPP_MAX] =3D {CTL_INVALID_BIT= , 16, 17, 18, 19, CTL_INVALID_BIT, CTL_INVALID_BIT, CTL_INVALID_BIT, CTL_INVALID_BIT, 0, 1, 2, 3, 4, 5}; =20 +static const u32 lm_tbl[LM_MAX] =3D {CTL_INVALID_BIT, 0, 1, 2, 3, 4, 5, 6,= 7}; + static int _mixer_stages(const struct dpu_lm_cfg *mixer, int count, enum dpu_lm lm) { @@ -649,7 +652,11 @@ static void dpu_hw_ctl_reset_intf_cfg_v1(struct dpu_hw= _ctl *ctx, merge3d_active); } =20 - dpu_hw_ctl_clear_all_blendstages(ctx); + if (ctx->ops.clear_all_blendstages) + ctx->ops.clear_all_blendstages(ctx); + + if (ctx->ops.set_active_lms) + ctx->ops.set_active_lms(ctx, NULL); =20 if (ctx->ops.set_active_fetch_pipes) ctx->ops.set_active_fetch_pipes(ctx, NULL); @@ -716,6 +723,23 @@ static void dpu_hw_ctl_set_active_pipes(struct dpu_hw_= ctl *ctx, DPU_REG_WRITE(&ctx->hw, CTL_PIPE_ACTIVE, val); } =20 +static void dpu_hw_ctl_set_active_lms(struct dpu_hw_ctl *ctx, + unsigned long *active_lms) +{ + int i; + u32 val =3D 0; + + if (active_lms) { + for (i =3D LM_0; i < LM_MAX; i++) { + if (test_bit(i, active_lms) && + lm_tbl[i] !=3D CTL_INVALID_BIT) + val |=3D BIT(lm_tbl[i]); + } + } + + DPU_REG_WRITE(&ctx->hw, CTL_LAYER_ACTIVE, val); +} + /** * dpu_hw_ctl_init() - Initializes the ctl_path hw driver object. * Should be called before accessing any ctl_path register. @@ -783,6 +807,7 @@ struct dpu_hw_ctl *dpu_hw_ctl_init(struct drm_device *d= ev, c->ops.setup_blendstage =3D dpu_hw_ctl_setup_blendstage; } else { c->ops.set_active_pipes =3D dpu_hw_ctl_set_active_pipes; + c->ops.set_active_lms =3D dpu_hw_ctl_set_active_lms; } c->ops.update_pending_flush_sspp =3D dpu_hw_ctl_update_pending_flush_sspp; c->ops.update_pending_flush_mixer =3D dpu_hw_ctl_update_pending_flush_mix= er; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h b/drivers/gpu/drm/m= sm/disp/dpu1/dpu_hw_ctl.h index 40c8190a329f331401b9503f047c1e74f970eefe..7175dfecea1057db3fa16fbfd41= 39182a53d1760 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h @@ -253,6 +253,15 @@ struct dpu_hw_ctl_ops { */ void (*set_active_pipes)(struct dpu_hw_ctl *ctx, unsigned long *active_pipes); + + /** + * Set active layer mixers attached to this CTL + * @ctx: ctl path ctx pointer + * @active_lms: bitmap of enum dpu_lm + */ + void (*set_active_lms)(struct dpu_hw_ctl *ctx, + unsigned long *active_lms); + }; =20 /** diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c b/drivers/gpu/drm/ms= m/disp/dpu1/dpu_hw_lm.c index 75bf3521b03c8e243ccfe1fc226aa71f23b296df..c631b4ae8dc13b7b18fab4721a7= b2f2d97da717a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c @@ -28,11 +28,19 @@ #define LM_FG_COLOR_FILL_XY 0x14 =20 /* >=3D v12 DPU */ +#define LM_BG_SRC_SEL_V12 0x14 +#define LM_BG_SRC_SEL_V12_RESET_VALUE 0x0000C0C0 #define LM_BORDER_COLOR_0_V12 0x1C #define LM_BORDER_COLOR_1_V12 0x20 =20 /* >=3D v12 DPU with offset to mixer base + stage base */ +#define LM_BLEND0_FG_SRC_SEL_V12 0x04 #define LM_BLEND0_CONST_ALPHA_V12 0x08 +#define LM_FG_COLOR_FILL_COLOR_0_V12 0x0C +#define LM_FG_COLOR_FILL_COLOR_1_V12 0x10 +#define LM_FG_COLOR_FILL_SIZE_V12 0x14 +#define LM_FG_COLOR_FILL_XY_V12 0x18 + #define LM_BLEND0_FG_ALPHA 0x04 #define LM_BLEND0_BG_ALPHA 0x08 =20 @@ -215,6 +223,122 @@ static void dpu_hw_lm_setup_color3_v12(struct dpu_hw_= mixer *ctx, } } =20 +static int _set_staged_sspp(u32 stage, struct dpu_hw_stage_cfg *stage_cfg, + int pipes_per_stage, u32 *value) +{ + int i; + u32 pipe_type =3D 0, pipe_id =3D 0, rec_id =3D 0; + u32 src_sel[PIPES_PER_STAGE]; + + *value =3D LM_BG_SRC_SEL_V12_RESET_VALUE; + if (!stage_cfg || !pipes_per_stage) + return 0; + + for (i =3D 0; i < pipes_per_stage; i++) { + enum dpu_sspp pipe =3D stage_cfg->stage[stage][i]; + enum dpu_sspp_multirect_index rect_index =3D stage_cfg->multirect_index[= stage][i]; + + src_sel[i] =3D LM_BG_SRC_SEL_V12_RESET_VALUE; + + if (!pipe) + continue; + + /* translate pipe data to SWI pipe_type, pipe_id */ + if (pipe >=3D SSPP_DMA0 && pipe <=3D SSPP_DMA5) { + pipe_type =3D 0; + pipe_id =3D pipe - SSPP_DMA0; + } else if (pipe >=3D SSPP_VIG0 && pipe <=3D SSPP_VIG3) { + pipe_type =3D 1; + pipe_id =3D pipe - SSPP_VIG0; + } else { + DPU_ERROR("invalid rec-%d pipe:%d\n", i, pipe); + return -EINVAL; + } + + /* translate rec data to SWI rec_id */ + if (rect_index =3D=3D DPU_SSPP_RECT_SOLO || rect_index =3D=3D DPU_SSPP_R= ECT_0) { + rec_id =3D 0; + } else if (rect_index =3D=3D DPU_SSPP_RECT_1) { + rec_id =3D 1; + } else { + DPU_ERROR("invalid rec-%d rect_index:%d\n", i, rect_index); + rec_id =3D 0; + } + + /* calculate SWI value for rec-0 and rec-1 and store it temporary buffer= */ + src_sel[i] =3D (((pipe_type & 0x3) << 6) | ((rec_id & 0x3) << 4) | (pipe= _id & 0xf)); + } + + /* calculate final SWI register value for rec-0 and rec-1 */ + *value =3D 0; + for (i =3D 0; i < pipes_per_stage; i++) + *value |=3D src_sel[i] << (i * 8); + + return 0; +} + +static int dpu_hw_lm_setup_blendstage(struct dpu_hw_mixer *ctx, enum dpu_l= m lm, + struct dpu_hw_stage_cfg *stage_cfg) +{ + struct dpu_hw_blk_reg_map *c =3D &ctx->hw; + int i, ret, stages, stage_off, pipes_per_stage; + u32 value; + + stages =3D ctx->cap->sblk->maxblendstages; + if (stages <=3D 0) + return -EINVAL; + + if (ctx->cap->sourcesplit) + pipes_per_stage =3D PIPES_PER_STAGE; + else + pipes_per_stage =3D 1; + + /* + * When stage configuration is empty, we can enable the + * border color by setting the corresponding LAYER_ACTIVE bit + * and un-staging all the pipes from the layer mixer. + */ + if (!stage_cfg) + DPU_REG_WRITE(c, LM_BG_SRC_SEL_V12, LM_BG_SRC_SEL_V12_RESET_VALUE); + + for (i =3D DPU_STAGE_0; i <=3D stages; i++) { + stage_off =3D _stage_offset(ctx, i); + if (stage_off < 0) + return stage_off; + + ret =3D _set_staged_sspp(i, stage_cfg, pipes_per_stage, &value); + if (ret) + return ret; + + DPU_REG_WRITE(c, LM_BLEND0_FG_SRC_SEL_V12 + stage_off, value); + } + + return 0; +} + +static int dpu_hw_lm_clear_all_blendstages(struct dpu_hw_mixer *ctx) +{ + struct dpu_hw_blk_reg_map *c =3D &ctx->hw; + int i, stages, stage_off; + + stages =3D ctx->cap->sblk->maxblendstages; + if (stages <=3D 0) + return -EINVAL; + + DPU_REG_WRITE(c, LM_BG_SRC_SEL_V12, LM_BG_SRC_SEL_V12_RESET_VALUE); + + for (i =3D DPU_STAGE_0; i <=3D stages; i++) { + stage_off =3D _stage_offset(ctx, i); + if (stage_off < 0) + return stage_off; + + DPU_REG_WRITE(c, LM_BLEND0_FG_SRC_SEL_V12 + stage_off, + LM_BG_SRC_SEL_V12_RESET_VALUE); + } + + return 0; +} + /** * dpu_hw_lm_init() - Initializes the mixer hw driver object. * should be called once before accessing every mixer. @@ -257,6 +381,8 @@ struct dpu_hw_mixer *dpu_hw_lm_init(struct drm_device *= dev, c->ops.setup_border_color =3D dpu_hw_lm_setup_border_color; } else { c->ops.setup_alpha_out =3D dpu_hw_lm_setup_color3_v12; + c->ops.setup_blendstage =3D dpu_hw_lm_setup_blendstage; + c->ops.clear_all_blendstages =3D dpu_hw_lm_clear_all_blendstages; c->ops.setup_border_color =3D dpu_hw_lm_setup_border_color_v12; } c->ops.setup_misr =3D dpu_hw_lm_setup_misr; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h b/drivers/gpu/drm/ms= m/disp/dpu1/dpu_hw_lm.h index fff1156add683fec8ce6785e7fe1d769d0de3fe0..1b9ecd082d7fd72b07008787e1c= aea968ed23376 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h @@ -11,6 +11,7 @@ #include "dpu_hw_util.h" =20 struct dpu_hw_mixer; +struct dpu_hw_stage_cfg; =20 struct dpu_hw_mixer_cfg { u32 out_width; @@ -48,6 +49,23 @@ struct dpu_hw_lm_ops { */ void (*setup_alpha_out)(struct dpu_hw_mixer *ctx, uint32_t mixer_op); =20 + /** + * Clear layer mixer to pipe configuration + * @ctx : mixer ctx pointer + * Returns: 0 on success or -error + */ + int (*clear_all_blendstages)(struct dpu_hw_mixer *ctx); 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[78.11.220.99]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-abbaa56026fsm865456666b.113.2025.02.21.07.25.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2025 07:25:30 -0800 (PST) From: Krzysztof Kozlowski Date: Fri, 21 Feb 2025 16:24:31 +0100 Subject: [PATCH v3 21/21] drm/msm/mdss: Add support for SM8750 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250221-b4-sm8750-display-v3-21-3ea95b1630ea@linaro.org> References: <20250221-b4-sm8750-display-v3-0-3ea95b1630ea@linaro.org> In-Reply-To: <20250221-b4-sm8750-display-v3-0-3ea95b1630ea@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , Jonathan Marek , Kuogee Hsieh , Neil Armstrong Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Srini Kandagatla , Rob Clark X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3191; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=npT/AUk70cBHCRbn81WnGX4UoVxSXbDYwaGyJuk3VME=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBnuJq/ctXpMZ8Jnwnml7qBOIiMMaNsLSOfnFQtu E+RAw9e9LeJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZ7iavwAKCRDBN2bmhouD 17mXD/94+XDsJfLydNAyZTQ+/RWjpP+M005+GCV3TKtBNDit1ewBvJdQko5LBfWZJlSMI0nTmKJ z/z7fgHHOeeW58wIwdsjtLf3k3SR7XqaonuobTJHEP+gdpvcUvFRKfBzwpsAjFbtVRiZ9SZM0pB 814FttaFuZO0WF9rYaRk1bdtoAoAeZJ3zli7f53GyQ6mbAye5P0vrhMnVUSpK3C9vp8pSyOQ0Eb 0fkMQxzYCMmSaCaIpffD9XH7GFEGgjhO43h+yHZp+qELOfCDizLV+BzbIixYLvAH5u7D8cl2Woq D6L2M/qrSHWSV6STwB26EPFDr/40lcVL6RDglOv44lNTVwvwnGhh/HUmume8slOYwK4PtlB9Aen U6o3772Tsho6oqXQ5rIUYfYiyiHp0yP39Wrh+G8HMYk78tCSaXuEEGl4XnXuB8HyKDYWdUrnYZA +zE/9srdqNj1bqsup1ouiljIQSyUjh7uGff9MUrh9p+57CVMWHkFTgiFJdmmjlc6y9n+u1OX4dW tj9prAwgFZBlqyPZ76kH/F3pn6Sgr+gSVqB7tvQ6C+iaSaJkHP9+G+nMRp5HQ1aga0WU9nEi5yr 8E0Im/f16dGTMtSNUM1Fm7mT4PwXWLXaZlLJdQYJviLwCP6YkJSi35ZIo2qhJzlNvZsmjxcqQAB Zcg9tFWD5yU7oJw== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Add support for the Qualcomm SM8750 platform. Reviewed-by: Dmitry Baryshkov Signed-off-by: Krzysztof Kozlowski --- drivers/gpu/drm/msm/msm_mdss.c | 33 +++++++++++++++++++++++++++++++++ drivers/gpu/drm/msm/msm_mdss.h | 1 + 2 files changed, 34 insertions(+) diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index dcb49fd30402b80edd2cb5971f95a78eaad6081f..3f00eb6de3a9d2bee7637c6f516= efff78b7d872b 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -222,6 +222,24 @@ static void msm_mdss_setup_ubwc_dec_40(struct msm_mdss= *msm_mdss) } } =20 +static void msm_mdss_setup_ubwc_dec_50(struct msm_mdss *msm_mdss) +{ + const struct msm_mdss_data *data =3D msm_mdss->mdss_data; + u32 value =3D MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle) | + MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit); + + if (data->ubwc_bank_spread) + value |=3D MDSS_UBWC_STATIC_UBWC_BANK_SPREAD; + + if (data->macrotile_mode) + value |=3D MDSS_UBWC_STATIC_MACROTILE_MODE; + + writel_relaxed(value, msm_mdss->mmio + REG_MDSS_UBWC_STATIC); + + writel_relaxed(4, msm_mdss->mmio + REG_MDSS_UBWC_CTRL_2); + writel_relaxed(1, msm_mdss->mmio + REG_MDSS_UBWC_PREDICTION_MODE); +} + #define MDSS_HW_MAJ_MIN \ (MDSS_HW_VERSION_MAJOR__MASK | MDSS_HW_VERSION_MINOR__MASK) =20 @@ -339,6 +357,9 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss) case UBWC_4_3: msm_mdss_setup_ubwc_dec_40(msm_mdss); break; + case UBWC_5_0: + msm_mdss_setup_ubwc_dec_50(msm_mdss); + break; default: dev_err(msm_mdss->dev, "Unsupported UBWC decoder version %x\n", msm_mdss->mdss_data->ubwc_dec_version); @@ -722,6 +743,17 @@ static const struct msm_mdss_data sm8550_data =3D { .reg_bus_bw =3D 57000, }; =20 +static const struct msm_mdss_data sm8750_data =3D { + .ubwc_enc_version =3D UBWC_5_0, + .ubwc_dec_version =3D UBWC_5_0, + .ubwc_swizzle =3D 6, + .ubwc_bank_spread =3D true, + /* TODO: highest_bank_bit =3D 2 for LP_DDR4 */ + .highest_bank_bit =3D 3, + .macrotile_mode =3D true, + .reg_bus_bw =3D 57000, +}; + static const struct msm_mdss_data x1e80100_data =3D { .ubwc_enc_version =3D UBWC_4_0, .ubwc_dec_version =3D UBWC_4_3, @@ -756,6 +788,7 @@ static const struct of_device_id mdss_dt_match[] =3D { { .compatible =3D "qcom,sm8450-mdss", .data =3D &sm8350_data }, { .compatible =3D "qcom,sm8550-mdss", .data =3D &sm8550_data }, { .compatible =3D "qcom,sm8650-mdss", .data =3D &sm8550_data}, + { .compatible =3D "qcom,sm8750-mdss", .data =3D &sm8750_data}, { .compatible =3D "qcom,x1e80100-mdss", .data =3D &x1e80100_data}, {} }; diff --git a/drivers/gpu/drm/msm/msm_mdss.h b/drivers/gpu/drm/msm/msm_mdss.h index 14dc53704314558841ee1fe08d93309fd2233812..dd0160c6ba1a297cea5b87cd8b0= 3895b2aa08213 100644 --- a/drivers/gpu/drm/msm/msm_mdss.h +++ b/drivers/gpu/drm/msm/msm_mdss.h @@ -22,6 +22,7 @@ struct msm_mdss_data { #define UBWC_3_0 0x30000000 #define UBWC_4_0 0x40000000 #define UBWC_4_3 0x40030000 +#define UBWC_5_0 0x50000000 =20 const struct msm_mdss_data *msm_mdss_get_mdss_data(struct device *dev); =20 --=20 2.43.0