From nobody Thu Dec 18 13:14:26 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 7FD6D214212; Thu, 20 Feb 2025 18:04:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740074701; cv=none; b=jpX6aRtNMy6QtDsCkdaF1RHZZyOeAZhvlZXzIWCnatsfMPA8HImbg9tl/zpapEidbPmkjaeJhEgk2YLY89tsE4jORjWlyYNTHGrNwzE0Mi5PeXZQ/PaMM0yicv/Mv9jrWl3Z43dvqAwgx7AM0ha2etZ2XKOFG4DdkrvRJRzuJCs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740074701; c=relaxed/simple; bh=wSGkRHix23Rg/RD0EtFj6NYDI+obYIqaysIit5V1FIw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=uhnvxp3zQ6/8Qq1TNprXGUen5wSkavmq1ZrMOeJ8vCWGw7cmWMp0zFEctubIYF4sPlIFqTrHP8p3vXmTenoOcCqYwCOZoIM8XTRsRZ69SmIMjZL3RaXYxAoaVYnQUKn5n4PuJoxrSxrWvO/++Dp0xAz/NhWxvv2bTevPdldsRVM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E6A9116F3; Thu, 20 Feb 2025 10:05:16 -0800 (PST) Received: from e119884-lin.cambridge.arm.com (e119884-lin.cambridge.arm.com [10.1.196.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id BC3253F59E; Thu, 20 Feb 2025 10:04:56 -0800 (PST) From: Vincenzo Frascino To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Vincenzo Frascino , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Russell King , Will Deacon , Mark Rutland , Jessica Clarke Subject: [PATCH v6 07/10] arm64: dts: morello: Add support for common functionalities Date: Thu, 20 Feb 2025 18:04:25 +0000 Message-ID: <20250220180427.3382482-8-vincenzo.frascino@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250220180427.3382482-1-vincenzo.frascino@arm.com> References: <20250220180427.3382482-1-vincenzo.frascino@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Morello architecture is an experimental extension to Armv8.2-A, which extends the AArch64 state with the principles proposed in version 7 of the Capability Hardware Enhanced RISC Instructions (CHERI) ISA. The Morello Platform (soc) and the Fixed Virtual Platfom (fvp) share some functionalities that have conveniently been included in morello.dtsi to avoid duplication. Introduce morello.dtsi. Note: Morello fvp will be introduced with a future patch series. Signed-off-by: Vincenzo Frascino Reviewed-by: Linus Walleij --- arch/arm64/boot/dts/arm/morello.dtsi | 323 +++++++++++++++++++++++++++ 1 file changed, 323 insertions(+) create mode 100644 arch/arm64/boot/dts/arm/morello.dtsi diff --git a/arch/arm64/boot/dts/arm/morello.dtsi b/arch/arm64/boot/dts/arm= /morello.dtsi new file mode 100644 index 000000000000..e35e5e482720 --- /dev/null +++ b/arch/arm64/boot/dts/arm/morello.dtsi @@ -0,0 +1,323 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (c) 2020-2024, Arm Limited. All rights reserved. + */ + +#include + +/ { + interrupt-parent =3D <&gic>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + + soc_refclk50mhz: clock-50000000 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <50000000>; + clock-output-names =3D "apb_pclk"; + }; + + soc_refclk85mhz: clock-85000000 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <85000000>; + clock-output-names =3D "iofpga:aclk"; + }; + + cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + compatible =3D "arm,rainier"; + reg =3D <0x0 0x0>; + device_type =3D "cpu"; + enable-method =3D "psci"; + /* 4 ways set associative */ + i-cache-size =3D <0x10000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <512>; + d-cache-size =3D <0x10000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_0>; + clocks =3D <&scmi_dvfs 0>; + + l2_0: l2-cache-0 { + compatible =3D "cache"; + cache-level =3D <2>; + /* 8 ways set associative */ + cache-size =3D <0x100000>; + cache-line-size =3D <64>; + cache-sets =3D <2048>; + cache-unified; + next-level-cache =3D <&l3_0>; + + l3_0: l3-cache { + compatible =3D "cache"; + cache-level =3D <3>; + cache-size =3D <0x100000>; + cache-unified; + }; + }; + }; + + cpu1: cpu@100 { + compatible =3D "arm,rainier"; + reg =3D <0x0 0x100>; + device_type =3D "cpu"; + enable-method =3D "psci"; + /* 4 ways set associative */ + i-cache-size =3D <0x10000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <512>; + d-cache-size =3D <0x10000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_1>; + clocks =3D <&scmi_dvfs 0>; + + l2_1: l2-cache-1 { + compatible =3D "cache"; + cache-level =3D <2>; + /* 8 ways set associative */ + cache-size =3D <0x100000>; + cache-line-size =3D <64>; + cache-sets =3D <2048>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu2: cpu@10000 { + compatible =3D "arm,rainier"; + reg =3D <0x0 0x10000>; + device_type =3D "cpu"; + enable-method =3D "psci"; + /* 4 ways set associative */ + i-cache-size =3D <0x10000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <512>; + d-cache-size =3D <0x10000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_2>; + clocks =3D <&scmi_dvfs 1>; + + l2_2: l2-cache-2 { + compatible =3D "cache"; + cache-level =3D <2>; + /* 8 ways set associative */ + cache-size =3D <0x100000>; + cache-line-size =3D <64>; + cache-sets =3D <2048>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu3: cpu@10100 { + compatible =3D "arm,rainier"; + reg =3D <0x0 0x10100>; + device_type =3D "cpu"; + enable-method =3D "psci"; + /* 4 ways set associative */ + i-cache-size =3D <0x10000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <512>; + d-cache-size =3D <0x10000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_3>; + clocks =3D <&scmi_dvfs 1>; + + l2_3: l2-cache-3 { + compatible =3D "cache"; + cache-level =3D <2>; + /* 8 ways set associative */ + cache-size =3D <0x100000>; + cache-line-size =3D <64>; + cache-sets =3D <2048>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + }; + + firmware { + interrupt-parent =3D <&gic>; + + scmi { + compatible =3D "arm,scmi"; + mbox-names =3D "tx", "rx"; + mboxes =3D <&mailbox 1 0>, <&mailbox 1 1>; + shmem =3D <&cpu_scp_hpri0>, <&cpu_scp_hpri1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + scmi_dvfs: protocol@13 { + reg =3D <0x13>; + #clock-cells =3D <1>; + }; + + scmi_clk: protocol@14 { + reg =3D <0x14>; + #clock-cells =3D <1>; + }; + }; + }; + + /* The first bank of memory, memory map is actually provided by UEFI. */ + memory@80000000 { + device_type =3D "memory"; + /* [0x80000000-0xffffffff] */ + reg =3D <0x00000000 0x80000000 0x0 0x7f000000>; + }; + + memory@8080000000 { + device_type =3D "memory"; + /* [0x8080000000-0x83f7ffffff] */ + reg =3D <0x00000080 0x80000000 0x3 0x78000000>; + }; + + pmu { + compatible =3D "arm,rainier-pmu"; + interrupts =3D ; + }; + + psci { + compatible =3D "arm,psci-0.2"; + method =3D "smc"; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + secure-firmware@ff000000 { + reg =3D <0x0 0xff000000 0x0 0x01000000>; + no-map; + }; + }; + + spe-pmu { + compatible =3D "arm,statistical-profiling-extension-v1"; + interrupts =3D ; + }; + + soc: soc { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + interrupt-parent =3D <&gic>; + ranges; + + uart0: serial@2a400000 { + compatible =3D "arm,pl011", "arm,primecell"; + reg =3D <0x0 0x2a400000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&soc_refclk50mhz>, <&soc_refclk50mhz>; + clock-names =3D "uartclk", "apb_pclk"; + + status =3D "disabled"; + }; + + gic: interrupt-controller@2c010000 { + compatible =3D "arm,gic-v3"; + reg =3D <0x0 0x30000000 0x0 0x10000>, /* GICD */ + <0x0 0x300c0000 0x0 0x80000>; /* GICR */ + + interrupts =3D ; + + #interrupt-cells =3D <3>; + interrupt-controller; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + its1: msi-controller@30040000 { + compatible =3D "arm,gic-v3-its"; + reg =3D <0x0 0x30040000 0x0 0x20000>; + + msi-controller; + #msi-cells =3D <1>; + }; + + its2: msi-controller@30060000 { + compatible =3D "arm,gic-v3-its"; + reg =3D <0x0 0x30060000 0x0 0x20000>; + + msi-controller; + #msi-cells =3D <1>; + }; + + its_ccix: msi-controller@30080000 { + compatible =3D "arm,gic-v3-its"; + reg =3D <0x0 0x30080000 0x0 0x20000>; + + msi-controller; + #msi-cells =3D <1>; + }; + + its_pcie: msi-controller@300a0000 { + compatible =3D "arm,gic-v3-its"; + reg =3D <0x0 0x300a0000 0x0 0x20000>; + + msi-controller; + #msi-cells =3D <1>; + }; + }; + + smmu_dp: iommu@2ce00000 { + compatible =3D "arm,smmu-v3"; + reg =3D <0x0 0x2ce00000 0x0 0x40000>; + + interrupts =3D , + , + ; + interrupt-names =3D "eventq", "gerror", "cmdq-sync"; + #iommu-cells =3D <1>; + }; + + mailbox: mhu@45000000 { + compatible =3D "arm,mhu-doorbell", "arm,primecell"; + reg =3D <0x0 0x45000000 0x0 0x1000>; + + interrupts =3D , + ; + #mbox-cells =3D <2>; + clocks =3D <&soc_refclk50mhz>; + clock-names =3D "apb_pclk"; + }; + + sram: sram@45200000 { + compatible =3D "mmio-sram"; + reg =3D <0x0 0x06000000 0x0 0x8000>; + ranges =3D <0 0x0 0x06000000 0x8000>; + + #address-cells =3D <1>; + #size-cells =3D <1>; + + cpu_scp_hpri0: scp-sram@0 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0x80>; + }; + + cpu_scp_hpri1: scp-sram@80 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x80 0x80>; + }; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + }; +}; --=20 2.43.0