From nobody Tue Dec 16 23:47:49 2025 Received: from mail-ej1-f53.google.com (mail-ej1-f53.google.com [209.85.218.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 241CB213248 for ; Thu, 20 Feb 2025 17:42:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740073375; cv=none; b=pIkpK3ShEfNAjysENT+QExLNX/gdOxWmeA+e85lU1/e1PZdYz9elAPKx1tgbvYy/LNxVe7EciszHPx6//UGeE+rvHomaVt1ahgmlRLSEdefw0+FlF9Nh+aL3Ksos6/pCkRtb5XXiCnyFRBlesu+lv53C8KJe1+3Y4X1O2Wffmhg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740073375; c=relaxed/simple; bh=MhEWbQKeL4hp6PAsi3bp/coMyvA+vOUXxLINdXHgeAI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=gAMAZPjZ8ZIxAPFCw+/Vqln+tSLIREqhM0U5QAy/G1G4WowVlRfMi5QUbrrht0bBIUn705or6AhF4WRTvbGMYQ/y4f2hYM1pPyzluqM3GN/ngbjTaNevHtSm349OtT1PLGY9QA6GBEdQ/XXcwK0eSi3FTPByIfVHHoaHCNT9Yf4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=iDoliWli; arc=none smtp.client-ip=209.85.218.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="iDoliWli" Received: by mail-ej1-f53.google.com with SMTP id a640c23a62f3a-abb90f68f8cso235200466b.3 for ; Thu, 20 Feb 2025 09:42:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1740073371; x=1740678171; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=mtFXokZVjvbfuakmYskRnuTAG5EU61PrUinN7HB6kKA=; b=iDoliWliqpB1D9mTN+amgWaC+eI9vwEcpsJXGnu4TTLc24G1llR42buEJrWr9IXZ7l aszAQ4nScA7PgpRK2QG18fTF3moUDGP6m8gnFNbOki/Phm16DiVNPk4/MD6KQW9KNtSk f03/OZMJUab2DZujFNkHqfUBjrPfq+OQ1KiA6Gog4Pm1CoLpWl54dvGwpT52WRJ5booC SyPiX3bKU4D8l1eVM/sx5A6saSybfs/ShfSxquNW4tLEOsty5Yqf6tjUxOSdQTLe8F+w +Pkx6mK8Qv0hWlr0/sC1e26bWoaU+y0kXo5NI3qNP4zAO5+HY4FO1vHgmfj/dIf9TuBX U+lg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740073371; x=1740678171; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mtFXokZVjvbfuakmYskRnuTAG5EU61PrUinN7HB6kKA=; b=xSwSfr3wwO0yvZIpLb1v6Ht+11IOc8atx0JKJuA3nQSOX7DU/NasjA7zglhmK8NHUN c88DWhCIrsUB3ewzbnTjTPe3YPPakO88MSW1jCuBOXCZw8bTPHbV6eTtNWkG+/fXoH+d rIUCSe2qrlZpY/lVSMHAZqvjEgoPkh1nCFE82QmTnxMEWE1YbWP8Nn8q/x1jAHIW9CkI Pk9K18HwF9dLKl6EZQou5CIJVJmDB7aAkx8DmNn9X81nbs+yJgJQk2Zw0VijkVu11QjC W+Asuw0a7wHTU/c13OHNWRBPo15V73QHPYZTYEjEPOnCnU1qad1585dLo4i38aa4qCCD ++hA== X-Forwarded-Encrypted: i=1; AJvYcCWzCLdAB1vO798IwPK0oflAOOwFq9t/dQ+GOyghuqEBbwWc533sQa/igyxnvtBTlNvtcPDiAZEIZA/vjuI=@vger.kernel.org X-Gm-Message-State: AOJu0YzAsPqWX0OnHZVNU2Ubyrg+2tpwc5PJU6BCcXXwzhDWPr4LisWa Lr0D80I/2fW4KKAXX5Qs4PoAMFJ9fdgeqjcfxV+qG+4PG04PjLnZK1vckKIc3sI= X-Gm-Gg: ASbGncvEq7otsw57XGENKtnpaGfQ8WUqb75/4JLy50e6Idfwhbd4Le8ph2guH131nYa BvdOLU7tKJzEOvJap18yASVvesoVjpMjztXU0lw5z7ncAlnR77DpFLx0p41VaItUfbQPHRzCXF2 puwKgTARL8Z2QRbKr7bgAwpS3PMSEc2F+ygNLW5wamVKaevrkGIjbaqaIHM9o6SnrFBkiFUKVC+ nlv9FMzmK4gASBwFv5Y7m8w1R+w9U/LpKNmOIQHIi/qzOe74MQO2sza2+W25vGT7onPWUqiPEjM hR7A86jmGEFuHA== X-Google-Smtp-Source: AGHT+IHOc6pZmP/o+UqAl/Ci/QaculaXeGegJZ+BpMU5iWILTIJklH4fKUpWEJUIlH3/h0D9qMiKeQ== X-Received: by 2002:a17:906:308b:b0:aba:519b:f774 with SMTP id a640c23a62f3a-abc09d31cc7mr20665566b.52.1740073371356; Thu, 20 Feb 2025 09:42:51 -0800 (PST) Received: from [127.0.1.1] ([62.231.96.41]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-abb8190d1b6sm1014496166b.36.2025.02.20.09.42.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Feb 2025 09:42:50 -0800 (PST) From: Abel Vesa Date: Thu, 20 Feb 2025 19:42:30 +0200 Subject: [PATCH RESEND v5 1/4] arm64: dts: qcom: x1e80100-crd: Describe the Parade PS8830 retimers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250220-x1e80100-dts-crd-t14s-enable-typec-retimers-v5-1-380a3e0e7edc@linaro.org> References: <20250220-x1e80100-dts-crd-t14s-enable-typec-retimers-v5-0-380a3e0e7edc@linaro.org> In-Reply-To: <20250220-x1e80100-dts-crd-t14s-enable-typec-retimers-v5-0-380a3e0e7edc@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Johan Hovold , Dmitry Baryshkov , Rajendra Nayak , Sibi Sankar , Christophe JAILLET , Trilok Soni , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa X-Mailer: b4 0.15-dev-dedf8 X-Developer-Signature: v=1; a=openpgp-sha256; l=12392; i=abel.vesa@linaro.org; h=from:subject:message-id; bh=MhEWbQKeL4hp6PAsi3bp/coMyvA+vOUXxLINdXHgeAI=; b=owEBbQKS/ZANAwAKARtfRMkAlRVWAcsmYgBnt2mORlMnb4EDNPBmpnwYoBhwBKWouBNIFzown zci/uNVbfmJAjMEAAEKAB0WIQRO8+4RTnqPKsqn0bgbX0TJAJUVVgUCZ7dpjgAKCRAbX0TJAJUV VgNQEACXvzaDn+aT7RfxSA8sl/yA5sr4K5PQ2xFwD7zRyLPKWGbRiVA8stltI3A4QLSKqKO9N/o PonHs4hxsvBXYCeDWh+tv05mbxFVQabM2Lx32AI1mIIB/bHAjzkD68A41mpLUAPMZJnW3/+7WjV 2GlomEmJfVPKa2JNpscj0YeAwX+/dknQo6EycFyYzZBuT+RiKMBT7r9H9y680MhAHw3vphHqpjv V95/vcoQ1QRgqvlVHziyw6A2cf81WEBGKFzLSn74dqI43ozBczxq2w6F8cbiKc1Cv3wupOp7yVc zbxkvn147n5rBA5d7kAAsKyDiXEifnRK8wFGNYgiKqBCdVJIWso1i4Q95uVdFwV3Igj+BV7OaWc 5wV/9hiWRfC0C4hAiyKe18gFS+1BS6c08s+7dQ41qaaE2DkM+vBLlotUyiV85OQnJKn42Db7q5K sylPPC0AZHcel087e1v1Di2AEouMBU19ZwgW1/Yq4bWpPluh4aEoHMtYVjxxN/Tx0MQQiyko+9C n5bUbFg6vzmc1+aiiqkBSNofdRqwnaP2HXXrjlmkc0zPlzl3UgUKUa2W8Zpyyb1PWxqmfyDGRh9 dmpx6yPdMPog+XjllNtIeILA71WyocQb0pExSEkjo9S+VpSeWJ5LjTAZAKbK+a3VnPi2OeOZ5a5 6Sl7ehraOvqc5XA== X-Developer-Key: i=abel.vesa@linaro.org; a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE The X Elite CRD board comes with 3 Parade PS8830 retimers, one for each Type-C port. These handle the orientation and altmode switching and are controlled over I2C. In the connection chain, they sit between the USB/DisplayPort combo PHY and the Type-C connector. Describe the retimers and all gpio controlled voltage regulators used by each retimer. Also, modify the pmic glink graph to include the retimers in between the SuperSpeed/Sideband in endpoints and the QMP PHY out endpoints. Signed-off-by: Abel Vesa Reviewed-by: Johan Hovold Tested-by: Johan Hovold --- arch/arm64/boot/dts/qcom/x1e80100-crd.dts | 450 ++++++++++++++++++++++++++= +++- 1 file changed, 444 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts b/arch/arm64/boot/dt= s/qcom/x1e80100-crd.dts index ff5b3472fafd35a2a3754c11ab0b9b9e8ea5a4b4..1b29082788a366c63474b74e7dc= 916176a57546d 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts @@ -100,7 +100,15 @@ port@1 { reg =3D <1>; =20 pmic_glink_ss0_ss_in: endpoint { - remote-endpoint =3D <&usb_1_ss0_qmpphy_out>; + remote-endpoint =3D <&retimer_ss0_ss_out>; + }; + }; + + port@2 { + reg =3D <2>; + + pmic_glink_ss0_con_sbu_in: endpoint { + remote-endpoint =3D <&retimer_ss0_con_sbu_out>; }; }; }; @@ -129,7 +137,15 @@ port@1 { reg =3D <1>; =20 pmic_glink_ss1_ss_in: endpoint { - remote-endpoint =3D <&usb_1_ss1_qmpphy_out>; + remote-endpoint =3D <&retimer_ss1_ss_out>; + }; + }; + + port@2 { + reg =3D <2>; + + pmic_glink_ss1_con_sbu_in: endpoint { + remote-endpoint =3D <&retimer_ss1_con_sbu_out>; }; }; }; @@ -158,7 +174,15 @@ port@1 { reg =3D <1>; =20 pmic_glink_ss2_ss_in: endpoint { - remote-endpoint =3D <&usb_1_ss2_qmpphy_out>; + remote-endpoint =3D <&retimer_ss2_ss_out>; + }; + }; + + port@2 { + reg =3D <2>; + + pmic_glink_ss2_con_sbu_in: endpoint { + remote-endpoint =3D <&retimer_ss2_con_sbu_out>; }; }; }; @@ -311,6 +335,150 @@ vreg_nvme: regulator-nvme { regulator-boot-on; }; =20 + vreg_rtmr0_1p15: regulator-rtmr0-1p15 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_RTMR0_1P15"; + regulator-min-microvolt =3D <1150000>; + regulator-max-microvolt =3D <1150000>; + + gpio =3D <&pmc8380_5_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&usb0_pwr_1p15_reg_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_1p8: regulator-rtmr0-1p8 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_RTMR0_1P8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + gpio =3D <&pm8550ve_9_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&usb0_1p8_reg_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_3p3: regulator-rtmr0-3p3 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_RTMR0_3P3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + gpio =3D <&pm8550_gpios 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&usb0_3p3_reg_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_1p15: regulator-rtmr1-1p15 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_RTMR1_1P15"; + regulator-min-microvolt =3D <1150000>; + regulator-max-microvolt =3D <1150000>; + + gpio =3D <&tlmm 188 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&usb1_pwr_1p15_reg_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_1p8: regulator-rtmr1-1p8 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_RTMR1_1P8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + gpio =3D <&tlmm 175 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&usb1_pwr_1p8_reg_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_3p3: regulator-rtmr1-3p3 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_RTMR1_3P3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + gpio =3D <&tlmm 186 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&usb1_pwr_3p3_reg_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; + + vreg_rtmr2_1p15: regulator-rtmr2-1p15 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_RTMR2_1P15"; + regulator-min-microvolt =3D <1150000>; + regulator-max-microvolt =3D <1150000>; + + gpio =3D <&tlmm 189 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&usb2_pwr_1p15_reg_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; + + vreg_rtmr2_1p8: regulator-rtmr2-1p8 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_RTMR2_1P8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + gpio =3D <&tlmm 126 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&usb2_pwr_1p8_reg_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; + + vreg_rtmr2_3p3: regulator-rtmr2-3p3 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_RTMR2_3P3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + gpio =3D <&tlmm 187 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&usb2_pwr_3p3_reg_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; + vph_pwr: regulator-vph-pwr { compatible =3D "regulator-fixed"; =20 @@ -735,6 +903,178 @@ keyboard@3a { }; }; =20 +&i2c1 { + clock-frequency =3D <400000>; + + status =3D "okay"; + + typec-mux@8 { + compatible =3D "parade,ps8830"; + reg =3D <0x08>; + + clocks =3D <&rpmhcc RPMH_RF_CLK5>; + + vdd-supply =3D <&vreg_rtmr2_1p15>; + vdd33-supply =3D <&vreg_rtmr2_3p3>; + vdd33-cap-supply =3D <&vreg_rtmr2_3p3>; + vddar-supply =3D <&vreg_rtmr2_1p15>; + vddat-supply =3D <&vreg_rtmr2_1p15>; + vddio-supply =3D <&vreg_rtmr2_1p8>; + + reset-gpios =3D <&tlmm 185 GPIO_ACTIVE_LOW>; + + pinctrl-0 =3D <&rtmr2_default>; + pinctrl-names =3D "default"; + + orientation-switch; + retimer-switch; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + retimer_ss2_ss_out: endpoint { + remote-endpoint =3D <&pmic_glink_ss2_ss_in>; + }; + }; + + port@1 { + reg =3D <1>; + + retimer_ss2_ss_in: endpoint { + remote-endpoint =3D <&usb_1_ss2_qmpphy_out>; + }; + }; + + port@2 { + reg =3D <2>; + + retimer_ss2_con_sbu_out: endpoint { + remote-endpoint =3D <&pmic_glink_ss2_con_sbu_in>; + }; + }; + }; + }; +}; + +&i2c3 { + clock-frequency =3D <400000>; + + status =3D "okay"; + + typec-mux@8 { + compatible =3D "parade,ps8830"; + reg =3D <0x08>; + + clocks =3D <&rpmhcc RPMH_RF_CLK3>; + + vdd-supply =3D <&vreg_rtmr0_1p15>; + vdd33-supply =3D <&vreg_rtmr0_3p3>; + vdd33-cap-supply =3D <&vreg_rtmr0_3p3>; + vddar-supply =3D <&vreg_rtmr0_1p15>; + vddat-supply =3D <&vreg_rtmr0_1p15>; + vddio-supply =3D <&vreg_rtmr0_1p8>; + + reset-gpios =3D <&pm8550_gpios 10 GPIO_ACTIVE_LOW>; + + pinctrl-0 =3D <&rtmr0_default>; + pinctrl-names =3D "default"; + + retimer-switch; + orientation-switch; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + retimer_ss0_ss_out: endpoint { + remote-endpoint =3D <&pmic_glink_ss0_ss_in>; + }; + }; + + port@1 { + reg =3D <1>; + + retimer_ss0_ss_in: endpoint { + remote-endpoint =3D <&usb_1_ss0_qmpphy_out>; + }; + }; + + port@2 { + reg =3D <2>; + + retimer_ss0_con_sbu_out: endpoint { + remote-endpoint =3D <&pmic_glink_ss0_con_sbu_in>; + }; + }; + }; + }; +}; + +&i2c7 { + clock-frequency =3D <400000>; + + status =3D "okay"; + + typec-mux@8 { + compatible =3D "parade,ps8830"; + reg =3D <0x8>; + + clocks =3D <&rpmhcc RPMH_RF_CLK4>; + + vdd-supply =3D <&vreg_rtmr1_1p15>; + vdd33-supply =3D <&vreg_rtmr1_3p3>; + vdd33-cap-supply =3D <&vreg_rtmr1_3p3>; + vddar-supply =3D <&vreg_rtmr1_1p15>; + vddat-supply =3D <&vreg_rtmr1_1p15>; + vddio-supply =3D <&vreg_rtmr1_1p8>; + + reset-gpios =3D <&tlmm 176 GPIO_ACTIVE_LOW>; + + pinctrl-0 =3D <&rtmr1_default>; + pinctrl-names =3D "default"; + + retimer-switch; + orientation-switch; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + retimer_ss1_ss_out: endpoint { + remote-endpoint =3D <&pmic_glink_ss1_ss_in>; + }; + }; + + port@1 { + reg =3D <1>; + + retimer_ss1_ss_in: endpoint { + remote-endpoint =3D <&usb_1_ss1_qmpphy_out>; + }; + }; + + port@2 { + reg =3D <2>; + + retimer_ss1_con_sbu_out: endpoint { + remote-endpoint =3D <&pmic_glink_ss1_con_sbu_in>; + }; + }; + + }; + }; +}; + &i2c8 { clock-frequency =3D <400000>; =20 @@ -883,6 +1223,26 @@ &pcie6a_phy { status =3D "okay"; }; =20 +&pm8550_gpios { + rtmr0_default: rtmr0-reset-n-active-state { + pins =3D "gpio10"; + function =3D "normal"; + power-source =3D <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; + + usb0_3p3_reg_en: usb0-3p3-reg-en-state { + pins =3D "gpio11"; + function =3D "normal"; + power-source =3D <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; +}; + &pm8550ve_8_gpios { misc_3p3_reg_en: misc-3p3-reg-en-state { pins =3D "gpio6"; @@ -896,6 +1256,17 @@ misc_3p3_reg_en: misc-3p3-reg-en-state { }; }; =20 +&pm8550ve_9_gpios { + usb0_1p8_reg_en: usb0-1p8-reg-en-state { + pins =3D "gpio8"; + function =3D "normal"; + power-source =3D <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; +}; + &pmc8380_3_gpios { edp_bl_en: edp-bl-en-state { pins =3D "gpio4"; @@ -906,6 +1277,17 @@ edp_bl_en: edp-bl-en-state { }; }; =20 +&pmc8380_5_gpios { + usb0_pwr_1p15_reg_en: usb0-pwr-1p15-reg-en-state { + pins =3D "gpio8"; + function =3D "normal"; + power-source =3D <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; +}; + &qupv3_0 { status =3D "okay"; }; @@ -1143,6 +1525,20 @@ wake-n-pins { }; }; =20 + rtmr1_default: rtmr1-reset-n-active-state { + pins =3D "gpio176"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + rtmr2_default: rtmr2-reset-n-active-state { + pins =3D "gpio185"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + tpad_default: tpad-default-state { pins =3D "gpio3"; function =3D "gpio"; @@ -1164,6 +1560,48 @@ reset-n-pins { }; }; =20 + usb1_pwr_1p15_reg_en: usb1-pwr-1p15-reg-en-state { + pins =3D "gpio188"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + usb1_pwr_1p8_reg_en: usb1-pwr-1p8-reg-en-state { + pins =3D "gpio175"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + usb1_pwr_3p3_reg_en: usb1-pwr-3p3-reg-en-state { + pins =3D "gpio186"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + usb2_pwr_1p15_reg_en: usb2-pwr-1p15-reg-en-state { + pins =3D "gpio189"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + usb2_pwr_1p8_reg_en: usb2-pwr-1p8-reg-en-state { + pins =3D "gpio126"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + usb2_pwr_3p3_reg_en: usb2-pwr-3p3-reg-en-state { + pins =3D "gpio187"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + wcd_default: wcd-reset-n-active-state { pins =3D "gpio191"; function =3D "gpio"; @@ -1214,7 +1652,7 @@ &usb_1_ss0_dwc3_hs { }; =20 &usb_1_ss0_qmpphy_out { - remote-endpoint =3D <&pmic_glink_ss0_ss_in>; + remote-endpoint =3D <&retimer_ss0_ss_in>; }; =20 &usb_1_ss1_hsphy { @@ -1246,7 +1684,7 @@ &usb_1_ss1_dwc3_hs { }; =20 &usb_1_ss1_qmpphy_out { - remote-endpoint =3D <&pmic_glink_ss1_ss_in>; + remote-endpoint =3D <&retimer_ss1_ss_in>; }; =20 &usb_1_ss2_hsphy { @@ -1278,5 +1716,5 @@ &usb_1_ss2_dwc3_hs { }; =20 &usb_1_ss2_qmpphy_out { - remote-endpoint =3D <&pmic_glink_ss2_ss_in>; + remote-endpoint =3D <&retimer_ss2_ss_in>; }; --=20 2.34.1 From nobody Tue Dec 16 23:47:49 2025 Received: from mail-ej1-f45.google.com (mail-ej1-f45.google.com [209.85.218.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 947DC21323F for ; Thu, 20 Feb 2025 17:42:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740073376; cv=none; b=iBcmO1V9EqUTrbl4jCUWhsXq4+QxihqG7ut8fTrg7PchrZEQtwzdRX7+t/ksHyDObl9rz/thS4eM5jIXxNVxbgOxi6fEVq5Ff1088JRHAAh5qK/Ri1UpXxtDzsJ8l/30qYxe4Zsaf2n7x15EUjBKewBGXQs3zEgoNj7TcDBihFE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740073376; c=relaxed/simple; bh=gVJH9Gtcl03xa1Qz66YDMAwNgxABAgavGDD5XlqUJoc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=BF21IfUMlNhkTfJi4vWbXeDhm0vUFLPtwn4a+WID+oEupoWwt3M6vkR0ac3Y4mvhhDAp6Scm6m/edJQdXl2ZGfyMHjuA9QIMF8a5KwR/a1bXJqiG+O0r9KqvC5C6G0O9p7I3JgjXGCDlSwlCNXQnJ06e+SkOP6JcHiCT3dTP5FU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=dd6dWjLd; arc=none smtp.client-ip=209.85.218.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="dd6dWjLd" Received: by mail-ej1-f45.google.com with SMTP id a640c23a62f3a-ab7483b9bf7so198347566b.3 for ; Thu, 20 Feb 2025 09:42:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1740073373; x=1740678173; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=FFct8uQIitChE7GTd5g7k6V18TU1ChsY3SUn47qNwJk=; b=dd6dWjLdZRAUhP4ag4z4fIGfM3jWqgWtjVT5dbzVMqwijyEU8oQ4gS4ScUCJFINZxe pXe/N2MxTO3y8UM1eDoPVoFCiMPFPcWqG7XvzMMcYxpPbsngCUoUq/MGJzRIm78+Z0Lw 6UEr4Zy4CgmUc/i4v7GPGoYV8QYWjbvc258EOaJ7H3tUpjpGLJYQggNo8u+NLSYr48bw k8Z2jJC5xBByTFNfmqUWT34RMQCc8hE6tXvPrmgMaovy0zk5+IWq3A5JPUJOjgdEynee AOb11sKzI41I44p5RxcQJYQ+Fdrnrlzbd952gV3yxR9pqBYUiHu8g7yNoH9eBQthX67D JCcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740073373; x=1740678173; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FFct8uQIitChE7GTd5g7k6V18TU1ChsY3SUn47qNwJk=; b=i9CwaJpGsrMdRJZw/VPel2zsZs0Kr5hI2fcs3boUerlo3UJZxvSRVrcP72Ob7E7MQH 75r0b6sJgMZP8GCMV3EnrD4nxfzJefGECm1VUY2LRAQAFbfkIxJ5t2nBAykjyC3nShuc qLMNaas4uNP+c6/r1Zx5HE5D1eFrCxiMkrNV61d15AUTztC8iI397tlJ5YbSw+KDUyzZ Q7FxTLJAD/yeUS43yZNt7HRYrUuSDkJ2NxFQjkcxNlTq0fiqHTOiK+ZJZ2YvLVti3jyI TqogIxOVxIHC/uduxgFsAchoDheOjKkbGM4yakDTPJtB1h6L8YMhMAGmkvXG+zkKFfxZ GjOQ== X-Forwarded-Encrypted: i=1; AJvYcCWn7kT3C1HGF4l1xRRljmcDGH55MJPLFrEq+4z9EsOAP2N6fMuvY5+GDwUsWOWCI67lrOkBegkanlMkKlw=@vger.kernel.org X-Gm-Message-State: AOJu0YwKTu9l1Kb65Eys2HbcvHu9V7YkjhomgGhCvqGDJTr+jb0842ip jXUXws6t+m9jDv0A7ncHpNca2roxNAL35Us74RXZuvz2+DTLQbOJViZiwCc2Km8= X-Gm-Gg: ASbGncsCmzmVjchqkYeMlEHP9L2Ik5cS3ZrOqScmYcPzYWoeDQ7pPgmL/pf0sdPNlDi nbCIrcUpKjkPXOCNBhLvoEERUrO3fOvPmFXhcBTMJJhcUeJo8mbXUA4KfXqWEdUPW8m8cjnxq1X jyt8cVjciWW979CqZ0HbZj0jOCuQacLPlI2bOEN/wOAB000I7CMjiwjtYfaDdmyK/vp/hHWa+V+ Znv9LrfH+QDGdWblkO0yMLIXKNU11V01KYYt4aAh/dkdfjZR730BAqzx6hYefI1uSmkyF2Du3Vz SD6FaNt8jIPeKQ== X-Google-Smtp-Source: AGHT+IHoChXESAm3tHDmhie5FqCPsgIwPTlgGc289J1TFc1ErRRThHBbDjyQRb7arj3Byi6qzDjzag== X-Received: by 2002:a17:907:6ea5:b0:abb:e6e1:22c1 with SMTP id a640c23a62f3a-abc09bf55bfmr27929866b.35.1740073372836; Thu, 20 Feb 2025 09:42:52 -0800 (PST) Received: from [127.0.1.1] ([62.231.96.41]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-abb8190d1b6sm1014496166b.36.2025.02.20.09.42.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Feb 2025 09:42:52 -0800 (PST) From: Abel Vesa Date: Thu, 20 Feb 2025 19:42:31 +0200 Subject: [PATCH RESEND v5 2/4] arm64: dts: qcom: x1e80100-crd: Enable external DisplayPort support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250220-x1e80100-dts-crd-t14s-enable-typec-retimers-v5-2-380a3e0e7edc@linaro.org> References: <20250220-x1e80100-dts-crd-t14s-enable-typec-retimers-v5-0-380a3e0e7edc@linaro.org> In-Reply-To: <20250220-x1e80100-dts-crd-t14s-enable-typec-retimers-v5-0-380a3e0e7edc@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Johan Hovold , Dmitry Baryshkov , Rajendra Nayak , Sibi Sankar , Christophe JAILLET , Trilok Soni , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa X-Mailer: b4 0.15-dev-dedf8 X-Developer-Signature: v=1; a=openpgp-sha256; l=1260; i=abel.vesa@linaro.org; h=from:subject:message-id; bh=gVJH9Gtcl03xa1Qz66YDMAwNgxABAgavGDD5XlqUJoc=; b=owEBbQKS/ZANAwAKARtfRMkAlRVWAcsmYgBnt2mRQlgK0Nwdy1hpVYUCtz4zecXroyxVXe3e9 mvJBNH4dZiJAjMEAAEKAB0WIQRO8+4RTnqPKsqn0bgbX0TJAJUVVgUCZ7dpkQAKCRAbX0TJAJUV Vv5fD/4gz3+kQ8opOvrXNlEchSEGhjzpFIQtvOe4K/aLiLhaMn4rxcC4wp+ZLzS0JC8ArrcLYai b/j74yFlKow5jPkrXDzVwj7cNz1CGr1AVycy2iuYk8oiHtu+dBk2cvuojQ6hJ9fd1hS0nfuO+jY OxpJlDAa84G2NJJlBa5H5Uivlq6SOnT4pesOltomxU20wFV/CP1sA8kUJhKfWhun3V9uhHO9orj kp6di3cfVat09qkL19wnj+oaE0uyzyFf7AdcZeegITWCvunbcQrQbWUx/iw/7xm4zT+WZkqIddp ot51PiT+zJWJQqbCULnFVRlzv0OAttUTf1NFMjQFovQ3C4IUhKfFB/4TQJEcx7cO3izi5UER+QO 3TQcl1N0dj87yb4t+uAAxIUk+81tBkKrKCgpeN5+gx8jMYUJ+8IYK6PgXe01aJf+ti/cesLYvkr aHtyP4Wmb+iKoE6BMSU9dJzPszHhLOB4DLHRmygn3MU0UvrH/frfwbJ5mLNbswDfjwHRsXp0Q8E 030xXI8JySkvOr5uOHCXsSDnbowl4GaXsosCaUcfjNmme2MJpRwHvXbFu/OLGsLU8h/cJ8Z7dwm DnyqKrvyPBvrrqyDSbzLGlhlPHcloaHQEwFrwNX8MzvlheVpFzNlB154LzvA/ys0Gr3yk8Cz+sE mzPAgxjOOfY8dgg== X-Developer-Key: i=abel.vesa@linaro.org; a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE The X Elite CRD provides external DisplayPort on all 3 USB Type-C ports. Each one of this ports is connected to a dedicated DisplayPort controller. Due to support missing in the USB/DisplayPort combo PHY driver, the external DisplayPort is limited to 2 lanes. So enable all 3 remaining DisplayPort controllers and limit their data lanes number to 2. Signed-off-by: Abel Vesa Reviewed-by: Johan Hovold Reviewed-by: Konrad Dybcio Tested-by: Johan Hovold --- arch/arm64/boot/dts/qcom/x1e80100-crd.dts | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts b/arch/arm64/boot/dt= s/qcom/x1e80100-crd.dts index 1b29082788a366c63474b74e7dc916176a57546d..9f9b1197963e2a278f66d5dde56= 3930ebcc3d9d9 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts @@ -1125,6 +1125,30 @@ &mdss { status =3D "okay"; }; =20 +&mdss_dp0 { + status =3D "okay"; +}; + +&mdss_dp0_out { + data-lanes =3D <0 1>; +}; + +&mdss_dp1 { + status =3D "okay"; +}; + +&mdss_dp1_out { + data-lanes =3D <0 1>; +}; + +&mdss_dp2 { + status =3D "okay"; +}; + +&mdss_dp2_out { + data-lanes =3D <0 1>; +}; + &mdss_dp3 { compatible =3D "qcom,x1e80100-dp"; /delete-property/ #sound-dai-cells; --=20 2.34.1 From nobody Tue Dec 16 23:47:49 2025 Received: from mail-ej1-f47.google.com (mail-ej1-f47.google.com [209.85.218.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F209C2139D7 for ; Thu, 20 Feb 2025 17:42:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740073378; cv=none; b=TCw0v3EVqjzU0V+l4qQfqh9X7jiXYcuXn/mMOJCrArHljNITGi2rrl8K1SDrKaOsoDXDYlRjp0ZXSt3h6eUSoZjwOVuO+0lcYjRfguRxkd6mI+ge1PTiN7tFCssfmCM+cPvWCPUsDjQjaKeOnr+RjZF18Pg8HRfc9yzUKT1VZQE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740073378; c=relaxed/simple; bh=H6psuYr/khWLTtcO49R4DEtibu326KaUeLgMAhahr0A=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=REKV1baBusgI8WJ0lUXADILLeCPEkMKosyCpU0GP+aqHFv+VQ8S4sFB2kMwfxZm2mEovl6GN2gcAcWowCFnvUaeNyonZbuxiV1aS3Cj8gRAvVZaPstan/aMMT9hVKVipeJ4vt4o0silhW6jr9fjUApTSZSahzTQGzUVX2cVm7/Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=fIDZGBsK; arc=none smtp.client-ip=209.85.218.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="fIDZGBsK" Received: by mail-ej1-f47.google.com with SMTP id a640c23a62f3a-abb8d63b447so165254266b.0 for ; Thu, 20 Feb 2025 09:42:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1740073374; x=1740678174; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=xGkguD4WjPU3rvNjbgPApv3RRpOLC/FxxKjgFnpvQLg=; b=fIDZGBsKiOjsE3tzh1aUaqpDsgsI8dXDueej5/kFkND2Ktp2b/V7AZNdkf7nDBz1Ck Xx+4zWLsB645dC3qP5j1Fwn2preAWcdf2qUW+n+J/vjno8xV6RfXEgWmwWdr1PaP30nE gIyfuuouDEiKrUWSDxxyJcSvCrJcF91hByOgreUCaT13WlgMFa3eeqq8S8MvKeXzT9Z9 Xbq+OM/mTczI2EMGrkrF+85nwsGL2+Or3iVdomBnYvXgl+dBrrEKQX3YMUH08jnXXUJt xnNBt9RM19KBj3B7a8n0JarfbLmps2lYP1DTuXiio+thXLBux9PSHB/O1TkZRzxV3elj m3zw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740073374; x=1740678174; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xGkguD4WjPU3rvNjbgPApv3RRpOLC/FxxKjgFnpvQLg=; b=PHkAsjpwu3spX0KBHcTzLhgwVKoLRW53X6Tkqgsh7/sIDOid5YomUpf6DMP+6ty+O2 bJhkThJZzzk/WzHM546lmSj6m2pqSCyn7Jzdvxc80xV/iOFH98+12wzKkzD1j1ppNGTU rOGoQc+rv4U0lRazqbKIE25EgHrASJiHSnckuCXDxUb+TYJsZi2vh/kufYEQjSYMAM7F LQdACpRIGyqneBkaFKNGB4gRJwfcNHByIYp/96XiXeih3twLFvZ3y/332qsBbNvqmNBX ggfXRVxVcVIkxgfOCZgwT1fZ1/XP+8/iK8oq0Circr6yPqDbYSIk4yAWLhnaHyhx+EA8 XPSg== X-Forwarded-Encrypted: i=1; AJvYcCU5hYFdi5z6/L6LK/RQWJedzCCvKDe1foH9BiCnOvWHxu6joMzN5i1ZInu4RWG24ZAxUq6lPFtXZV8QxTw=@vger.kernel.org X-Gm-Message-State: AOJu0Yx6tVKXaYJrAMnt57Du93pp2rU0nsMeFqB5qC63u85eHyChdaeJ wP1hDNSoEDHtmNZxivKOoYczB9XoF92SVYsyHhfZs8B8zPDpeoaYOFp06MsEM6A= X-Gm-Gg: ASbGncth3DRdq+7K4epotxCKY7x48vLDLRS5i3SNZGEsnCVYR9EaHatRB/3xZhm6ZM+ yzzQW0VU4723dGqIbVasa03XgIyVWWKfKoPk8Rw2pczb3r09QfRj4jB0HACaT1ao4W2hsOcUzFj 5I8yh0Y9p7Y3DMBtIAdOZGCPDvFDyoil1P+7d656Gt3i5fadsM/y4rv5Pi3cf0mwhoXlnsAw7fo j9CE/aXBRyALMKK47bH7W7DIWq8oKPSag5cKfucOYLF0QPdGzBcOBm030GBahXMlovbXACpnadu r0k0nwwuHazlNg== X-Google-Smtp-Source: AGHT+IEgAxZAVDKHz/YfBt4uHMzb8WwFtmIz0Uj9r/1bwdKE3HUZYFKVQsR2cf2enQNRmr8aG/dxXA== X-Received: by 2002:a17:907:948c:b0:ab7:e3cb:ca81 with SMTP id a640c23a62f3a-abc09aac8cbmr26786466b.30.1740073374332; Thu, 20 Feb 2025 09:42:54 -0800 (PST) Received: from [127.0.1.1] ([62.231.96.41]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-abb8190d1b6sm1014496166b.36.2025.02.20.09.42.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Feb 2025 09:42:53 -0800 (PST) From: Abel Vesa Date: Thu, 20 Feb 2025 19:42:32 +0200 Subject: [PATCH RESEND v5 3/4] arm64: dts: qcom: x1e80100-t14s: Describe the Parade PS8830 retimers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250220-x1e80100-dts-crd-t14s-enable-typec-retimers-v5-3-380a3e0e7edc@linaro.org> References: <20250220-x1e80100-dts-crd-t14s-enable-typec-retimers-v5-0-380a3e0e7edc@linaro.org> In-Reply-To: <20250220-x1e80100-dts-crd-t14s-enable-typec-retimers-v5-0-380a3e0e7edc@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Johan Hovold , Dmitry Baryshkov , Rajendra Nayak , Sibi Sankar , Christophe JAILLET , Trilok Soni , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa X-Mailer: b4 0.15-dev-dedf8 X-Developer-Signature: v=1; a=openpgp-sha256; l=8894; i=abel.vesa@linaro.org; h=from:subject:message-id; bh=H6psuYr/khWLTtcO49R4DEtibu326KaUeLgMAhahr0A=; b=owEBbQKS/ZANAwAKARtfRMkAlRVWAcsmYgBnt2mTKvIUixxOjaSyo4NIKICyJbUzQKFrujNVL HUjQCjQdNyJAjMEAAEKAB0WIQRO8+4RTnqPKsqn0bgbX0TJAJUVVgUCZ7dpkwAKCRAbX0TJAJUV VqSDEADFJqTjvzeBfjpQFsMBcWQ/Wg56QhpXtC85QtVaUucIeYkNvsDgp+yvxloKha4NKA5W5O4 campUh/TXG3etMg38sJ9xXaYBOkcnLtHmAfxp43uCP9FgsDTWFhUJ5oKcgv4Qkt8etu43Aaet6k 2v4VrOAUmPr1qemGqh6Mm1YZd4P80HOKcYnsdcmbjYkQjGlV5zfs64SZRuPy/74P1Fhk+vpPZ3o 2JUfh6yIumT8vnZH73Q6GH+QAWSGvI0vZIL4jhTvzRyDD1e9Nymz+dPTH0qUuiJ7KYDLtwvhhts L+aPjrN+njN6YKh3hpOAlTrTU382XyWNrxkGQg+byYvPn0Vftb9UrZ12rAqMo961S9uBlnrXUf+ b/oIduo7aMwCpKyetqe8lleeMuJwoCbuBxnKPVYVJ7rI14CNi1Ez4J3A/JE+S3UFBt2g9Px5hwd zXT+SvC5N3zYnUdskTISAM1JS2rc/Iw87j+mtuHFtioMCfBEX3g4jwZOH0dBuOkvvNOSNbvdoK2 Uf/jP4npogqfPx0mRQu5ICBiUYysuf/x6CEaUYAqb35/asmLLLYhp5AnXVJ7Kytm8JdZEzzcPGo B7DEijxw0r1KKOsGRFNrJGzzCnLPJ+70eDacSxwCeoshobCAuK2bBRea1gpZJaMceZGhbfWyDGO cthXGeErQFa1Lbg== X-Developer-Key: i=abel.vesa@linaro.org; a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE The Lenovo ThinkPad T14s Gen6 laptop comes with 3 Parade PS8830 retimers, one for each Type-C port. These handle the orientation and altmode switching and are controlled over I2C. In the connection chain, they sit between the USB/DisplayPort combo PHY and the Type-C connector. Describe the retimers and all gpio controlled voltage regulators used by each retimer. Also, modify the pmic glink graph to include the retimers in between the SuperSpeed/Sideband in endpoints and the QMP PHY out endpoints. Signed-off-by: Abel Vesa Reviewed-by: Johan Hovold Reviewed-by: Konrad Dybcio Tested-by: Johan Hovold --- .../dts/qcom/x1e78100-lenovo-thinkpad-t14s.dts | 305 +++++++++++++++++= +++- 1 file changed, 301 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dts b/a= rch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dts index b2c2347f54fa65f9355f0d7c008119e95bb64fb2..8949afc2f10e8fe912ac118335f= 7dc471566cf8d 100644 --- a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dts +++ b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dts @@ -92,7 +92,15 @@ port@1 { reg =3D <1>; =20 pmic_glink_ss0_ss_in: endpoint { - remote-endpoint =3D <&usb_1_ss0_qmpphy_out>; + remote-endpoint =3D <&retimer_ss0_ss_out>; + }; + }; + + port@2 { + reg =3D <2>; + + pmic_glink_ss0_con_sbu_in: endpoint { + remote-endpoint =3D <&retimer_ss0_con_sbu_out>; }; }; }; @@ -121,7 +129,15 @@ port@1 { reg =3D <1>; =20 pmic_glink_ss1_ss_in: endpoint { - remote-endpoint =3D <&usb_1_ss1_qmpphy_out>; + remote-endpoint =3D <&retimer_ss1_ss_out>; + }; + }; + + port@2 { + reg =3D <2>; + + pmic_glink_ss1_con_sbu_in: endpoint { + remote-endpoint =3D <&retimer_ss1_con_sbu_out>; }; }; }; @@ -169,6 +185,102 @@ vreg_nvme: regulator-nvme { regulator-boot-on; }; =20 + vreg_rtmr0_1p15: regulator-rtmr0-1p15 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_RTMR0_1P15"; + regulator-min-microvolt =3D <1150000>; + regulator-max-microvolt =3D <1150000>; + + gpio =3D <&pmc8380_5_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&usb0_pwr_1p15_reg_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_1p8: regulator-rtmr0-1p8 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_RTMR0_1P8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + gpio =3D <&pm8550ve_9_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&usb0_1p8_reg_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_3p3: regulator-rtmr0-3p3 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_RTMR0_3P3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + gpio =3D <&pm8550_gpios 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&usb0_3p3_reg_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_1p15: regulator-rtmr1-1p15 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_RTMR1_1P15"; + regulator-min-microvolt =3D <1150000>; + regulator-max-microvolt =3D <1150000>; + + gpio =3D <&tlmm 188 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&usb1_pwr_1p15_reg_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_1p8: regulator-rtmr1-1p8 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_RTMR1_1P8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + gpio =3D <&tlmm 175 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&usb1_pwr_1p8_reg_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_3p3: regulator-rtmr1-3p3 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_RTMR1_3P3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + gpio =3D <&tlmm 186 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&usb1_pwr_3p3_reg_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; + vph_pwr: regulator-vph-pwr { compatible =3D "regulator-fixed"; =20 @@ -607,6 +719,63 @@ keyboard@3a { }; }; =20 +&i2c3 { + clock-frequency =3D <400000>; + + status =3D "okay"; + + typec-mux@8 { + compatible =3D "parade,ps8830"; + reg =3D <0x08>; + + clocks =3D <&rpmhcc RPMH_RF_CLK3>; + + vdd-supply =3D <&vreg_rtmr0_1p15>; + vdd33-supply =3D <&vreg_rtmr0_3p3>; + vdd33-cap-supply =3D <&vreg_rtmr0_3p3>; + vddar-supply =3D <&vreg_rtmr0_1p15>; + vddat-supply =3D <&vreg_rtmr0_1p15>; + vddio-supply =3D <&vreg_rtmr0_1p8>; + + reset-gpios =3D <&pm8550_gpios 10 GPIO_ACTIVE_LOW>; + + pinctrl-0 =3D <&rtmr0_default>; + pinctrl-names =3D "default"; + + orientation-switch; + retimer-switch; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + retimer_ss0_ss_out: endpoint { + remote-endpoint =3D <&pmic_glink_ss0_ss_in>; + }; + }; + + port@1 { + reg =3D <1>; + + retimer_ss0_ss_in: endpoint { + remote-endpoint =3D <&usb_1_ss0_qmpphy_out>; + }; + }; + + port@2 { + reg =3D <2>; + + retimer_ss0_con_sbu_out: endpoint { + remote-endpoint =3D <&pmic_glink_ss0_con_sbu_in>; + }; + }; + }; + }; +}; + &i2c5 { clock-frequency =3D <400000>; =20 @@ -655,6 +824,64 @@ eusb6_repeater: redriver@4f { }; }; =20 +&i2c7 { + clock-frequency =3D <400000>; + + status =3D "okay"; + + typec-mux@8 { + compatible =3D "parade,ps8830"; + reg =3D <0x8>; + + clocks =3D <&rpmhcc RPMH_RF_CLK4>; + + vdd-supply =3D <&vreg_rtmr1_1p15>; + vdd33-supply =3D <&vreg_rtmr1_3p3>; + vdd33-cap-supply =3D <&vreg_rtmr1_3p3>; + vddar-supply =3D <&vreg_rtmr1_1p15>; + vddat-supply =3D <&vreg_rtmr1_1p15>; + vddio-supply =3D <&vreg_rtmr1_1p8>; + + reset-gpios =3D <&tlmm 176 GPIO_ACTIVE_LOW>; + + pinctrl-0 =3D <&rtmr1_default>; + pinctrl-names =3D "default"; + + retimer-switch; + orientation-switch; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + retimer_ss1_ss_out: endpoint { + remote-endpoint =3D <&pmic_glink_ss1_ss_in>; + }; + }; + + port@1 { + reg =3D <1>; + + retimer_ss1_ss_in: endpoint { + remote-endpoint =3D <&usb_1_ss1_qmpphy_out>; + }; + }; + + port@2 { + reg =3D <2>; + + retimer_ss1_con_sbu_out: endpoint { + remote-endpoint =3D <&pmic_glink_ss1_con_sbu_in>; + }; + }; + + }; + }; +}; + &i2c8 { clock-frequency =3D <400000>; =20 @@ -777,6 +1004,37 @@ &pcie6a_phy { status =3D "okay"; }; =20 +&pm8550_gpios { + rtmr0_default: rtmr0-reset-n-active-state { + pins =3D "gpio10"; + function =3D "normal"; + power-source =3D <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; + + usb0_3p3_reg_en: usb0-3p3-reg-en-state { + pins =3D "gpio11"; + function =3D "normal"; + power-source =3D <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; +}; + +&pm8550ve_9_gpios { + usb0_1p8_reg_en: usb0-1p8-reg-en-state { + pins =3D "gpio8"; + function =3D "normal"; + power-source =3D <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; +}; + &pmc8380_3_gpios { edp_bl_en: edp-bl-en-state { pins =3D "gpio4"; @@ -787,6 +1045,17 @@ edp_bl_en: edp-bl-en-state { }; }; =20 +&pmc8380_5_gpios { + usb0_pwr_1p15_reg_en: usb0-pwr-1p15-reg-en-state { + pins =3D "gpio8"; + function =3D "normal"; + power-source =3D <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; +}; + &qupv3_0 { status =3D "okay"; }; @@ -1007,6 +1276,34 @@ wake-n-pins { }; }; =20 + rtmr1_default: rtmr1-reset-n-active-state { + pins =3D "gpio176"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + usb1_pwr_1p15_reg_en: usb1-pwr-1p15-reg-en-state { + pins =3D "gpio188"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + usb1_pwr_1p8_reg_en: usb1-pwr-1p8-reg-en-state { + pins =3D "gpio175"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + usb1_pwr_3p3_reg_en: usb1-pwr-3p3-reg-en-state { + pins =3D "gpio186"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + wcd_default: wcd-reset-n-active-state { pins =3D "gpio191"; function =3D "gpio"; @@ -1045,7 +1342,7 @@ &usb_1_ss0_dwc3_hs { }; =20 &usb_1_ss0_qmpphy_out { - remote-endpoint =3D <&pmic_glink_ss0_ss_in>; + remote-endpoint =3D <&retimer_ss0_ss_in>; }; =20 &usb_1_ss1_hsphy { @@ -1077,7 +1374,7 @@ &usb_1_ss1_dwc3_hs { }; =20 &usb_1_ss1_qmpphy_out { - remote-endpoint =3D <&pmic_glink_ss1_ss_in>; + remote-endpoint =3D <&retimer_ss1_ss_in>; }; =20 &usb_2 { --=20 2.34.1 From nobody Tue Dec 16 23:47:49 2025 Received: from mail-ej1-f42.google.com (mail-ej1-f42.google.com [209.85.218.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8228F21420C for ; Thu, 20 Feb 2025 17:42:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740073379; cv=none; b=hE0HQ979Znns5nPnwUZsCfkf/RuRKV4DqTweNXigfckCJPCQ6xuej/gGjE8szrghJc9h+CJMoHI7wpT/W7BhXPbPfvPAvpeOwHfvSYaEgfQa4PT66SE/LeICm8SoO1mfTJD7mtj1Eh5zm1cAGNxXVaQr8aFi9JOHAkUOEVvsJHE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740073379; c=relaxed/simple; bh=Bvqj2Bvxl3OYmN+DIORaL6pwjqZMUxhczbq8SpPpcBg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=F7FgZZyNaXF7AchxbAqye98xjbL6Pgpku2QisoS8/OkJ/R4RkQ5PMBJiJmp8O5j6sWNIV9WXAapl5O/rx/n93xqOuDZzO9Jl0quSHIWVK2vlFiDJd5IsvVDh77iuwXhJtXa4iS/hdEwuj12D8rmGE/eHhzFCesvBSrWvrxGBDVU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=N7C2L2uF; arc=none smtp.client-ip=209.85.218.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="N7C2L2uF" Received: by mail-ej1-f42.google.com with SMTP id a640c23a62f3a-abb90c20baeso166898866b.1 for ; Thu, 20 Feb 2025 09:42:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1740073376; x=1740678176; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=PIvr/zIA/fHFAIJRV6jomca+cYE4/Uv6vfvvU7Z0u8E=; b=N7C2L2uFH2X7wa2pRPrsE5yQ/boQzwYncXn1Anb4vIDeQRXFuaepRjjCOp3A1IlSf9 L2UrrECv5qfn9J4dPO4DdIbx9An8wCdtQY2+r72tysx2xA70WRMcalIEpK2MHLsBHM7Y KnTeIiUdrfxD5sdtfd8qliJDGWFKN0Dq6JH6dqyikQryM40/ysAntczeEpecgfhq3DF5 hirue7FyT3l+M5NWW722dzyWtpLJLNa+2RiSEfQyFb4ibEHfm93JjtkOAJ1jgOPdYhv6 ijU60Td2xAhQ7AOCOn9sEu4AqUwxeinYvEviyqgVxvi5K6iMwpudxKaUqjDZ2ahVpr4B P4gw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740073376; x=1740678176; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PIvr/zIA/fHFAIJRV6jomca+cYE4/Uv6vfvvU7Z0u8E=; b=bUVHmwl4CUeuZiBZ/R6N7RRsToAGfbqT6bcFLh7YfNNQMc+dsAaYHuG8uN5UTdNOTG f/Bet4owdWZ1z2xwqj2c75RNogy1fYb0xQ1hr4vAYJinShwFqivIbmKwlNBVhaNWcTtJ u9HHlMpZWjKbxh2cV2nU0+Hzea5TvjKC57iSGnvSaSyq9pL/dJJVEmv2oo4Gm/b9Paiq XtoZGTp3neaB2BlsmbYrb7jCHhBaDtTKyp4gIOyWbUG3yokaGd+NYiVBIHsQrqds9K4B CfiygOJF06JyHkBfrO+j2PuCZaSHDjzSZMR5GuWPjObW8qY2TYkp6yy6q+xmVI595NsW YJNg== X-Forwarded-Encrypted: i=1; AJvYcCWXk9iA5gtj9Bgg23Y78I5LGliOs/MyNDm0XvSvzqq8iw6Uv9KWTYcz4BWrsL35L7U7JhbC30IvZRao2BQ=@vger.kernel.org X-Gm-Message-State: AOJu0YxdkIRTBMdhXsz0v8flnP6L1cfL7V4eGG++3NHKSHFvExtUhBLY d/RYKcJvg6S9sA71/B3RL48/c4d+W4gWfoU1BPuahPgyb1v/Y7zc36M80ob1F4g= X-Gm-Gg: ASbGnculVIPMg5/5VDbmgZvfG7bTKJnsLx2Xa82N1qutuBaKZzW4Zn6jzz0QFVPGPTk hLaqzu2KwBhR7EEYgBr9xdVD8q3e2Qzbjmn+hQOKuqCiM5pm3gXAClMBoCQeLjeQ81pITNDu4m0 EQiaXXDCBUQ1yX0X/OEgisz25elArRdCAUXHDdPWrtSH2eaUDux6VNsuzbZD/T4deKTE6MVSC8y elBEbs7LHtJ0CAnOtZ9EdEibzR9MwFGWU5evmY30sB9OYtP7z40BVD2Yvaz4nyoUqWayLOSe0c5 lfrE5LHNsC4lxw== X-Google-Smtp-Source: AGHT+IGQVC2etDTib4uxuvWzjjAQAb9eZZOOrQ8eRCihV5lRcYzD5dmzSu0YUxjREXP9QcJeRsKGrg== X-Received: by 2002:a17:906:31d7:b0:aba:598b:dbde with SMTP id a640c23a62f3a-abc099b7812mr23712166b.8.1740073375789; Thu, 20 Feb 2025 09:42:55 -0800 (PST) Received: from [127.0.1.1] ([62.231.96.41]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-abb8190d1b6sm1014496166b.36.2025.02.20.09.42.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Feb 2025 09:42:55 -0800 (PST) From: Abel Vesa Date: Thu, 20 Feb 2025 19:42:33 +0200 Subject: [PATCH RESEND v5 4/4] arm64: dts: qcom: x1e80100-t14s: Enable external DisplayPort support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250220-x1e80100-dts-crd-t14s-enable-typec-retimers-v5-4-380a3e0e7edc@linaro.org> References: <20250220-x1e80100-dts-crd-t14s-enable-typec-retimers-v5-0-380a3e0e7edc@linaro.org> In-Reply-To: <20250220-x1e80100-dts-crd-t14s-enable-typec-retimers-v5-0-380a3e0e7edc@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Johan Hovold , Dmitry Baryshkov , Rajendra Nayak , Sibi Sankar , Christophe JAILLET , Trilok Soni , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa X-Mailer: b4 0.15-dev-dedf8 X-Developer-Signature: v=1; a=openpgp-sha256; l=1261; i=abel.vesa@linaro.org; h=from:subject:message-id; bh=Bvqj2Bvxl3OYmN+DIORaL6pwjqZMUxhczbq8SpPpcBg=; b=owEBbQKS/ZANAwAKARtfRMkAlRVWAcsmYgBnt2mWEWlcTVj58VYmaZ+QdXK1+UQ82KuTSVdj0 uFPFl0UQPyJAjMEAAEKAB0WIQRO8+4RTnqPKsqn0bgbX0TJAJUVVgUCZ7dplgAKCRAbX0TJAJUV VgiSD/96ILKscjqybjFGzjmSG5oFqQHGxI80ckWLkm00/fqbD/feT4h7nuq073Pzjp0fc3JxSlD VRa5iB1aSeoRxZragYyYvicX5x6PviB3VH0Rqa9OUPwvjXg3j6dqs/4r3z/5kz+RqWFeRgWzixm Qf+pXyAVkEEuCoIIfRj1hcd0/S4H8NRTeXYU5AJDe5xGtiD42zm9pVQ3GqDxFBJpKtt0pBCz0Nf yiRWKKI03opYAkibrFuS3XV2gY2auWPBHXcfTkntrrW1Ucr2QDrFuYc9PD3H38W/x/avFkAkzEd WYpZA43S0QKsUm/6Cr7+NZXnSRTAzyq84pkTPYgADl8jgDZf1k6hS5bvOqId4nkRLCIBSCUhcqs BG5sxcHXOYkDw8JQ6rl4tLIQstBkW9zKnetYd5edd2F/bihWa17+1uKlsBSzyT48tci2xBYg62a nAtf9sHHcn3/SaEupVmXSJD2RL9MIwpnUup52x2Qi0BYAznTHhP1/0d7NTrBsnQi5TZUoMo9WVA 5Fe7Qk+CEqvo1H75ff5ZYCgXenGBz3pEDAQ9LIsobsEkdfomL2CvC4mjGg8zPZgoZTOEs5UZasT qGeQb4oTiaRVHc1hcm9w1aoWdFKF6piNvcEdWiqO/QbTLBfL//Q5Ir5mRn0ZIXvi1aJdsrpm6Xh 1K8Iq19CJdv1SNg== X-Developer-Key: i=abel.vesa@linaro.org; a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE The Lenovo ThinkPad T14s Gen6 provides external DisplayPort on all 2 USB Type-C ports. Each one of this ports is connected to a dedicated DisplayPort controller. Due to support missing in the USB/DisplayPort combo PHY driver, the external DisplayPort is limited to 2 lanes. So enable the first and second DisplayPort controllers and limit their data lanes number to 2. Signed-off-by: Abel Vesa Reviewed-by: Johan Hovold Reviewed-by: Konrad Dybcio Tested-by: Johan Hovold --- .../boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dts | 16 ++++++++++++= ++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dts b/a= rch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dts index 8949afc2f10e8fe912ac118335f7dc471566cf8d..850fdab9f0b1d38e7b8f5f81f71= 87576357c4514 100644 --- a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dts +++ b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dts @@ -924,6 +924,22 @@ &mdss { status =3D "okay"; }; =20 +&mdss_dp0 { + status =3D "okay"; +}; + +&mdss_dp0_out { + data-lanes =3D <0 1>; +}; + +&mdss_dp1 { + status =3D "okay"; +}; + +&mdss_dp1_out { + data-lanes =3D <0 1>; +}; + &mdss_dp3 { compatible =3D "qcom,x1e80100-dp"; /delete-property/ #sound-dai-cells; --=20 2.34.1