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Thu, 20 Feb 2025 09:42:12 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 51K9gBxk014611 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 20 Feb 2025 09:42:11 GMT Received: from yuanfang4-gv.ap.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 20 Feb 2025 01:42:06 -0800 From: Yuanfang Zhang Date: Thu, 20 Feb 2025 17:41:25 +0800 Subject: [PATCH 5/5] coresight-tnoc: add nodes to configure freq packet Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250220-trace-noc-driver-v1-5-15d78bd48e12@quicinc.com> References: <20250220-trace-noc-driver-v1-0-15d78bd48e12@quicinc.com> In-Reply-To: <20250220-trace-noc-driver-v1-0-15d78bd48e12@quicinc.com> To: Suzuki K Poulose , Mike Leach , James Clark , "Alexander Shishkin" CC: , , , , Yuanfang Zhang X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1740044514; l=3505; i=quic_yuanfang@quicinc.com; s=20241209; h=from:subject:message-id; bh=D9nO0Rw8IFdx8/JC61W3qCybMF46rPTusGdMNvOiv98=; b=ytz5uErs24gdEcmBxtu39+tZCkTaeRzPZqkFSIlGu3N5H9CtOudTsRJnlEculWU/ssPHawnR+ xqLzvW7E1mtCKwKVfl8Kw+cs2+1C1N6wX0DTNDJbc1E4lrTezhh8wpG X-Developer-Key: i=quic_yuanfang@quicinc.com; a=ed25519; pk=ZrIjRVq9LN8/zCQGbDEwrZK/sfnVjwQ2elyEZAOaV1Q= X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 3bG4iI2z1IT3A49eBuqdkjYEGYgTiFwY X-Proofpoint-GUID: 3bG4iI2z1IT3A49eBuqdkjYEGYgTiFwY X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-20_04,2025-02-20_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 lowpriorityscore=0 clxscore=1015 adultscore=0 phishscore=0 mlxlogscore=999 bulkscore=0 malwarescore=0 impostorscore=0 priorityscore=1501 mlxscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2502100000 definitions=main-2502200070 Three nodes for freq packet config are added here: 1. freq_type: used to set the type of issued ATB FREQ packets. 0: 'FREQ' packets; 1: 'FREQ_TS' packets. 2. freq_req_val: used to set frequency values carried by 'FREQ' and 'FREQ_TS' packets. 3. freq_ts_req: writing '1' to issue a 'FREQ' or 'FREQ_TS' packet. Signed-off-by: Yuanfang Zhang --- drivers/hwtracing/coresight/coresight-tnoc.c | 97 ++++++++++++++++++++++++= ++++ 1 file changed, 97 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-tnoc.c b/drivers/hwtraci= ng/coresight/coresight-tnoc.c index 3ff3504603f66bd595484374f1cdac90c528b665..629df98959d1bfb55771376fac2= 818a48cb9c259 100644 --- a/drivers/hwtracing/coresight/coresight-tnoc.c +++ b/drivers/hwtracing/coresight/coresight-tnoc.c @@ -112,10 +112,107 @@ static ssize_t flag_type_show(struct device *dev, } static DEVICE_ATTR_RW(flag_type); =20 +static ssize_t freq_type_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct trace_noc_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + + return sysfs_emit(buf, "%u\n", drvdata->freq_type); +} + +static ssize_t freq_type_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct trace_noc_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + unsigned long val; + + if (kstrtoul(buf, 0, &val)) + return -EINVAL; + + if (val !=3D 1 && val !=3D 0) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + if (val) + drvdata->freq_type =3D FREQ_TS; + else + drvdata->freq_type =3D FREQ; + spin_unlock(&drvdata->spinlock); + + return size; +} +static DEVICE_ATTR_RW(freq_type); + +static ssize_t freq_req_val_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct trace_noc_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + + return sysfs_emit(buf, "%u\n", drvdata->freq_req_val); +} + +static ssize_t freq_req_val_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct trace_noc_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + unsigned long val; + + if (kstrtoul(buf, 0, &val)) + return -EINVAL; + + if (val) { + spin_lock(&drvdata->spinlock); + drvdata->freq_req_val =3D val; + spin_unlock(&drvdata->spinlock); + } + + return size; +} +static DEVICE_ATTR_RW(freq_req_val); + +static ssize_t freq_ts_req_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct trace_noc_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + struct coresight_device *csdev =3D drvdata->csdev; + unsigned long val; + u32 reg; + + if (kstrtoul(buf, 0, &val)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + if (csdev->refcnt =3D=3D 0) { + spin_unlock(&drvdata->spinlock); + return -EPERM; + } + + if (val) { + reg =3D readl_relaxed(drvdata->base + TRACE_NOC_CTRL); + reg =3D reg | TRACE_NOC_CTRL_FREQTSREQ; + writel_relaxed(reg, drvdata->base + TRACE_NOC_CTRL); + } + spin_unlock(&drvdata->spinlock); + + return size; +} +static DEVICE_ATTR_WO(freq_ts_req); + static struct attribute *trace_noc_attrs[] =3D { &dev_attr_flush_req.attr, &dev_attr_flush_status.attr, &dev_attr_flag_type.attr, + &dev_attr_freq_type.attr, + &dev_attr_freq_req_val.attr, + &dev_attr_freq_ts_req.attr, NULL, }; =20 --=20 2.34.1