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[46.253.189.43]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4395a1b8397sm234417565e9.36.2025.02.20.00.49.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Feb 2025 00:49:47 -0800 (PST) From: Krzysztof Kozlowski Date: Thu, 20 Feb 2025 09:49:41 +0100 Subject: [PATCH v2 2/4] arm64: dts: qcom: sm8750: Add LPASS macro codecs and pinctrl Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250220-sm8750-audio-v2-2-fbe243c4afc3@linaro.org> References: <20250220-sm8750-audio-v2-0-fbe243c4afc3@linaro.org> In-Reply-To: <20250220-sm8750-audio-v2-0-fbe243c4afc3@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Melody Olvera , Satya Durga Srinivasu Prabhala , Srinivas Kandagatla , Krzysztof Kozlowski X-Mailer: b4 0.14.2 Add LPASS macro codecs and LPASS TLMM pin controller on Qualcomm SM8750 for proper sound support. These are fully compatible with earlier SM8550. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 202 +++++++++++++++++++++++++++++++= ++++ 1 file changed, 202 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qco= m/sm8750.dtsi index 683dd5529f02c8b446e704106294bd68d55d65dc..55668ee979a465aa0149ff9317d= 2cbc733e9c27b 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -15,6 +15,7 @@ #include #include #include +#include =20 / { interrupt-parent =3D <&intc>; @@ -2072,6 +2073,74 @@ q6prmcc: clock-controller { }; }; =20 + lpass_wsa2macro: codec@6aa0000 { + compatible =3D "qcom,sm8750-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-ma= cro"; + reg =3D <0x0 0x06aa0000 0x0 0x1000>; + clocks =3D <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE= _COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_vamacro>; + clock-names =3D "mclk", + "macro", + "dcodec", + "fsgen"; + + #clock-cells =3D <0>; + clock-output-names =3D "wsa2-mclk"; + #sound-dai-cells =3D <1>; + }; + + lpass_rxmacro: codec@6ac0000 { + compatible =3D "qcom,sm8750-lpass-rx-macro", "qcom,sm8550-lpass-rx-macr= o"; + reg =3D <0x0 0x06ac0000 0x0 0x1000>; + clocks =3D <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_C= OUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_vamacro>; + clock-names =3D "mclk", + "macro", + "dcodec", + "fsgen"; + + #clock-cells =3D <0>; + clock-output-names =3D "mclk"; + #sound-dai-cells =3D <1>; + }; + + lpass_txmacro: codec@6ae0000 { + compatible =3D "qcom,sm8750-lpass-tx-macro", "qcom,sm8550-lpass-tx-macr= o"; + reg =3D <0x0 0x06ae0000 0x0 0x1000>; + clocks =3D <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUP= LE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_vamacro>; + clock-names =3D "mclk", + "macro", + "dcodec", + "fsgen"; + + #clock-cells =3D <0>; + clock-output-names =3D "mclk"; + #sound-dai-cells =3D <1>; + }; + + lpass_wsamacro: codec@6b00000 { + compatible =3D "qcom,sm8750-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-ma= cro"; + reg =3D <0x0 0x06b00000 0x0 0x1000>; + clocks =3D <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_= COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_vamacro>; + clock-names =3D "mclk", + "macro", + "dcodec", + "fsgen"; + + #clock-cells =3D <0>; + clock-output-names =3D "mclk"; + #sound-dai-cells =3D <1>; + }; + lpass_ag_noc: interconnect@7e40000 { compatible =3D "qcom,sm8750-lpass-ag-noc"; reg =3D <0x0 0x07e40000 0x0 0xe080>; @@ -2093,6 +2162,139 @@ lpass_lpicx_noc: interconnect@7420000 { #interconnect-cells =3D <2>; }; =20 + lpass_vamacro: codec@7660000 { + compatible =3D "qcom,sm8750-lpass-va-macro", "qcom,sm8550-lpass-va-macr= o"; + reg =3D <0x0 0x07660000 0x0 0x1000>; + clocks =3D <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUP= LE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names =3D "mclk", + "macro", + "dcodec"; + + #clock-cells =3D <0>; + clock-output-names =3D "fsgen"; + #sound-dai-cells =3D <1>; + }; + + lpass_tlmm: pinctrl@7760000 { + compatible =3D "qcom,sm8750-lpass-lpi-pinctrl", + "qcom,sm8650-lpass-lpi-pinctrl"; + reg =3D <0x0 0x07760000 0x0 0x20000>; + + clocks =3D <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names =3D "core", "audio"; + + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&lpass_tlmm 0 0 23>; + + tx_swr_active: tx-swr-active-state { + clk-pins { + pins =3D "gpio0"; + function =3D "swr_tx_clk"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-disable; + }; + + data-pins { + pins =3D "gpio1", "gpio2", "gpio14"; + function =3D "swr_tx_data"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-bus-hold; + }; + }; + + rx_swr_active: rx-swr-active-state { + clk-pins { + pins =3D "gpio3"; + function =3D "swr_rx_clk"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-disable; + }; + + data-pins { + pins =3D "gpio4", "gpio5"; + function =3D "swr_rx_data"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-bus-hold; + }; + }; + + dmic01_default: dmic01-default-state { + clk-pins { + pins =3D "gpio6"; + function =3D "dmic1_clk"; + drive-strength =3D <8>; + output-high; + }; + + data-pins { + pins =3D "gpio7"; + function =3D "dmic1_data"; + drive-strength =3D <8>; + input-enable; + }; + }; + + dmic23_default: dmic23-default-state { + clk-pins { + pins =3D "gpio8"; + function =3D "dmic2_clk"; + drive-strength =3D <8>; + output-high; + }; + + data-pins { + pins =3D "gpio9"; + function =3D "dmic2_data"; + drive-strength =3D <8>; + input-enable; + }; + }; + + wsa_swr_active: wsa-swr-active-state { + clk-pins { + pins =3D "gpio10"; + function =3D "wsa_swr_clk"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-disable; + }; + + data-pins { + pins =3D "gpio11"; + function =3D "wsa_swr_data"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-bus-hold; + }; + }; + + wsa2_swr_active: wsa2-swr-active-state { + clk-pins { + pins =3D "gpio15"; + function =3D "wsa2_swr_clk"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-disable; + }; + + data-pins { + pins =3D "gpio16"; + function =3D "wsa2_swr_data"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-bus-hold; + }; + }; + }; + pdc: interrupt-controller@b220000 { compatible =3D "qcom,sm8750-pdc", "qcom,pdc"; reg =3D <0x0 0x0b220000 0x0 0x10000>, <0x0 0x164400f0 0x0 0x64>; --=20 2.43.0