From nobody Fri Dec 19 01:43:28 2025 Received: from smtp-42ae.mail.infomaniak.ch (smtp-42ae.mail.infomaniak.ch [84.16.66.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C30E81F3B91 for ; Thu, 20 Feb 2025 12:20:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=84.16.66.174 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740054046; cv=none; b=A/S9lm9qJTmhSVwdZ3w+Axyu9+Qp+vpmtgTxGe3pHhPbbmTr2wBEgwOjQuspz+p+4hlhZs5ojM8QTBQSrPskmG4BMDnJih0N/OBbl5Y31NZ+zeBhV1/vbWyEFgJ1RY0Adu2B5l54JO2G1BIIXzBVjVgYNAUsz01e7dYo1yzd3Po= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740054046; c=relaxed/simple; bh=wEHei7rK9AAwWqopWPvUals/MXPnXVHEoEKBHAfk5B0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ans6O5qyTHtJzJT2X7D6lHHaLDBLQy30PF10GS6SJI2UMdsCiF63AJleEmoBhULo0i0UPrGl/KX9DpdnLQZ5N7JtzuWsaT/dxebPKBvRv4amyyDbyradCfkMqmdTYVT0cN/pPTPMB8iGE/0pBYGWP+8lu1u5F/vRYm8TG+huWZk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=0leil.net; spf=pass smtp.mailfrom=0leil.net; arc=none smtp.client-ip=84.16.66.174 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=0leil.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=0leil.net Received: from smtp-3-0000.mail.infomaniak.ch (smtp-3-0000.mail.infomaniak.ch [10.4.36.107]) by smtp-3-3000.mail.infomaniak.ch (Postfix) with ESMTPS id 4YzC5c2v1qzsY6; Thu, 20 Feb 2025 13:20:36 +0100 (CET) Received: from unknown by smtp-3-0000.mail.infomaniak.ch (Postfix) with ESMTPA id 4YzC5b6Cy2zGpB; Thu, 20 Feb 2025 13:20:35 +0100 (CET) From: Quentin Schulz Date: Thu, 20 Feb 2025 13:20:11 +0100 Subject: [PATCH 2/5] arm64: dts: rockchip: fix pinmux of UART5 for PX30 Ringneck on Haikou Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250220-ringneck-dtbos-v1-2-25c97f2385e6@cherry.de> References: <20250220-ringneck-dtbos-v1-0-25c97f2385e6@cherry.de> In-Reply-To: <20250220-ringneck-dtbos-v1-0-25c97f2385e6@cherry.de> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Quentin Schulz , Farouk Bouabid Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Quentin Schulz , stable@vger.kernel.org X-Mailer: b4 0.14.2 X-Infomaniak-Routing: alpha From: Quentin Schulz UART5 uses GPIO0_B5 as UART RTS but muxed in its GPIO function, therefore UART5 must request this pin to be muxed in that function, so let's do that. Fixes: 5963d97aa780 ("arm64: dts: rockchip: add rs485 support on uart5 of p= x30-ringneck-haikou") Cc: stable@vger.kernel.org Signed-off-by: Quentin Schulz --- arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts b/arch/a= rm64/boot/dts/rockchip/px30-ringneck-haikou.dts index 2321536c553fed20bc02d91f40a5d5a6dc20892c..08a11e47584137ed84f31aadc53= a1bdd2ca95530 100644 --- a/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts +++ b/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts @@ -194,6 +194,13 @@ sd_card_led_pin: sd-card-led-pin { <3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; }; }; + + uart { + uart5_rts_gpio: uart5-rts-gpio { + rockchip,pins =3D + <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; }; =20 &pwm0 { @@ -227,7 +234,7 @@ &uart0 { }; =20 &uart5 { - pinctrl-0 =3D <&uart5_xfer>; + pinctrl-0 =3D <&uart5_xfer &uart5_rts_gpio>; rts-gpios =3D <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; status =3D "okay"; }; --=20 2.48.1