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Thu, 20 Feb 2025 04:22:50 -0800 (PST) From: Nick Chan Date: Thu, 20 Feb 2025 20:21:50 +0800 Subject: [PATCH 9/9] arm64: dts: apple: t8015: Add CPU caches Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250220-caches-v1-9-2c7011097768@gmail.com> References: <20250220-caches-v1-0-2c7011097768@gmail.com> In-Reply-To: <20250220-caches-v1-0-2c7011097768@gmail.com> To: Sven Peter , Janne Grunau , Alyssa Rosenzweig , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2355; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=6VGsP5C1mUSlactoow//Nl59ChZ/SauVCkyBSv3d3Es=; b=owEBbQKS/ZANAwAIAQHKCLemxQgkAcsmYgBntx5/a+YVG+deJ0Nr2fwotL1kKLBzPkzU5tQy/ qTpx6SuLeiJAjMEAAEIAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCZ7cefwAKCRABygi3psUI JJ4HD/90gXqkkbacSqy5KnE+w1N1e31n0JOSxIazQ6ex4qCut08tkl4/4KKfQDTqLWx1bRmC6Ro BmJ72nqMXNsP6M12MwndhaKXtHVKtcsIWpufScOZGpnV7BK4MvF/fM1E+EomxRJJ95oDr705j3v JSsQCHYKgbBOoZnFdvrwIOLAZPgnEsGptOFsYmC1cqvi5OiLLs1woYnHJxahOGmEFZzXvTUBxby /PrxQp1Hbu0gW6U9zfU5a6QXh89b0uhBcZ5zeHN7jv3ndXBZzLYsyhGk8Ic0+qXtJ95VxPuZ4u1 1rJPybeizYGSW+ST6G2QZ2hV/5bExjrdN/nBMlqX0oU+xpLNyzXiGJEvgtR0UzmIq37wYsk9MWn 3s3N1AP6X7EDFTHNzyB2ighs9yEbCw/eLU0bMnD1xBZmE2OhDPETVqR7bqRRXuSPdLaOMRA6pgf HXT5FXDhki0kb2nNMQ84RNR2sBzxpkmWz4uHGC/uoHN/49fVrNU6x3f41xvxD6Gy38vbVZNkEQN ocUA/F3Ij1urqV8xYarinY23Z6KMcUjrAn8WYHP/GkoXI8j0fCUBalljbFeRg7tVdrgeXokUbRp 3BJpcctT9Pv3GSoINdIB6YMreZMtr/3S1Svw+v3/a9y5CtF+IOViydTL+qlyZwgu1AB4RXYUNJJ tnjIMwLFCCG3Zgg== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Add information about CPU caches in Apple A11 SoC. Signed-off-by: Nick Chan --- arch/arm64/boot/dts/apple/t8015.dtsi | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8015.dtsi b/arch/arm64/boot/dts/app= le/t8015.dtsi index b68647bebd20782ba7a125e670b3264c184b62cd..138073dbac3c5a3ec495b078b37= 14cf800b471dd 100644 --- a/arch/arm64/boot/dts/apple/t8015.dtsi +++ b/arch/arm64/boot/dts/apple/t8015.dtsi @@ -63,6 +63,9 @@ cpu_e0: cpu@0 { capacity-dmips-mhz =3D <633>; enable-method =3D "spin-table"; device_type =3D "cpu"; + next-level-cache =3D <&l2_cache_0>; + i-cache-size =3D <0x8000>; + d-cache-size =3D <0x8000>; }; =20 cpu_e1: cpu@1 { @@ -74,6 +77,9 @@ cpu_e1: cpu@1 { capacity-dmips-mhz =3D <633>; enable-method =3D "spin-table"; device_type =3D "cpu"; + next-level-cache =3D <&l2_cache_0>; + i-cache-size =3D <0x8000>; + d-cache-size =3D <0x8000>; }; =20 cpu_e2: cpu@2 { @@ -85,6 +91,9 @@ cpu_e2: cpu@2 { capacity-dmips-mhz =3D <633>; enable-method =3D "spin-table"; device_type =3D "cpu"; + next-level-cache =3D <&l2_cache_0>; + i-cache-size =3D <0x8000>; + d-cache-size =3D <0x8000>; }; =20 cpu_e3: cpu@3 { @@ -96,6 +105,9 @@ cpu_e3: cpu@3 { capacity-dmips-mhz =3D <633>; enable-method =3D "spin-table"; device_type =3D "cpu"; + next-level-cache =3D <&l2_cache_0>; + i-cache-size =3D <0x8000>; + d-cache-size =3D <0x8000>; }; =20 cpu_p0: cpu@10004 { @@ -107,6 +119,9 @@ cpu_p0: cpu@10004 { capacity-dmips-mhz =3D <1024>; enable-method =3D "spin-table"; device_type =3D "cpu"; + next-level-cache =3D <&l2_cache_1>; + i-cache-size =3D <0x10000>; + d-cache-size =3D <0x10000>; }; =20 cpu_p1: cpu@10005 { @@ -118,6 +133,23 @@ cpu_p1: cpu@10005 { capacity-dmips-mhz =3D <1024>; enable-method =3D "spin-table"; device_type =3D "cpu"; + next-level-cache =3D <&l2_cache_1>; + i-cache-size =3D <0x10000>; + d-cache-size =3D <0x10000>; + }; + + l2_cache_0: l2-cache-0 { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + cache-size =3D <0x100000>; + }; + + l2_cache_1: l2-cache-1 { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + cache-size =3D <0x800000>; }; }; =20 --=20 2.48.1