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Thu, 20 Feb 2025 04:22:39 -0800 (PST) From: Nick Chan Date: Thu, 20 Feb 2025 20:21:46 +0800 Subject: [PATCH 5/9] arm64: dts: apple: s8001: Add CPU caches Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250220-caches-v1-5-2c7011097768@gmail.com> References: <20250220-caches-v1-0-2c7011097768@gmail.com> In-Reply-To: <20250220-caches-v1-0-2c7011097768@gmail.com> To: Sven Peter , Janne Grunau , Alyssa Rosenzweig , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1139; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=iKAQVbN6H8LNJ4L0t5TJAQywaYEBuG3C40azpKpmjE4=; b=owEBbQKS/ZANAwAIAQHKCLemxQgkAcsmYgBntx5+NPjeURwiNzAzZwx+4KYBipsYXVdqfZo8J bphtR8GE3eJAjMEAAEIAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCZ7cefgAKCRABygi3psUI JO22D/49OTwRyfjXN0ZLwJOwuqVuNXrhFrd/9B7/xmgUAgstIWuD72YkGK6u+jBzquNjMxCCBaa rofULIp28eH/iRTKp/KwVLZLPR1QvbgMR3wHzb7k+mCfM03uwH8+0Z0cWkoBsEonT5gNI378NWG EoNCrFK/318jyMX7qDJm+zAFiQYeQOcMs13xcXvROY4o3kXajsPlBO1o4PklMsatD50v6Zpq5G3 MpqKprgUxia7SGQZw4N/6B6cTBf7eoPQ1ZYeKJmtL3r6nIxTNMU+S35wQG3rUcXzVGzKaF7rhNi TpztKyGuVIvvlRRPLP+MRzptCCKujaLGWFqA3QHsA6bnKjWWCQQJrhVVAq6E/o9UORfe2bY2JiP amz4gpRMhLt8YU6qJJAntdHZj+tpeEwDKpN6IUTmuTyck+nlZKJD4GfDBTD5up5/Pfp04CDv7ox /bMRH1mX0duXQVtPVWaV9jGfATYfB/mvqSftktheaOm2l+vEJW+1ELqPU6cUkoR6n4Pqi8AT+Yi Uo8d3oK6YSMIBX/ykn3+wdQXLGiaROOm1TJrtM1i1tWR5c5j7F7Uyeo2yHsrFKwF/Q6oaED2xZW r88pwbxAvHO5/1dUchprQRWGQJWbfmlo8OwuFVOwUyFJFikZOQe2w/zh3VuChlOf/TdgxrKS1AM P3eyhYJrjvKfpzw== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Add information about CPU caches in Apple A9X SoC. Signed-off-by: Nick Chan --- arch/arm64/boot/dts/apple/s8001.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/apple/s8001.dtsi b/arch/arm64/boot/dts/app= le/s8001.dtsi index d56d49c048bbf55e5f2edf40f6fd1fcff6342a9f..fee3507658948a9b4db6a185665= fdff9f5acc446 100644 --- a/arch/arm64/boot/dts/apple/s8001.dtsi +++ b/arch/arm64/boot/dts/apple/s8001.dtsi @@ -36,6 +36,9 @@ cpu0: cpu@0 { performance-domains =3D <&cpufreq>; enable-method =3D "spin-table"; device_type =3D "cpu"; + next-level-cache =3D <&l2_cache>; + i-cache-size =3D <0x10000>; + d-cache-size =3D <0x10000>; }; =20 cpu1: cpu@1 { @@ -46,6 +49,16 @@ cpu1: cpu@1 { performance-domains =3D <&cpufreq>; enable-method =3D "spin-table"; device_type =3D "cpu"; + next-level-cache =3D <&l2_cache>; + i-cache-size =3D <0x10000>; + d-cache-size =3D <0x10000>; + }; + + l2_cache: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + cache-size =3D <0x300000>; }; }; =20 --=20 2.48.1