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Thu, 20 Feb 2025 04:22:34 -0800 (PST) From: Nick Chan Date: Thu, 20 Feb 2025 20:21:44 +0800 Subject: [PATCH 3/9] arm64: dts: apple: t7001: Add CPU caches Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250220-caches-v1-3-2c7011097768@gmail.com> References: <20250220-caches-v1-0-2c7011097768@gmail.com> In-Reply-To: <20250220-caches-v1-0-2c7011097768@gmail.com> To: Sven Peter , Janne Grunau , Alyssa Rosenzweig , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1414; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=3dP0oDAIN/InBoJgIEEqaYRol8BwNynu3ip0BA5Xbxw=; b=owEBbQKS/ZANAwAIAQHKCLemxQgkAcsmYgBntx5+6R8kl4XjwXno6F3R1YST47PDcS75fBq9D rJWwg4NDTyJAjMEAAEIAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCZ7cefgAKCRABygi3psUI JH6bD/4+Uuk91oX9dOv7aKSCauwvonXydDd98FtccI7OIe68dRR3+FUfJTG8uyXR+pYU/mNKFzR ZZUoH0VGqFto509TYITNK/SpkOdFyiXL6HeAwk7qJOfsPMRc3sigral9s7lvLIbUdtUiz6HnDCf fBBBbikZwjRa+DD+uJaQlRC1w1anizTEWrGL6t64YZfOSj2AbeJL7Zstv6NQPVhGPkcYfTZdtwL 81ZYUXPCHpSPuqWPS4QOYAsJUQU42XHCq/bti9nI3Tck9VSZ1nKy+re7Qn6os6ONPaZB78/FNHS 5e3wazbFon98qhpKB9zaR386r5uHoVcCidjHi2FW3s/zL/3XFOifV7QNwf0EpJRJFGrh7unBGsY 21iPBE1hav7RAnWirgmnQJELJ2Wb0M54976wFqtSC/DLGK8+v4Ly//P7s2z8tWESSKshNVpqNzi l6V1S2D3hp5E6xIh9l9Z3YuOPdqotRyTUZmjoAnJpl4zG97rdRDqpynbdwTyGmNncZGeo4ipggQ COriGrhTb6WgOIDPzd2Uu+uesy0JCbkMnrTyc8npg7Xo86G/lCxfhS/8BT03so0KmwrYgr4OcSW sKQGasFL7wwrZv3Ru2IDH9jP+tpRlD1CVdwZLJWbPXioIlq2obTiTytTwZ+4bG9TdjEYKMzoCva HsyzDzgsE+iB+/Q== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Add information about CPU caches in Apple A8X SoC. Signed-off-by: Nick Chan --- arch/arm64/boot/dts/apple/t7001.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t7001.dtsi b/arch/arm64/boot/dts/app= le/t7001.dtsi index 8e2c67e19c4167fc6639458ce79588e153336603..a2efa81305df47bdfea6bc2a4d6= 749719a6ee619 100644 --- a/arch/arm64/boot/dts/apple/t7001.dtsi +++ b/arch/arm64/boot/dts/apple/t7001.dtsi @@ -39,6 +39,9 @@ cpu0: cpu@0 { operating-points-v2 =3D <&typhoon_opp>; enable-method =3D "spin-table"; device_type =3D "cpu"; + next-level-cache =3D <&l2_cache>; + i-cache-size =3D <0x10000>; + d-cache-size =3D <0x10000>; }; =20 cpu1: cpu@1 { @@ -49,6 +52,9 @@ cpu1: cpu@1 { operating-points-v2 =3D <&typhoon_opp>; enable-method =3D "spin-table"; device_type =3D "cpu"; + next-level-cache =3D <&l2_cache>; + i-cache-size =3D <0x10000>; + d-cache-size =3D <0x10000>; }; =20 cpu2: cpu@2 { @@ -59,6 +65,16 @@ cpu2: cpu@2 { operating-points-v2 =3D <&typhoon_opp>; enable-method =3D "spin-table"; device_type =3D "cpu"; + next-level-cache =3D <&l2_cache>; + i-cache-size =3D <0x10000>; + d-cache-size =3D <0x10000>; + }; + + l2_cache: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + cache-size =3D <0x200000>; }; }; =20 --=20 2.48.1