From nobody Thu Dec 18 23:30:10 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id B410A1FECD9 for ; Wed, 19 Feb 2025 16:41:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739983280; cv=none; b=O8qXmcLVRLzXpTlRD0JCywgGdAvoJYxK83TFZLYBjdDCIWQPx4DgbyX4M4UB+zqLso1X1ZIEbcnE3iryVOkq0NHpgVHOD2F9LHMQY5qPE7k0di3N0bo0aGWxC7S2VSTjfBiAblc8xnDE+tmZF8v6OYuWjBJKx8DHyn9VX6DskEk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739983280; c=relaxed/simple; bh=KLnK/Ja0S9/NJfa6d61a2G0S5RlFUFSOS3iaAKUnlzw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Syn5ilrjlKDy9AsaKUyj3fB5VvEegsavCVtCL1ufWDCzkWFDGUQHx5hyVL1zF+swZQQ4LIa2yD/uozdRJtLDK4c6Tw/sYqovmAbw2Bu32XTQ2GigMrwam6Wcc7BhYNxd2iAhi9ngr0Ts4QB8QuTN/Q6K9Z0QrFoQX3jWO3Uwdgg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 820B51688; Wed, 19 Feb 2025 08:41:35 -0800 (PST) Received: from e123572-lin.arm.com (e123572-lin.cambridge.arm.com [10.1.194.54]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1BEA23F6A8; Wed, 19 Feb 2025 08:41:15 -0800 (PST) From: Kevin Brodsky To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Kevin Brodsky , Catalin Marinas , Joey Gouly , Will Deacon Subject: [PATCH 1/3] arm64/sysreg: Improve PIR/POR helpers Date: Wed, 19 Feb 2025 16:40:27 +0000 Message-ID: <20250219164029.2309119-2-kevin.brodsky@arm.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20250219164029.2309119-1-kevin.brodsky@arm.com> References: <20250219164029.2309119-1-kevin.brodsky@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" We currently have one helper to set a PIRx_ELx's permission field to a given value, PIRx_ELx_PERM(), and another helper to extract a permission field from POR_ELx, POR_ELx_IDX(). The naming is pretty confusing - it isn't clear at all that "_PERM" corresponds to a setter and "_IDX" to a getter. This patch aims at improving the situation by using the same suffixes as FIELD_PREP()/FIELD_GET(), which we have already adopted for SYS_FIELD_{PREP,GET}(): * PIRx_ELx_PERM_PREP(), POR_ELx_PERM_PREP() create a register value where the permission field for a given index is set to a given value. * POR_ELx_PERM_GET() extracts the permission field from a given register value for a given index. These helpers are not implemented using FIELD_PREP()/FIELD_GET() because the mask may not be constant, and they need to be usable in assembly. They are all defined in asm/sysreg.h, as one would expect for basic sysreg-related helpers. Finally the new POR_ELx_PERM_* macros are used for existing calculations in signal.c and mmu.c. Signed-off-by: Kevin Brodsky --- arch/arm64/include/asm/pgtable-prot.h | 36 +++++++++++++-------------- arch/arm64/include/asm/por.h | 9 +++---- arch/arm64/include/asm/sysreg.h | 10 +++++++- arch/arm64/kernel/signal.c | 2 +- arch/arm64/mm/mmu.c | 6 ++--- 5 files changed, 34 insertions(+), 29 deletions(-) diff --git a/arch/arm64/include/asm/pgtable-prot.h b/arch/arm64/include/asm= /pgtable-prot.h index a95f1f77bb39..7830d031742e 100644 --- a/arch/arm64/include/asm/pgtable-prot.h +++ b/arch/arm64/include/asm/pgtable-prot.h @@ -169,25 +169,25 @@ static inline bool __pure lpa2_is_enabled(void) #define PAGE_GCS_RO __pgprot(_PAGE_GCS_RO) =20 #define PIE_E0 ( \ - PIRx_ELx_PERM(pte_pi_index(_PAGE_GCS), PIE_GCS) | \ - PIRx_ELx_PERM(pte_pi_index(_PAGE_GCS_RO), PIE_R) | \ - PIRx_ELx_PERM(pte_pi_index(_PAGE_EXECONLY), PIE_X_O) | \ - PIRx_ELx_PERM(pte_pi_index(_PAGE_READONLY_EXEC), PIE_RX_O) | \ - PIRx_ELx_PERM(pte_pi_index(_PAGE_SHARED_EXEC), PIE_RWX_O) | \ - PIRx_ELx_PERM(pte_pi_index(_PAGE_READONLY), PIE_R_O) | \ - PIRx_ELx_PERM(pte_pi_index(_PAGE_SHARED), PIE_RW_O)) + PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_GCS), PIE_GCS) | \ + PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_GCS_RO), PIE_R) | \ + PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_EXECONLY), PIE_X_O) | \ + PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_READONLY_EXEC), PIE_RX_O) | \ + PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_SHARED_EXEC), PIE_RWX_O) | \ + PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_READONLY), PIE_R_O) | \ + PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_SHARED), PIE_RW_O)) =20 #define PIE_E1 ( \ - PIRx_ELx_PERM(pte_pi_index(_PAGE_GCS), PIE_NONE_O) | \ - PIRx_ELx_PERM(pte_pi_index(_PAGE_GCS_RO), PIE_NONE_O) | \ - PIRx_ELx_PERM(pte_pi_index(_PAGE_EXECONLY), PIE_NONE_O) | \ - PIRx_ELx_PERM(pte_pi_index(_PAGE_READONLY_EXEC), PIE_R) | \ - PIRx_ELx_PERM(pte_pi_index(_PAGE_SHARED_EXEC), PIE_RW) | \ - PIRx_ELx_PERM(pte_pi_index(_PAGE_READONLY), PIE_R) | \ - PIRx_ELx_PERM(pte_pi_index(_PAGE_SHARED), PIE_RW) | \ - PIRx_ELx_PERM(pte_pi_index(_PAGE_KERNEL_ROX), PIE_RX) | \ - PIRx_ELx_PERM(pte_pi_index(_PAGE_KERNEL_EXEC), PIE_RWX) | \ - PIRx_ELx_PERM(pte_pi_index(_PAGE_KERNEL_RO), PIE_R) | \ - PIRx_ELx_PERM(pte_pi_index(_PAGE_KERNEL), PIE_RW)) + PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_GCS), PIE_NONE_O) | \ + PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_GCS_RO), PIE_NONE_O) | \ + PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_EXECONLY), PIE_NONE_O) | \ + PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_READONLY_EXEC), PIE_R) | \ + PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_SHARED_EXEC), PIE_RW) | \ + PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_READONLY), PIE_R) | \ + PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_SHARED), PIE_RW) | \ + PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_KERNEL_ROX), PIE_RX) | \ + PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_KERNEL_EXEC), PIE_RWX) | \ + PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_KERNEL_RO), PIE_R) | \ + PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_KERNEL), PIE_RW)) =20 #endif /* __ASM_PGTABLE_PROT_H */ diff --git a/arch/arm64/include/asm/por.h b/arch/arm64/include/asm/por.h index e06e9f473675..e6bf00bd0500 100644 --- a/arch/arm64/include/asm/por.h +++ b/arch/arm64/include/asm/por.h @@ -6,26 +6,25 @@ #ifndef _ASM_ARM64_POR_H #define _ASM_ARM64_POR_H =20 -#define POR_BITS_PER_PKEY 4 -#define POR_ELx_IDX(por_elx, idx) (((por_elx) >> ((idx) * POR_BITS_PER_PKE= Y)) & 0xf) +#include =20 static inline bool por_elx_allows_read(u64 por, u8 pkey) { - u8 perm =3D POR_ELx_IDX(por, pkey); + u8 perm =3D POR_ELx_PERM_GET(pkey, por); =20 return perm & POE_R; } =20 static inline bool por_elx_allows_write(u64 por, u8 pkey) { - u8 perm =3D POR_ELx_IDX(por, pkey); + u8 perm =3D POR_ELx_PERM_GET(pkey, por); =20 return perm & POE_W; } =20 static inline bool por_elx_allows_exec(u64 por, u8 pkey) { - u8 perm =3D POR_ELx_IDX(por, pkey); + u8 perm =3D POR_ELx_PERM_GET(pkey, por); =20 return perm & POE_X; } diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysre= g.h index 05ea5223d2d5..c9ce4ce5131c 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -1062,8 +1062,11 @@ #define PIE_RX UL(0xa) #define PIE_RW UL(0xc) #define PIE_RWX UL(0xe) +#define PIE_MASK UL(0xf) =20 -#define PIRx_ELx_PERM(idx, perm) ((perm) << ((idx) * 4)) +#define PIRx_ELx_BITS_PER_IDX 4 +#define PIRx_ELx_PERM_SHIFT(idx) ((idx) * PIRx_ELx_BITS_PER_IDX) +#define PIRx_ELx_PERM_PREP(idx, perm) (((perm) & PIE_MASK) << PIRx_ELx_PER= M_SHIFT(idx)) =20 /* * Permission Overlay Extension (POE) permission encodings. @@ -1078,6 +1081,11 @@ #define POE_RXW UL(0x7) #define POE_MASK UL(0xf) =20 +#define POR_ELx_BITS_PER_IDX 4 +#define POR_ELx_PERM_SHIFT(idx) ((idx) * POR_ELx_BITS_PER_IDX) +#define POR_ELx_PERM_GET(idx, reg) (((reg) >> POR_ELx_PERM_SHIFT(idx)) & P= OE_MASK) +#define POR_ELx_PERM_PREP(idx, perm) (((perm) & POE_MASK) << POR_ELx_PERM_= SHIFT(idx)) + /* Initial value for Permission Overlay Extension for EL0 */ #define POR_EL0_INIT POE_RXW =20 diff --git a/arch/arm64/kernel/signal.c b/arch/arm64/kernel/signal.c index 99ea26d400ff..bf6226256549 100644 --- a/arch/arm64/kernel/signal.c +++ b/arch/arm64/kernel/signal.c @@ -91,7 +91,7 @@ static void save_reset_user_access_state(struct user_acce= ss_state *ua_state) u64 por_enable_all =3D 0; =20 for (int pkey =3D 0; pkey < arch_max_pkey(); pkey++) - por_enable_all |=3D POE_RXW << (pkey * POR_BITS_PER_PKEY); + por_enable_all |=3D POR_ELx_PERM_PREP(pkey, POE_RXW); =20 ua_state->por_el0 =3D read_sysreg_s(SYS_POR_EL0); write_sysreg_s(por_enable_all, SYS_POR_EL0); diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c index b4df5bc5b1b8..69a83a77ccce 100644 --- a/arch/arm64/mm/mmu.c +++ b/arch/arm64/mm/mmu.c @@ -1557,7 +1557,6 @@ int arch_set_user_pkey_access(struct task_struct *tsk= , int pkey, unsigned long i { u64 new_por =3D POE_RXW; u64 old_por; - u64 pkey_shift; =20 if (!system_supports_poe()) return -ENOSPC; @@ -1582,12 +1581,11 @@ int arch_set_user_pkey_access(struct task_struct *t= sk, int pkey, unsigned long i new_por &=3D ~POE_X; =20 /* Shift the bits in to the correct place in POR for pkey: */ - pkey_shift =3D pkey * POR_BITS_PER_PKEY; - new_por <<=3D pkey_shift; + new_por =3D POR_ELx_PERM_PREP(pkey, new_por); =20 /* Get old POR and mask off any old bits in place: */ old_por =3D read_sysreg_s(SYS_POR_EL0); - old_por &=3D ~(POE_MASK << pkey_shift); + old_por &=3D ~(POE_MASK << POR_ELx_PERM_SHIFT(pkey)); =20 /* Write old part along with new part: */ write_sysreg_s(old_por | new_por, SYS_POR_EL0); --=20 2.47.0 From nobody Thu Dec 18 23:30:10 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 128861FF1DE for ; Wed, 19 Feb 2025 16:41:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739983280; cv=none; b=Cy755IPQCR3WVLBMlHEBqy89gb1NtnXW9oVg8qEbfHKoRNCtq9fF5IrBqg9h5wn94KLxvl4ZZqgxIMtpVEaMGCjtaRDdZKPF31ETBaZk1iPdBUfFlzIyRb8dcfepMjo0ZcODdk6d48u0LChHiad5x/OpA8x/uMVe8PWtvq9utUg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739983280; c=relaxed/simple; bh=2sBR9qItZZOqfqSoJ0QH9/EK8wyYa2zIgabRbY29GmA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; 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charset="utf-8" It is customary to list R, W, X permissions in that order. In fact this is already the case for PIE constants (PIE_RWX). Rename POE_RXW accordingly, as well as POE_XW (currently unused). While at it also swap the W/X lines in compute_s1_overlay_permissions() to follow the R, W, X order. Signed-off-by: Kevin Brodsky --- arch/arm64/include/asm/sysreg.h | 6 +++--- arch/arm64/kernel/signal.c | 2 +- arch/arm64/kvm/at.c | 8 ++++---- arch/arm64/mm/mmu.c | 4 ++-- 4 files changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysre= g.h index c9ce4ce5131c..034e0576de5a 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -1077,8 +1077,8 @@ #define POE_RX UL(0x3) #define POE_W UL(0x4) #define POE_RW UL(0x5) -#define POE_XW UL(0x6) -#define POE_RXW UL(0x7) +#define POE_WX UL(0x6) +#define POE_RWX UL(0x7) #define POE_MASK UL(0xf) =20 #define POR_ELx_BITS_PER_IDX 4 @@ -1087,7 +1087,7 @@ #define POR_ELx_PERM_PREP(idx, perm) (((perm) & POE_MASK) << POR_ELx_PERM_= SHIFT(idx)) =20 /* Initial value for Permission Overlay Extension for EL0 */ -#define POR_EL0_INIT POE_RXW +#define POR_EL0_INIT POE_RWX =20 /* * Definitions for Guarded Control Stack diff --git a/arch/arm64/kernel/signal.c b/arch/arm64/kernel/signal.c index bf6226256549..a7c37afb4ebe 100644 --- a/arch/arm64/kernel/signal.c +++ b/arch/arm64/kernel/signal.c @@ -91,7 +91,7 @@ static void save_reset_user_access_state(struct user_acce= ss_state *ua_state) u64 por_enable_all =3D 0; =20 for (int pkey =3D 0; pkey < arch_max_pkey(); pkey++) - por_enable_all |=3D POR_ELx_PERM_PREP(pkey, POE_RXW); + por_enable_all |=3D POR_ELx_PERM_PREP(pkey, POE_RWX); =20 ua_state->por_el0 =3D read_sysreg_s(SYS_POR_EL0); write_sysreg_s(por_enable_all, SYS_POR_EL0); diff --git a/arch/arm64/kvm/at.c b/arch/arm64/kvm/at.c index 3a96c96816e9..f74a66ce3064 100644 --- a/arch/arm64/kvm/at.c +++ b/arch/arm64/kvm/at.c @@ -1090,22 +1090,22 @@ static void compute_s1_overlay_permissions(struct k= vm_vcpu *vcpu, break; } =20 - if (pov_perms & ~POE_RXW) + if (pov_perms & ~POE_RWX) pov_perms =3D POE_NONE; =20 if (wi->poe && wr->pov) { wr->pr &=3D pov_perms & POE_R; - wr->px &=3D pov_perms & POE_X; wr->pw &=3D pov_perms & POE_W; + wr->px &=3D pov_perms & POE_X; } =20 - if (uov_perms & ~POE_RXW) + if (uov_perms & ~POE_RWX) uov_perms =3D POE_NONE; =20 if (wi->e0poe && wr->uov) { wr->ur &=3D uov_perms & POE_R; - wr->ux &=3D uov_perms & POE_X; wr->uw &=3D uov_perms & POE_W; + wr->ux &=3D uov_perms & POE_X; } } =20 diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c index 69a83a77ccce..3c54dea1303f 100644 --- a/arch/arm64/mm/mmu.c +++ b/arch/arm64/mm/mmu.c @@ -1555,7 +1555,7 @@ void __cpu_replace_ttbr1(pgd_t *pgdp, bool cnp) #ifdef CONFIG_ARCH_HAS_PKEYS int arch_set_user_pkey_access(struct task_struct *tsk, int pkey, unsigned = long init_val) { - u64 new_por =3D POE_RXW; + u64 new_por; u64 old_por; =20 if (!system_supports_poe()) @@ -1570,7 +1570,7 @@ int arch_set_user_pkey_access(struct task_struct *tsk= , int pkey, unsigned long i return -EINVAL; =20 /* Set the bits we need in POR: */ - new_por =3D POE_RXW; + new_por =3D POE_RWX; if (init_val & PKEY_DISABLE_WRITE) new_por &=3D ~POE_W; if (init_val & PKEY_DISABLE_ACCESS) --=20 2.47.0 From nobody Thu Dec 18 23:30:10 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 51A6F1FF61E for ; Wed, 19 Feb 2025 16:41:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 15736204C; Wed, 19 Feb 2025 08:41:38 -0800 (PST) Received: from e123572-lin.arm.com (e123572-lin.cambridge.arm.com [10.1.194.54]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A424F3F6A8; Wed, 19 Feb 2025 08:41:18 -0800 (PST) From: Kevin Brodsky To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Kevin Brodsky , Catalin Marinas , Joey Gouly , Will Deacon Subject: [PATCH 3/3] arm64/sysreg: Move POR_EL0_INIT to asm/por.h Date: Wed, 19 Feb 2025 16:40:29 +0000 Message-ID: <20250219164029.2309119-4-kevin.brodsky@arm.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20250219164029.2309119-1-kevin.brodsky@arm.com> References: <20250219164029.2309119-1-kevin.brodsky@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The value of POR_EL0_INIT is not architectural, it is a software decision. Since we have a dedicated header for POR_ELx, we might as well define POR_EL0_INIT there. While at it also define POR_EL0_INIT using POR_ELx_PERM_PREP(), making it clearer that we are setting permissions for POIndex/pkey 0. Signed-off-by: Kevin Brodsky --- arch/arm64/include/asm/por.h | 2 ++ arch/arm64/include/asm/sysreg.h | 3 --- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/arm64/include/asm/por.h b/arch/arm64/include/asm/por.h index e6bf00bd0500..d913d5b529e4 100644 --- a/arch/arm64/include/asm/por.h +++ b/arch/arm64/include/asm/por.h @@ -8,6 +8,8 @@ =20 #include =20 +#define POR_EL0_INIT POR_ELx_PERM_PREP(0, POE_RWX) + static inline bool por_elx_allows_read(u64 por, u8 pkey) { u8 perm =3D POR_ELx_PERM_GET(pkey, por); diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysre= g.h index 034e0576de5a..e3252f8bb465 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -1086,9 +1086,6 @@ #define POR_ELx_PERM_GET(idx, reg) (((reg) >> POR_ELx_PERM_SHIFT(idx)) & P= OE_MASK) #define POR_ELx_PERM_PREP(idx, perm) (((perm) & POE_MASK) << POR_ELx_PERM_= SHIFT(idx)) =20 -/* Initial value for Permission Overlay Extension for EL0 */ -#define POR_EL0_INIT POE_RWX - /* * Definitions for Guarded Control Stack */ --=20 2.47.0