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Tue, 18 Feb 2025 17:10:32 -0800 (PST) Received: from cs20-buildserver.lan ([2403:c300:dc0a:4fe5:2e0:4cff:fe68:863]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-220d5348f05sm96080315ad.2.2025.02.18.17.10.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Feb 2025 17:10:32 -0800 (PST) From: Stanley Chu X-Google-Original-From: Stanley Chu To: frank.li@nxp.com, miquel.raynal@bootlin.com, alexandre.belloni@bootlin.com, linux-i3c@lists.infradead.org Cc: linux-kernel@vger.kernel.org, tomer.maimon@nuvoton.com, kwliu@nuvoton.com, yschu@nuvoton.com Subject: [PATCH v1 3/3] i3c: master: svc: fix npcm845 invalid slvstart event Date: Wed, 19 Feb 2025 09:10:19 +0800 Message-Id: <20250219011019.1600058-4-yschu@nuvoton.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250219011019.1600058-1-yschu@nuvoton.com> References: <20250219011019.1600058-1-yschu@nuvoton.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" I3C HW may generate an invalid SlvStart event when emitting a STOP. If it is a true SlvStart, the MSTATUS state should be SLVREQ. Check the MSTATUS state to ignore the false event. Signed-off-by: Stanley Chu --- drivers/i3c/master/svc-i3c-master.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/i3c/master/svc-i3c-master.c b/drivers/i3c/master/svc-i= 3c-master.c index 22cb1f1c1fdc..14cedcb81c52 100644 --- a/drivers/i3c/master/svc-i3c-master.c +++ b/drivers/i3c/master/svc-i3c-master.c @@ -59,6 +59,7 @@ #define SVC_I3C_MSTATUS_STATE(x) FIELD_GET(GENMASK(2, 0), (x)) #define SVC_I3C_MSTATUS_STATE_DAA(x) (SVC_I3C_MSTATUS_STATE(x) =3D=3D 5) #define SVC_I3C_MSTATUS_STATE_IDLE(x) (SVC_I3C_MSTATUS_STATE(x) =3D=3D 0) +#define SVC_I3C_MSTATUS_STATE_SLVREQ(x) (SVC_I3C_MSTATUS_STATE(x) =3D=3D= 1) #define SVC_I3C_MSTATUS_BETWEEN(x) FIELD_GET(BIT(4), (x)) #define SVC_I3C_MSTATUS_NACKED(x) FIELD_GET(BIT(5), (x)) #define SVC_I3C_MSTATUS_IBITYPE(x) FIELD_GET(GENMASK(7, 6), (x)) @@ -143,6 +144,12 @@ * Fill the FIFO in advance to prevent FIFO from becoming empty. */ #define SVC_I3C_QUIRK_FIFO_EMPTY BIT(0) +/* + * SVC_I3C_QUIRK_FLASE_SLVSTART: + * I3C HW may generate an invalid SlvStart event when emitting a STOP. + * If it is a true SlvStart, the MSTATUS state should be SLVREQ. + */ +#define SVC_I3C_QUIRK_FALSE_SLVSTART BIT(1) =20 struct svc_i3c_cmd { u8 addr; @@ -576,6 +583,11 @@ static irqreturn_t svc_i3c_master_irq_handler(int irq,= void *dev_id) /* Clear the interrupt status */ writel(SVC_I3C_MINT_SLVSTART, master->regs + SVC_I3C_MSTATUS); =20 + /* Ignore the false event */ + if ((master->quirks & SVC_I3C_QUIRK_FIFO_EMPTY) && + !SVC_I3C_MSTATUS_STATE_SLVREQ(active)) + return IRQ_HANDLED; + svc_i3c_master_disable_interrupts(master); =20 /* Handle the interrupt in a non atomic context */ @@ -1915,7 +1927,8 @@ static int svc_i3c_master_probe(struct platform_devic= e *pdev) svc_i3c_master_reset(master); =20 if (device_is_compatible(master->dev, "nuvoton,npcm845-i3c")) - master->quirks =3D SVC_I3C_QUIRK_FIFO_EMPTY; + master->quirks =3D SVC_I3C_QUIRK_FIFO_EMPTY | + SVC_I3C_QUIRK_FALSE_SLVSTART; =20 /* Register the master */ ret =3D i3c_master_register(&master->base, &pdev->dev, --=20 2.34.1