From nobody Fri Dec 19 07:26:40 2025 Received: from fllvem-ot03.ext.ti.com (fllvem-ot03.ext.ti.com [198.47.19.245]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B87A61E5201; Tue, 18 Feb 2025 18:55:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.245 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739904915; cv=none; b=VVYOg8Sf/6jcCbTdLPvpp1H1Nx60SU8CxG3GFUUvFg+OBfAwG7rmJiaseiJDXaSLJ/rzkRGRYs8/MeDSifTitb7cphWUN9UlvfoE73HDEfW8dG0lp/oecU/QXBva+bJ7YhKgADnJ0iGunVEmxRb/o9LriohTg824hZp6R3uRjtM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739904915; c=relaxed/simple; bh=lpNMHdvmuzzHYEXpcCaam4+YBu+ZIqP0etGoxNjExl0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=OwE4sdayQvdOgGdl7pe0Wc5khBMP5wBT4ZZemmZL1s6uoYJy5jTdEp4gsdGFcVqCOuGOEvb/o44+Th1IAyW/JYyiPZyAJLzrx8s0xcXBNQVCjUN0JscwaO1Ff8sGgZnDWT2Y9kax9r75gaSeVGg8v+T2oepoIk78PIT0+H50pt8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=eBCcKc2M; arc=none smtp.client-ip=198.47.19.245 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="eBCcKc2M" Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllvem-ot03.ext.ti.com (8.15.2/8.15.2) with ESMTPS id 51IIt1cJ1601148 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 18 Feb 2025 12:55:01 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1739904901; bh=EYoaQKOG0j2VrFU1cmqPC5t9p1n01H3GC07p2m/mp0Q=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=eBCcKc2MQgD3O9wzLYQLqDp2RHlNaf8SSa6l6pTgiMq91KUI6EuyE47VVakrXZuC0 Db/KBV/mcKnamNJDDuv+ANgoTZFK9i6Q4QL2KJUlP6VB+OQa5KEDVeyYJDKg2bnqcr k+PC2j+qOcFzUofvw0rnkFAyJoLLFDtqLeiQKlyY= Received: from DLEE108.ent.ti.com (dlee108.ent.ti.com [157.170.170.38]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 51IIt1GX021064 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 18 Feb 2025 12:55:01 -0600 Received: from DLEE115.ent.ti.com (157.170.170.26) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 18 Feb 2025 12:55:00 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 18 Feb 2025 12:55:00 -0600 Received: from uda0490681.. ([10.24.69.142]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 51IIsrxZ123821; Tue, 18 Feb 2025 12:54:57 -0600 From: Vaishnav Achath To: , , , , , , , CC: , , , Subject: [PATCH 1/5] arm64: dts: ti: k3-j722s-main: Add BCDMA CSI overrides Date: Wed, 19 Feb 2025 00:24:48 +0530 Message-ID: <20250218185452.600797-2-vaishnav.a@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250218185452.600797-1-vaishnav.a@ti.com> References: <20250218185452.600797-1-vaishnav.a@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" J722S has a dedicated CSI BCDMA instance which is slightly different from AM62P in TX channel support, add the overrides and additional properties to support CSI BCDMA on J722S. Signed-off-by: Vaishnav Achath Reviewed-by: Yemike Abhilash Chandra --- arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-j722s-main.dtsi index 3ac2d45a0558..f8e4424f3bb7 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi @@ -204,6 +204,16 @@ c7x_1: dsp@7e200000 { }; }; =20 +&main_bcdma_csi { + compatible =3D "ti,j722s-dmss-bcdma-csi"; + reg =3D <0x00 0x4e230000 0x00 0x100>, + <0x00 0x4e180000 0x00 0x20000>, + <0x00 0x4e300000 0x00 0x10000>, + <0x00 0x4e100000 0x00 0x80000>; + reg-names =3D "gcfg", "rchanrt", "tchanrt", "ringrt"; + ti,sci-rm-range-tchan =3D <0x22>; +}; + /* MCU domain overrides */ =20 &mcu_r5fss0_core0 { --=20 2.34.1 From nobody Fri Dec 19 07:26:40 2025 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EE2E81E51E0; Tue, 18 Feb 2025 18:55:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.246 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739904915; cv=none; b=N6lX2SILrT+WIwoocN7njKzJcJAVDZyjkWS5FeBKm+pMnffGKr/X8GI1ILtEu5qxlryHEd21PHkZ/IFuU5WEbgSSG5ZeKszGhB4uD7UzM45UIh2AMMcsSFQ/ZD4Mv9vVaa/08EyMr4IU0KPo9M3IR1KLprJlbS+DyAfvCvJnPko= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739904915; c=relaxed/simple; bh=5TmJAiZBN90TOu4q/jkNIQcsUGmjWFWHXB+2deRRvNw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ZkUVbojkeoNrLc/tFAClhZeMQdP8+ZmjYPNdY8EXNirgG1RFnYGn/8lM8NmKKzv5/eShONb1JcsLJegS4V639oU2kwIj6TDU67QjIcDytVzOp3HydzL0dy5spcSLfClp4hrJXY8SJDcEBGY99AO7cH1kfRELvMYStZP6Wptkku8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=FvhT1M73; arc=none smtp.client-ip=198.47.19.246 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="FvhT1M73" Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllvem-ot04.ext.ti.com (8.15.2/8.15.2) with ESMTPS id 51IIt4b2060601 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 18 Feb 2025 12:55:04 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1739904904; bh=+mzZWC6x4HtKvt8lE1i3uuPpKisVzmzGwWeB1THsahc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=FvhT1M73oH/+1EmkvOkolL6mdvR/7BPV+5JmGpRcdIV+mQEwXmIOx5stvHxjyv3At OAhSnGAH2Jx7+mYJBAIfxgjH7EU7Nr6ZKDYLdS5nTkKTYetNG3TAVT0Tz/8tMZQhrr MKOKl/q3P3YzUGFAvw4PL//SMa5exESltZbzZWvA= Received: from DLEE114.ent.ti.com (dlee114.ent.ti.com [157.170.170.25]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 51IIt4fN061082 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 18 Feb 2025 12:55:04 -0600 Received: from DLEE113.ent.ti.com (157.170.170.24) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 18 Feb 2025 12:55:04 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 18 Feb 2025 12:55:04 -0600 Received: from uda0490681.. ([10.24.69.142]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 51IIsrxa123821; Tue, 18 Feb 2025 12:55:01 -0600 From: Vaishnav Achath To: , , , , , , , CC: , , , Subject: [PATCH 2/5] arm64: dts: ti: k3-j722s-main: Add CSI2RX nodes Date: Wed, 19 Feb 2025 00:24:49 +0530 Message-ID: <20250218185452.600797-3-vaishnav.a@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250218185452.600797-1-vaishnav.a@ti.com> References: <20250218185452.600797-1-vaishnav.a@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" J722S has 4 CSI2RX receiver instances with external DPHY. The first CSI2RX instance node is derived from the AM62P common dtsi, Add the nodes for the subsequent three instances and keep them disabled. TRM (12.6 Camera Peripherals): https://www.ti.com/lit/zip/sprujb3 Signed-off-by: Vaishnav Achath Reviewed-by: Yemike Abhilash Chandra --- arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 183 ++++++++++++++++++++++ 1 file changed, 183 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-j722s-main.dtsi index f8e4424f3bb7..e69e9b34c0a4 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi @@ -154,6 +154,189 @@ usb1: usb@31200000 { }; }; =20 + ti_csi2rx1: ticsi2rx@30122000 { + compatible =3D "ti,j721e-csi2rx-shim"; + reg =3D <0x00 0x30122000 0x00 0x1000>; + ranges; + #address-cells =3D <2>; + #size-cells =3D <2>; + dmas =3D <&main_bcdma_csi 0 0x5100 0>; + dma-names =3D "rx0"; + power-domains =3D <&k3_pds 247 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; + + cdns_csi2rx1: csi-bridge@30121000 { + compatible =3D "ti,j721e-csi2rx", "cdns,csi2rx"; + reg =3D <0x00 0x30121000 0x00 0x1000>; + clocks =3D <&k3_clks 247 0>, <&k3_clks 247 3>, <&k3_clks 247 0>, + <&k3_clks 247 0>, <&k3_clks 247 4>, <&k3_clks 247 4>; + clock-names =3D "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys =3D <&dphy1>; + phy-names =3D "dphy"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + csi1_port0: port@0 { + reg =3D <0>; + status =3D "disabled"; + }; + + csi1_port1: port@1 { + reg =3D <1>; + status =3D "disabled"; + }; + + csi1_port2: port@2 { + reg =3D <2>; + status =3D "disabled"; + }; + + csi1_port3: port@3 { + reg =3D <3>; + status =3D "disabled"; + }; + + csi1_port4: port@4 { + reg =3D <4>; + status =3D "disabled"; + }; + }; + }; + }; + + ti_csi2rx2: ticsi2rx@30142000 { + compatible =3D "ti,j721e-csi2rx-shim"; + reg =3D <0x00 0x30142000 0x00 0x1000>; + ranges; + #address-cells =3D <2>; + #size-cells =3D <2>; + power-domains =3D <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>; + dmas =3D <&main_bcdma_csi 0 0x5200 0>; + dma-names =3D "rx0"; + status =3D "disabled"; + + cdns_csi2rx2: csi-bridge@30141000 { + compatible =3D "ti,j721e-csi2rx", "cdns,csi2rx"; + reg =3D <0x00 0x30141000 0x00 0x1000>; + clocks =3D <&k3_clks 248 0>, <&k3_clks 248 3>, <&k3_clks 248 0>, + <&k3_clks 248 0>, <&k3_clks 248 4>, <&k3_clks 248 4>; + clock-names =3D "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys =3D <&dphy2>; + phy-names =3D "dphy"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + csi2_port0: port@0 { + reg =3D <0>; + status =3D "disabled"; + }; + + csi2_port1: port@1 { + reg =3D <1>; + status =3D "disabled"; + }; + + csi2_port2: port@2 { + reg =3D <2>; + status =3D "disabled"; + }; + + csi2_port3: port@3 { + reg =3D <3>; + status =3D "disabled"; + }; + + csi2_port4: port@4 { + reg =3D <4>; + status =3D "disabled"; + }; + }; + }; + }; + + ti_csi2rx3: ticsi2rx@30162000 { + compatible =3D "ti,j721e-csi2rx-shim"; + reg =3D <0x00 0x30162000 0x00 0x1000>; + ranges; + #address-cells =3D <2>; + #size-cells =3D <2>; + dmas =3D <&main_bcdma_csi 0 0x5300 0>; + dma-names =3D "rx0"; + power-domains =3D <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; + + cdns_csi2rx3: csi-bridge@30161000 { + compatible =3D "ti,j721e-csi2rx", "cdns,csi2rx"; + reg =3D <0x00 0x30161000 0x00 0x1000>; + clocks =3D <&k3_clks 249 0>, <&k3_clks 249 3>, <&k3_clks 249 0>, + <&k3_clks 249 0>, <&k3_clks 249 4>, <&k3_clks 249 4>; + clock-names =3D "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys =3D <&dphy3>; + phy-names =3D "dphy"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + csi3_port0: port@0 { + reg =3D <0>; + status =3D "disabled"; + }; + + csi3_port1: port@1 { + reg =3D <1>; + status =3D "disabled"; + }; + + csi3_port2: port@2 { + reg =3D <2>; + status =3D "disabled"; + }; + + csi3_port3: port@3 { + reg =3D <3>; + status =3D "disabled"; + }; + + csi3_port4: port@4 { + reg =3D <4>; + status =3D "disabled"; + }; + }; + }; + }; + + dphy1: phy@30130000 { + compatible =3D "cdns,dphy-rx"; + reg =3D <0x00 0x30130000 0x00 0x1100>; + #phy-cells =3D <0>; + power-domains =3D <&k3_pds 251 TI_SCI_PD_EXCLUSIVE>; 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([10.24.69.142]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 51IIsrxb123821; Tue, 18 Feb 2025 12:55:04 -0600 From: Vaishnav Achath To: , , , , , , , CC: , , , Subject: [PATCH 3/5] arm64: dts: ti: k3-j722s-evm: Add camera peripherals Date: Wed, 19 Feb 2025 00:24:50 +0530 Message-ID: <20250218185452.600797-4-vaishnav.a@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250218185452.600797-1-vaishnav.a@ti.com> References: <20250218185452.600797-1-vaishnav.a@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" J722S EVM has four RPi camera connectors and dual MIPI Samtec CSI connectors which bring out the 4 x CSI2RX instances and the I2C camera control interfaces. Add the nodes for PCA9543 I2C switch and enable them. J722S EVM schematics: https://www.ti.com/lit/pdf/sprujb5 Signed-off-by: Vaishnav Achath Reviewed-by: Yemike Abhilash Chandra --- arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 28 +++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/= ti/k3-j722s-evm.dts index d184e9c1a0a5..5c0200c8811d 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts @@ -263,6 +263,13 @@ J722S_IOPAD(0x01e4, PIN_INPUT_PULLUP, 0) /* (B22) I2C0= _SDA */ bootph-all; }; =20 + main_i2c2_pins_default: main-i2c2-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x00b0, PIN_INPUT_PULLUP, 1) /* (P22) GPMC0_CSn2.I2C2_SCL */ + J722S_IOPAD(0x00b4, PIN_INPUT_PULLUP, 1) /* (P23) GPMC0_CSn3.I2C2_SDA */ + >; + }; + main_uart0_pins_default: main-uart0-default-pins { pinctrl-single,pins =3D < J722S_IOPAD(0x01c8, PIN_INPUT, 0) /* (A22) UART0_RXD */ @@ -631,6 +638,27 @@ tlv320aic3106: audio-codec@1b { }; }; =20 +&main_i2c2 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_i2c2_pins_default>; + clock-frequency =3D <400000>; + + pca9543_0: i2c-mux@70 { + compatible =3D "nxp,pca9543"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x70>; + }; + + pca9543_1: i2c-mux@71 { + compatible =3D "nxp,pca9543"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x71>; + }; +}; + &ospi0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&ospi0_pins_default>; --=20 2.34.1 From nobody Fri Dec 19 07:26:40 2025 Received: from fllvem-ot03.ext.ti.com (fllvem-ot03.ext.ti.com [198.47.19.245]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8B8721F583E; Tue, 18 Feb 2025 18:55:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.245 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739904920; cv=none; b=IF2fWu8P8kKuvtOMXonQ9WEHWfdxq/vSQZmM71QqzqroBUmqimk5FoBCMp6mq6NTwrculv4fMTyp/8Zwp404kuONKsYVr+a43m1x/00Ht/dyul6u/xNchDpvBKVibz2AAUKVRSGzftq0qzPEWlOdo/bN58Pn6twQ4W7RGn14+bo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739904920; c=relaxed/simple; bh=J1HlAHpkkPhDDk4h0ruhlOUuMzpadp3AhQP881j1pQk=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=h2WSzpqjb+xRx5YJb3sGStfKzpDs0QiNaSvgZ+TX7jw3+UVW1UbtjYV6EHlok4Nqyw/xL12H+ucevrCiW6Z1HncwREsby3MT6Tb0ls5yRdNDBqsWXpFtEzJzbk6qGyxPyzMpQfQknprpmfrV39Rye3UXiXTsIQndoa/9CYHJXzQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=m81HEGrZ; arc=none smtp.client-ip=198.47.19.245 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="m81HEGrZ" Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllvem-ot03.ext.ti.com (8.15.2/8.15.2) with ESMTPS id 51IItBT51601174 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 18 Feb 2025 12:55:11 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1739904911; bh=mxgXZggM7Pg2CEvVKuB/y6pGBU0FKd7gcuHTG8f+iMQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=m81HEGrZc+rvN6NeTT8auOhoiV8RCEzLXRNmBdzV3b9FjDS+KiEmXfh7ronMMWWI7 7a5UAIcXYDdvEonLVVtbB9i8W9odG9Jbb3fqrWz7t9Do8OzCigPrCCDH4Zs0lIYEWu uzsMcYwz5PaVTryJ13A0vmVvGxND/5CXgkBkLzvQ= Received: from DLEE107.ent.ti.com (dlee107.ent.ti.com [157.170.170.37]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 51IItBgc001025 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 18 Feb 2025 12:55:11 -0600 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 18 Feb 2025 12:55:11 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 18 Feb 2025 12:55:11 -0600 Received: from uda0490681.. ([10.24.69.142]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 51IIsrxc123821; Tue, 18 Feb 2025 12:55:08 -0600 From: Vaishnav Achath To: , , , , , , , CC: , , , Subject: [PATCH 4/5] arm64: dts: ti: k3-j722s-evm: Add overlay for quad IMX219 Date: Wed, 19 Feb 2025 00:24:51 +0530 Message-ID: <20250218185452.600797-5-vaishnav.a@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250218185452.600797-1-vaishnav.a@ti.com> References: <20250218185452.600797-1-vaishnav.a@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" RPi v2 Camera (IMX219) is an 8MP camera that can be used with J722S EVM through the 22-pin CSI-RX connector. Add a reference overlay for quad IMX219 RPI camera v2 modules on J722S EVM Signed-off-by: Vaishnav Achath Reviewed-by: Yemike Abhilash Chandra --- arch/arm64/boot/dts/ti/Makefile | 5 + ...k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtso | 304 ++++++++++++++++++ 2 files changed, 309 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-j722s-evm-csi2-quad-rpi-cam-i= mx219.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makef= ile index 8a4bdf87e2d4..9ae0917e5763 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -119,6 +119,7 @@ dtb-$(CONFIG_ARCH_K3) +=3D k3-j721s2-evm-pcie1-ep.dtbo # Boards with J722s SoC dtb-$(CONFIG_ARCH_K3) +=3D k3-am67a-beagley-ai.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-j722s-evm.dtb +dtb-$(CONFIG_ARCH_K3) +=3D k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtbo =20 # Boards with J784s4 SoC dtb-$(CONFIG_ARCH_K3) +=3D k3-am69-sk.dtb @@ -209,6 +210,8 @@ k3-j721e-sk-csi2-dual-imx219-dtbs :=3D k3-j721e-sk.dtb \ k3-j721e-sk-csi2-dual-imx219.dtbo k3-j721s2-evm-pcie1-ep-dtbs :=3D k3-j721s2-common-proc-board.dtb \ k3-j721s2-evm-pcie1-ep.dtbo +k3-j722s-evm-csi2-quad-rpi-cam-imx219-dtbs :=3D k3-j722s-evm.dtb \ + k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtbo k3-j784s4-evm-pcie0-pcie1-ep-dtbs :=3D k3-j784s4-evm.dtb \ k3-j784s4-evm-pcie0-pcie1-ep.dtbo k3-j784s4-evm-quad-port-eth-exp1-dtbs :=3D k3-j784s4-evm.dtb \ @@ -243,6 +246,7 @@ dtb- +=3D k3-am625-beagleplay-csi2-ov5640.dtb \ k3-j721e-evm-pcie1-ep.dtb \ k3-j721e-sk-csi2-dual-imx219.dtb \ k3-j721s2-evm-pcie1-ep.dtb \ + k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtb \ k3-j784s4-evm-pcie0-pcie1-ep.dtb \ k3-j784s4-evm-quad-port-eth-exp1.dtb \ k3-j784s4-evm-usxgmii-exp1-exp2.dtb @@ -266,5 +270,6 @@ DTC_FLAGS_k3-j721e-common-proc-board +=3D -@ DTC_FLAGS_k3-j721e-evm-pcie0-ep +=3D -@ DTC_FLAGS_k3-j721e-sk +=3D -@ DTC_FLAGS_k3-j721s2-common-proc-board +=3D -@ +DTC_FLAGS_k3-j722s-evm +=3D -@ DTC_FLAGS_k3-j784s4-evm +=3D -@ DTC_FLAGS_k3-j742s2-evm +=3D -@ diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm-csi2-quad-rpi-cam-imx219.d= tso b/arch/arm64/boot/dts/ti/k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtso new file mode 100644 index 000000000000..4c5ec2c7826e --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtso @@ -0,0 +1,304 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * DT Overlay for RPi Camera V2.1 on J722S-EVM board. + * + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + * + * Schematics: https://datasheets.raspberrypi.com/camera/camera-v2-schemat= ics.pdf + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&main_pmx0 { + cam0_reset_pins_default: cam0-reset-pins-default { + pinctrl-single,pins =3D < + J722S_IOPAD(0x03c, PIN_OUTPUT, 7) + >; + }; + + cam1_reset_pins_default: cam1-reset-pins-default { + pinctrl-single,pins =3D < + J722S_IOPAD(0x044, PIN_OUTPUT, 7) + >; + }; + + cam2_reset_pins_default: cam2-reset-pins-default { + pinctrl-single,pins =3D < + J722S_IOPAD(0x04c, PIN_OUTPUT, 7) + >; + }; + + cam3_reset_pins_default: cam3-reset-pins-default { + pinctrl-single,pins =3D < + J722S_IOPAD(0x054, PIN_OUTPUT, 7) + >; + }; +}; + +&{/} { + clk_imx219_fixed: imx219-xclk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <24000000>; + }; +}; + +&exp1 { + p06-hog{ + /* P06 - CSI01_MUX_SEL_2 */ + gpio-hog; + gpios =3D <6 GPIO_ACTIVE_HIGH>; + output-high; + line-name =3D "CSI01_MUX_SEL_2"; + }; + + p07-hog{ + /* P01 - CSI23_MUX_SEL_2 */ + gpio-hog; + gpios =3D <7 GPIO_ACTIVE_HIGH>; + output-high; + line-name =3D "CSI23_MUX_SEL_2"; + }; +}; + +&pca9543_0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + + i2c-alias-pool =3D /bits/ 16 <0x10 0x11>; + + /* CAM0 I2C */ + i2c@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + + imx219_0: sensor@10 { + compatible =3D "sony,imx219"; + reg =3D <0x10>; + + clocks =3D <&clk_imx219_fixed>; + clock-names =3D "xclk"; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cam0_reset_pins_default>; + + reset-gpios =3D <&main_gpio0 15 GPIO_ACTIVE_HIGH>; + + port { + csi2_cam0: endpoint { + remote-endpoint =3D <&csi2rx0_in_sensor>; + link-frequencies =3D /bits/ 64 <456000000>; + clock-lanes =3D <0>; + data-lanes =3D <1 2>; + }; + }; + }; + }; + + /* CAM1 I2C */ + i2c@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + + imx219_1: sensor@10 { + compatible =3D "sony,imx219"; + reg =3D <0x10>; + + clocks =3D <&clk_imx219_fixed>; + clock-names =3D "xclk"; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cam1_reset_pins_default>; + + reset-gpios =3D <&main_gpio0 17 GPIO_ACTIVE_HIGH>; + + port { + csi2_cam1: endpoint { + remote-endpoint =3D <&csi2rx1_in_sensor>; + link-frequencies =3D /bits/ 64 <456000000>; + clock-lanes =3D <0>; + data-lanes =3D <1 2>; + }; + }; + }; + }; +}; + +&pca9543_1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + + i2c-alias-pool =3D /bits/ 16 <0x10 0x11>; + + /* CAM0 I2C */ + i2c@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + + imx219_2: sensor@10 { + compatible =3D "sony,imx219"; + reg =3D <0x10>; + + clocks =3D <&clk_imx219_fixed>; + clock-names =3D "xclk"; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cam2_reset_pins_default>; + + reset-gpios =3D <&main_gpio0 19 GPIO_ACTIVE_HIGH>; + + port { + csi2_cam2: endpoint { + remote-endpoint =3D <&csi2rx2_in_sensor>; + link-frequencies =3D /bits/ 64 <456000000>; + clock-lanes =3D <0>; + data-lanes =3D <1 2>; + }; + }; + }; + }; + + /* CAM1 I2C */ + i2c@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + + imx219_3: sensor@10 { + compatible =3D "sony,imx219"; + reg =3D <0x10>; + + clocks =3D <&clk_imx219_fixed>; + clock-names =3D "xclk"; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cam3_reset_pins_default>; + + reset-gpios =3D <&main_gpio0 21 GPIO_ACTIVE_HIGH>; + + port { + csi2_cam3: endpoint { + remote-endpoint =3D <&csi2rx3_in_sensor>; + link-frequencies =3D /bits/ 64 <456000000>; + clock-lanes =3D <0>; + data-lanes =3D <1 2>; + }; + }; + }; + }; +}; + +&cdns_csi2rx0 { + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + csi0_port0: port@0 { + reg =3D <0>; + status =3D "okay"; + + csi2rx0_in_sensor: endpoint { + remote-endpoint =3D <&csi2_cam0>; + bus-type =3D <4>; /* CSI2 DPHY */ + clock-lanes =3D <0>; + data-lanes =3D <1 2>; + }; + }; + }; +}; + +&cdns_csi2rx1 { + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + csi1_port0: port@0 { + reg =3D <0>; + status =3D "okay"; + + csi2rx1_in_sensor: endpoint { + remote-endpoint =3D <&csi2_cam1>; + bus-type =3D <4>; /* CSI2 DPHY */ + clock-lanes =3D <0>; + data-lanes =3D <1 2>; + }; + }; + }; +}; + +&cdns_csi2rx2 { + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + csi2_port0: port@0 { + reg =3D <0>; + status =3D "okay"; + + csi2rx2_in_sensor: endpoint { + remote-endpoint =3D <&csi2_cam2>; + bus-type =3D <4>; /* CSI2 DPHY */ + clock-lanes =3D <0>; + data-lanes =3D <1 2>; + }; + }; + }; +}; + +&cdns_csi2rx3 { + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + csi3_port0: port@0 { + reg =3D <0>; + status =3D "okay"; + + csi2rx3_in_sensor: endpoint { + remote-endpoint =3D <&csi2_cam3>; + bus-type =3D <4>; /* CSI2 DPHY */ + clock-lanes =3D <0>; + data-lanes =3D <1 2>; + }; + }; + }; +}; + +&ti_csi2rx0 { + status =3D "okay"; +}; + +&dphy0 { + status =3D "okay"; +}; + +&ti_csi2rx1 { + status =3D "okay"; +}; + +&dphy1 { + status =3D "okay"; +}; + +&ti_csi2rx2 { + status =3D "okay"; +}; + +&dphy2 { + status =3D "okay"; +}; + +&ti_csi2rx3 { + status =3D "okay"; +}; + +&dphy3 { + status =3D "okay"; +}; --=20 2.34.1 From nobody Fri Dec 19 07:26:40 2025 Received: from lelvem-ot02.ext.ti.com (lelvem-ot02.ext.ti.com [198.47.23.235]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E2645272921; 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([10.24.69.142]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 51IIsrxd123821; Tue, 18 Feb 2025 12:55:11 -0600 From: Vaishnav Achath To: , , , , , , , CC: , , , Subject: [PATCH 5/5] arm64: dts: ti: k3-j722s-evm: Add overlay for TEVI OV5640 Date: Wed, 19 Feb 2025 00:24:52 +0530 Message-ID: <20250218185452.600797-6-vaishnav.a@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250218185452.600797-1-vaishnav.a@ti.com> References: <20250218185452.600797-1-vaishnav.a@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" TechNexion TEVI OV5640 camera is a 5MP camera that can be used with J722S EVM through the 22-pin CSI-RX connector. Add a reference overlay for quad TEVI OV5640 modules on J722S EVM. Signed-off-by: Vaishnav Achath Reviewed-by: Yemike Abhilash Chandra --- arch/arm64/boot/dts/ti/Makefile | 4 + .../k3-j722s-evm-csi2-quad-tevi-ov5640.dtso | 319 ++++++++++++++++++ 2 files changed, 323 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-j722s-evm-csi2-quad-tevi-ov56= 40.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makef= ile index 9ae0917e5763..0370392abda8 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -120,6 +120,7 @@ dtb-$(CONFIG_ARCH_K3) +=3D k3-j721s2-evm-pcie1-ep.dtbo dtb-$(CONFIG_ARCH_K3) +=3D k3-am67a-beagley-ai.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-j722s-evm.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtbo +dtb-$(CONFIG_ARCH_K3) +=3D k3-j722s-evm-csi2-quad-tevi-ov5640.dtbo =20 # Boards with J784s4 SoC dtb-$(CONFIG_ARCH_K3) +=3D k3-am69-sk.dtb @@ -212,6 +213,8 @@ k3-j721s2-evm-pcie1-ep-dtbs :=3D k3-j721s2-common-proc-= board.dtb \ k3-j721s2-evm-pcie1-ep.dtbo k3-j722s-evm-csi2-quad-rpi-cam-imx219-dtbs :=3D k3-j722s-evm.dtb \ k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtbo +k3-j722s-evm-csi2-quad-tevi-ov5640-dtbs :=3D k3-j722s-evm.dtb \ + k3-j722s-evm-csi2-quad-tevi-ov5640.dtbo k3-j784s4-evm-pcie0-pcie1-ep-dtbs :=3D k3-j784s4-evm.dtb \ k3-j784s4-evm-pcie0-pcie1-ep.dtbo k3-j784s4-evm-quad-port-eth-exp1-dtbs :=3D k3-j784s4-evm.dtb \ @@ -247,6 +250,7 @@ dtb- +=3D k3-am625-beagleplay-csi2-ov5640.dtb \ k3-j721e-sk-csi2-dual-imx219.dtb \ k3-j721s2-evm-pcie1-ep.dtb \ k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtb \ + k3-j722s-evm-csi2-quad-tevi-ov5640.dtb \ k3-j784s4-evm-pcie0-pcie1-ep.dtb \ k3-j784s4-evm-quad-port-eth-exp1.dtb \ k3-j784s4-evm-usxgmii-exp1-exp2.dtb diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm-csi2-quad-tevi-ov5640.dtso= b/arch/arm64/boot/dts/ti/k3-j722s-evm-csi2-quad-tevi-ov5640.dtso new file mode 100644 index 000000000000..f33f50465a07 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm-csi2-quad-tevi-ov5640.dtso @@ -0,0 +1,319 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * 4 x TEVI OV5640 MIPI Camera module on RPI camera connector. + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&{/} { + clk_ov5640_fixed: ov5640-xclk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <24000000>; + }; +}; + + +&main_pmx0 { + cam0_reset_pins_default: cam0-reset-pins-default { + pinctrl-single,pins =3D < + J722S_IOPAD(0x03c, PIN_OUTPUT, 7) + >; + }; + + cam1_reset_pins_default: cam1-reset-pins-default { + pinctrl-single,pins =3D < + J722S_IOPAD(0x044, PIN_OUTPUT, 7) + >; + }; + + cam2_reset_pins_default: cam2-reset-pins-default { + pinctrl-single,pins =3D < + J722S_IOPAD(0x04c, PIN_OUTPUT, 7) + >; + }; + + cam3_reset_pins_default: cam3-reset-pins-default { + pinctrl-single,pins =3D < + J722S_IOPAD(0x054, PIN_OUTPUT, 7) + >; + }; +}; + +&exp1 { + p06-hog{ + /* P06 - CSI01_MUX_SEL_2 */ + gpio-hog; + gpios =3D <6 GPIO_ACTIVE_HIGH>; + output-high; + line-name =3D "CSI01_MUX_SEL_2"; + }; + + p07-hog{ + /* P01 - CSI23_MUX_SEL_2 */ + gpio-hog; + gpios =3D <7 GPIO_ACTIVE_HIGH>; + output-high; + line-name =3D "CSI23_MUX_SEL_2"; + }; +}; + +&main_gpio0 { + p15-hog { + /* P15 - CSI2_CAMERA_GPIO1 */ + gpio-hog; + gpios =3D <15 GPIO_ACTIVE_HIGH>; + output-high; + line-name =3D "CSI2_CAMERA_GPIO1"; + }; + + p17-hog { + /* P17 - CSI2_CAMERA_GPIO2 */ + gpio-hog; + gpios =3D <17 GPIO_ACTIVE_HIGH>; + output-high; + line-name =3D "CSI2_CAMERA_GPIO2"; + }; + + p19-hog { + /* P19 - CSI2_CAMERA_GPIO3 */ + gpio-hog; + gpios =3D <19 GPIO_ACTIVE_HIGH>; + output-high; + line-name =3D "CSI2_CAMERA_GPIO3"; + }; + + p21-hog { + /* P21 - CSI2_CAMERA_GPIO4 */ + gpio-hog; + gpios =3D <21 GPIO_ACTIVE_HIGH>; + output-high; + line-name =3D "CSI2_CAMERA_GPIO4"; + }; +}; + +&pca9543_0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + + i2c-alias-pool =3D /bits/ 16 <0x3c 0x3d>; + + i2c@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + + ov5640_0: camera@3c { + compatible =3D "ovti,ov5640"; + reg =3D <0x3c>; + clocks =3D <&clk_ov5640_fixed>; + clock-names =3D "xclk"; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cam0_reset_pins_default>; + + port { + csi2_cam0: endpoint { + remote-endpoint =3D <&csi2rx0_in_sensor>; + clock-lanes =3D <0>; + data-lanes =3D <1 2>; + }; + }; + }; + }; + + i2c@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + + ov5640_1: camera@3c { + compatible =3D "ovti,ov5640"; + reg =3D <0x3c>; + clocks =3D <&clk_ov5640_fixed>; + clock-names =3D "xclk"; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cam1_reset_pins_default>; + + port { + csi2_cam1: endpoint { + remote-endpoint =3D <&csi2rx1_in_sensor>; + clock-lanes =3D <0>; + data-lanes =3D <1 2>; + }; + }; + }; + }; +}; + +&pca9543_1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + + i2c-alias-pool =3D /bits/ 16 <0x3c 0x3d>; + + i2c@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + + ov5640_2: camera@3c { + compatible =3D "ovti,ov5640"; + reg =3D <0x3c>; + clocks =3D <&clk_ov5640_fixed>; + clock-names =3D "xclk"; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cam2_reset_pins_default>; + + port { + csi2_cam2: endpoint { + remote-endpoint =3D <&csi2rx2_in_sensor>; + clock-lanes =3D <0>; + data-lanes =3D <1 2>; + }; + }; + }; + }; + + i2c@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + + ov5640_3: camera@3c { + compatible =3D "ovti,ov5640"; + reg =3D <0x3c>; + clocks =3D <&clk_ov5640_fixed>; + clock-names =3D "xclk"; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cam3_reset_pins_default>; + + port { + csi2_cam3: endpoint { + remote-endpoint =3D <&csi2rx3_in_sensor>; + clock-lanes =3D <0>; + data-lanes =3D <1 2>; + }; + }; + }; + }; +}; + +&cdns_csi2rx0 { + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + csi0_port0: port@0 { + reg =3D <0>; + status =3D "okay"; + + csi2rx0_in_sensor: endpoint { + remote-endpoint =3D <&csi2_cam0>; + bus-type =3D <4>; /* CSI2 DPHY */ + clock-lanes =3D <0>; + data-lanes =3D <1 2>; + }; + }; + }; +}; + +&cdns_csi2rx1 { + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + csi1_port0: port@0 { + reg =3D <0>; + status =3D "okay"; + + csi2rx1_in_sensor: endpoint { + remote-endpoint =3D <&csi2_cam1>; + bus-type =3D <4>; /* CSI2 DPHY */ + clock-lanes =3D <0>; + data-lanes =3D <1 2>; + }; + }; + }; +}; + +&cdns_csi2rx2 { + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + csi2_port0: port@0 { + reg =3D <0>; + status =3D "okay"; + + csi2rx2_in_sensor: endpoint { + remote-endpoint =3D <&csi2_cam2>; + bus-type =3D <4>; /* CSI2 DPHY */ + clock-lanes =3D <0>; + data-lanes =3D <1 2>; + }; + }; + }; +}; + +&cdns_csi2rx3 { + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + csi3_port0: port@0 { + reg =3D <0>; + status =3D "okay"; + + csi2rx3_in_sensor: endpoint { + remote-endpoint =3D <&csi2_cam3>; + bus-type =3D <4>; /* CSI2 DPHY */ + clock-lanes =3D <0>; + data-lanes =3D <1 2>; + }; + }; + }; +}; + +&ti_csi2rx0 { + status =3D "okay"; +}; + +&dphy0 { + status =3D "okay"; +}; + +&ti_csi2rx1 { + status =3D "okay"; +}; + +&dphy1 { + status =3D "okay"; +}; + + +&ti_csi2rx2 { + status =3D "okay"; +}; + +&dphy2 { + status =3D "okay"; +}; + + +&ti_csi2rx3 { + status =3D "okay"; +}; + +&dphy3 { + status =3D "okay"; +}; --=20 2.34.1