From nobody Fri Sep 5 22:31:41 2025 Received: from cpanel.siel.si (cpanel.siel.si [46.19.9.99]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 430A31DE2BC; Tue, 18 Feb 2025 07:42:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=46.19.9.99 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739864579; cv=none; b=aMP/wfXxuc4nXu9XMXqxlt15Eq2AGebOHyWDd6algK9XMxM+wmtitapWIXYIbS3fyiSFPhDJ0SErjX8o3WRJGp1MqggAWquuf6kysEAr4xkpn1CsPWWbvj7YPJjoCmXDVN744ZGsBRsgtCjNRCyJwQRL8e1tsESnZMBthj4nGE4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739864579; c=relaxed/simple; bh=181kaWNaGjBhyZTmRFrjgfsKp25rrab/bDDvrYVH/nA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=p7I5jcb5PLQlRDldCKLzpUMSa8DS9dhh9F93npd/f0BydT9RBFwHmKNRvlGw8NQqlu37QBrM/MVE1vbzEQTG8KEA3ZIpeIh86iZnUVOEKtq8addOT7Frhv/nzztQCl4LIjq/naPqU0B5U0GY87MeXEN0B9hChlmmPxG6oeL/ftU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=norik.com; spf=pass smtp.mailfrom=norik.com; arc=none smtp.client-ip=46.19.9.99 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=norik.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=norik.com Received: from 89-212-21-243.static.t-2.net ([89.212.21.243]:52604 helo=and-HP-Z4..) by cpanel.siel.si with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96.2) (envelope-from ) id 1tkIFt-00G0MD-0s; Tue, 18 Feb 2025 08:42:56 +0100 From: Andrej Picej To: shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, upstream@lists.phytec.de Subject: [PATCH v3 13/15] arm64: dts: imx8mm-phycore-som: Add overlay for rproc Date: Tue, 18 Feb 2025 08:41:54 +0100 Message-Id: <20250218074156.807214-14-andrej.picej@norik.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250218074156.807214-1-andrej.picej@norik.com> References: <20250218074156.807214-1-andrej.picej@norik.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - cpanel.siel.si X-AntiAbuse: Original Domain - vger.kernel.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - norik.com X-Get-Message-Sender-Via: cpanel.siel.si: authenticated_id: andrej.picej@norik.com X-Authenticated-Sender: cpanel.siel.si: andrej.picej@norik.com X-Source: X-Source-Args: X-Source-Dir: Content-Type: text/plain; charset="utf-8" From: Dominik Haller Adds a devicetree overlay containing reserved memory regions used for intercore communication between A53 and M4 cores. Signed-off-by: Dominik Haller Signed-off-by: Andrej Picej --- Changes in v3: - updated copyright year, - added address-cells and size-cells to the root node to fix a dts check warning. --- arch/arm64/boot/dts/freescale/Makefile | 2 + .../dts/freescale/imx8mm-phycore-rpmsg.dtso | 58 +++++++++++++++++++ 2 files changed, 60 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-phycore-rpmsg.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/f= reescale/Makefile index 7e0fef7ed9de..a10c8b5c2c4a 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -125,9 +125,11 @@ dtb-$(CONFIG_ARCH_MXC) +=3D imx8mm-phyboard-polis-rdk.= dtb =20 imx8mm-phyboard-polis-peb-av-10-dtbs +=3D imx8mm-phyboard-polis-rdk.dtb im= x8mm-phyboard-polis-peb-av-10.dtbo imx8mm-phyboard-polis-peb-eval-01-dtbs +=3D imx8mm-phyboard-polis-rdk.dtb = imx8mm-phyboard-polis-peb-eval-01.dtbo +imx8mm-phycore-rpmsg-dtbs +=3D imx8mm-phyboard-polis-rdk.dtb imx8mm-phycor= e-rpmsg.dtbo =20 dtb-$(CONFIG_ARCH_MXC) +=3D imx8mm-phyboard-polis-peb-av-10.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mm-phyboard-polis-peb-eval-01.dtb +dtb-$(CONFIG_ARCH_MXC) +=3D imx8mm-phycore-rpmsg.dtb =20 dtb-$(CONFIG_ARCH_MXC) +=3D imx8mm-phygate-tauri-l.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mm-prt8mm.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phycore-rpmsg.dtso b/arch= /arm64/boot/dts/freescale/imx8mm-phycore-rpmsg.dtso new file mode 100644 index 000000000000..43d5905f3d72 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-phycore-rpmsg.dtso @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + * Author: Dominik Haller + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + #address-cells =3D <2>; + #size-cells =3D <2>; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + m4_reserved: m4@80000000 { + reg =3D <0 0x80000000 0 0x1000000>; + no-map; + }; + + vdev0vring0: vdev0vring0@b8000000 { + reg =3D <0 0xb8000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@b8008000 { + reg =3D <0 0xb8008000 0 0x8000>; + no-map; + }; + + rsc_table: rsc_table@b80ff000 { + reg =3D <0 0xb80ff000 0 0x1000>; + no-map; + }; + + vdevbuffer: vdevbuffer@b8400000 { + compatible =3D "shared-dma-pool"; + reg =3D <0 0xb8400000 0 0x100000>; + no-map; + }; + }; + + core-m4 { + compatible =3D "fsl,imx8mm-cm4"; + clocks =3D <&clk IMX8MM_CLK_M4_DIV>; + mboxes =3D <&mu 0 1 + &mu 1 1 + &mu 3 1>; + mbox-names =3D "tx", "rx", "rxdb"; + memory-region =3D <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, <&rsc_t= able>; + syscon =3D <&src>; + }; +}; --=20 2.34.1