From nobody Fri Dec 19 09:12:13 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id B9ABA22B5A3; Mon, 17 Feb 2025 19:59:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739822363; cv=none; b=HCXqDWzmMhJQdAFd84BDcsIPkkIxe8XTuTCeFWFr7PPf2C/PufFPG4QTvaI5lvRkPJcXzsEpdt0Mb6PyDhKcJop0fIU3wYyyKwBLaaP8SfD4Iv/SPiIS42UzUANR3H+MeGZNil6uMwz3tbeZCj+o+lQtHGTjYTxYO7OqtoKsZ1E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739822363; c=relaxed/simple; bh=N3QnyXaL+LrGly7ui66XjpFf2/oiT1rSV8RLmeKWr5Y=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=kZAFVv9Pz9gZZ6RwDXGWrVZoHrMbo4Cx5UQX7eMwnni08VDYuWvMonENRErKl2SMA9kmaGNYilGQ2yJxaRXAk8BB3+xtFiCWYc+jp0GKmUgKK3CBfnpwr8CgXtdSW/+FZlV4k6f4jqzg0b4dRGR/51BwwQQFhAW5Vdgar9qRxpw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 07DE41692; Mon, 17 Feb 2025 11:59:40 -0800 (PST) Received: from e132581.cambridge.arm.com (e132581.arm.com [10.2.76.71]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 828623F6A8; Mon, 17 Feb 2025 11:59:18 -0800 (PST) From: Leo Yan To: Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , James Clark , Mike Leach , Mark Rutland , Alexander Shishkin , Jiri Olsa , Adrian Hunter , "Liang, Kan" , Will Deacon , Graham Woodward , Paschalis.Mpeis@arm.com, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Leo Yan Subject: [PATCH v3 01/12] perf script: Make printing flags reliable Date: Mon, 17 Feb 2025 19:58:57 +0000 Message-Id: <20250217195908.176207-2-leo.yan@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250217195908.176207-1-leo.yan@arm.com> References: <20250217195908.176207-1-leo.yan@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a check for the generated string of flags. Print out the raw number if the string generation fails. In another case, if the string length is longer than the aligned size, allow the completed string to be printed. Reviewed-by: Ian Rogers Reviewed-by: James Clark Signed-off-by: Leo Yan --- tools/perf/builtin-script.c | 10 ++++++++-- tools/perf/util/trace-event.h | 2 ++ 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/tools/perf/builtin-script.c b/tools/perf/builtin-script.c index d797cec4f054..2c4b1fb7dc72 100644 --- a/tools/perf/builtin-script.c +++ b/tools/perf/builtin-script.c @@ -1709,9 +1709,15 @@ static int perf_sample__fprintf_bts(struct perf_samp= le *sample, static int perf_sample__fprintf_flags(u32 flags, FILE *fp) { char str[SAMPLE_FLAGS_BUF_SIZE]; + int ret; + + ret =3D perf_sample__sprintf_flags(flags, str, sizeof(str)); + if (ret < 0) + return fprintf(fp, " raw flags:0x%-*x ", + SAMPLE_FLAGS_STR_ALIGNED_SIZE - 12, flags); =20 - perf_sample__sprintf_flags(flags, str, sizeof(str)); - return fprintf(fp, " %-21s ", str); + ret =3D max(ret, SAMPLE_FLAGS_STR_ALIGNED_SIZE); + return fprintf(fp, " %-*s ", ret, str); } =20 struct printer_data { diff --git a/tools/perf/util/trace-event.h b/tools/perf/util/trace-event.h index ac9fde2f980c..71e680bc3d4b 100644 --- a/tools/perf/util/trace-event.h +++ b/tools/perf/util/trace-event.h @@ -145,6 +145,8 @@ int common_flags(struct scripting_context *context); int common_lock_depth(struct scripting_context *context); =20 #define SAMPLE_FLAGS_BUF_SIZE 64 +#define SAMPLE_FLAGS_STR_ALIGNED_SIZE 21 + int perf_sample__sprintf_flags(u32 flags, char *str, size_t sz); =20 #if defined(LIBTRACEEVENT_VERSION) && LIBTRACEEVENT_VERSION >=3D MAKE_LIB= TRACEEVENT_VERSION(1, 5, 0) --=20 2.34.1 From nobody Fri Dec 19 09:12:13 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 63FE8238D54; Mon, 17 Feb 2025 19:59:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739822366; cv=none; b=dCOoiz9oaVN4eogolrjTac43CgACGdRKWNSRXELj8/51pczrQ/vEUGf+9rL9rznEMSkFpOv1id4XObDfk7U7z1kJKTZVDEVR8PU/ATmy20ZAGqqb+IMKateQUnaho35QpJtSiIRx/1Og6n2r4zDu6xFIM3TC/f/ic0btibbi5pg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739822366; c=relaxed/simple; bh=41epd4k4+JPTJYE9uKepUTs7bNrxzdsJTg5Bi8O2aFY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=bEIqvSBZxy4uhoYFVyk12q0UEPk85CAlBR8rYdAZ6O3mygX3QEC+PkjQooKDEuHIzAjAla4wbPADt9fkrcIu1iE/A/++A3AMSolMGB5vDai0rqu2J9W2LQ5rd7XDK5/Q82gRd18TlDkgNSViROcPKdfGFOSV7qLRO9Y4BM6ktNs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id AA1F6152B; Mon, 17 Feb 2025 11:59:42 -0800 (PST) Received: from e132581.cambridge.arm.com (e132581.arm.com [10.2.76.71]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 31A183F6A8; Mon, 17 Feb 2025 11:59:21 -0800 (PST) From: Leo Yan To: Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , James Clark , Mike Leach , Mark Rutland , Alexander Shishkin , Jiri Olsa , Adrian Hunter , "Liang, Kan" , Will Deacon , Graham Woodward , Paschalis.Mpeis@arm.com, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Leo Yan Subject: [PATCH v3 02/12] perf script: Refactor sample_flags_to_name() function Date: Mon, 17 Feb 2025 19:58:58 +0000 Message-Id: <20250217195908.176207-3-leo.yan@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250217195908.176207-1-leo.yan@arm.com> References: <20250217195908.176207-1-leo.yan@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When generating a string for sample flags, the sample_flags_to_name() function lacks the ability to parse the trace start bit or trace end bit. Therefore, the function is invoked multiple times after clearing its unsupported bits. This commit improves the sample_flags_to_name() function to parse sample flags in one go for three kinds of information: - The prefix info for trace start, trace end, etc. - Branch types. - Extra info for transaction and interrupt related info. As a result, the code is simplified to call the sample_flags_to_name() only once. No expectation for any changes in the perf script output. Reviewed-by: Ian Rogers Reviewed-by: James Clark Signed-off-by: Leo Yan --- tools/perf/util/event.h | 5 ++ tools/perf/util/trace-event-scripting.c | 85 ++++++++++++++++--------- 2 files changed, 59 insertions(+), 31 deletions(-) diff --git a/tools/perf/util/event.h b/tools/perf/util/event.h index 2744c54f404e..cd75efc09834 100644 --- a/tools/perf/util/event.h +++ b/tools/perf/util/event.h @@ -71,6 +71,11 @@ enum { =20 #define PERF_IP_FLAG_CHARS "bcrosyiABExghDt" =20 +#define PERF_ADDITIONAL_STATE_MASK \ + (PERF_IP_FLAG_IN_TX | \ + PERF_IP_FLAG_INTR_DISABLE | \ + PERF_IP_FLAG_INTR_TOGGLE) + #define PERF_BRANCH_MASK (\ PERF_IP_FLAG_BRANCH |\ PERF_IP_FLAG_CALL |\ diff --git a/tools/perf/util/trace-event-scripting.c b/tools/perf/util/trac= e-event-scripting.c index 4e81e02a4f18..712ba3a51bbe 100644 --- a/tools/perf/util/trace-event-scripting.c +++ b/tools/perf/util/trace-event-scripting.c @@ -313,49 +313,72 @@ static const struct { {0, NULL} }; =20 -static const char *sample_flags_to_name(u32 flags) +static int sample_flags_to_name(u32 flags, char *str, size_t size) { int i; - - for (i =3D 0; sample_flags[i].name ; i++) { - if (sample_flags[i].flags =3D=3D flags) - return sample_flags[i].name; + const char *prefix; + int pos =3D 0, ret; + u32 xf =3D flags & PERF_ADDITIONAL_STATE_MASK; + char xs[16] =3D { 0 }; + + /* Clear additional state bits */ + flags &=3D ~PERF_ADDITIONAL_STATE_MASK; + + if (flags & PERF_IP_FLAG_TRACE_BEGIN) + prefix =3D "tr strt "; + else if (flags & PERF_IP_FLAG_TRACE_END) + prefix =3D "tr end "; + else + prefix =3D ""; + + ret =3D snprintf(str + pos, size - pos, "%s", prefix); + if (ret < 0) + return ret; + pos +=3D ret; + + flags &=3D ~(PERF_IP_FLAG_TRACE_BEGIN | PERF_IP_FLAG_TRACE_END); + + for (i =3D 0; sample_flags[i].name; i++) { + if (sample_flags[i].flags !=3D flags) + continue; + + ret =3D snprintf(str + pos, size - pos, "%s", sample_flags[i].name); + if (ret < 0) + return ret; + pos +=3D ret; + break; } =20 - return NULL; + if (!xf) + return pos; + + snprintf(xs, sizeof(xs), "(%s%s%s)", + flags & PERF_IP_FLAG_IN_TX ? "x" : "", + flags & PERF_IP_FLAG_INTR_DISABLE ? "D" : "", + flags & PERF_IP_FLAG_INTR_TOGGLE ? "t" : ""); + + /* Right align the string if its length is less than the limit */ + if ((pos + strlen(xs)) < SAMPLE_FLAGS_STR_ALIGNED_SIZE) + ret =3D snprintf(str + pos, size - pos, "%*s", + (int)(SAMPLE_FLAGS_STR_ALIGNED_SIZE - ret), xs); + else + ret =3D snprintf(str + pos, size - pos, " %s", xs); + if (ret < 0) + return ret; + + return pos + ret; } =20 int perf_sample__sprintf_flags(u32 flags, char *str, size_t sz) { - u32 xf =3D PERF_IP_FLAG_IN_TX | PERF_IP_FLAG_INTR_DISABLE | - PERF_IP_FLAG_INTR_TOGGLE; const char *chars =3D PERF_IP_FLAG_CHARS; const size_t n =3D strlen(PERF_IP_FLAG_CHARS); - const char *name =3D NULL; size_t i, pos =3D 0; - char xs[16] =3D {0}; - - if (flags & xf) - snprintf(xs, sizeof(xs), "(%s%s%s)", - flags & PERF_IP_FLAG_IN_TX ? "x" : "", - flags & PERF_IP_FLAG_INTR_DISABLE ? "D" : "", - flags & PERF_IP_FLAG_INTR_TOGGLE ? "t" : ""); - - name =3D sample_flags_to_name(flags & ~xf); - if (name) - return snprintf(str, sz, "%-15s%6s", name, xs); - - if (flags & PERF_IP_FLAG_TRACE_BEGIN) { - name =3D sample_flags_to_name(flags & ~(xf | PERF_IP_FLAG_TRACE_BEGIN)); - if (name) - return snprintf(str, sz, "tr strt %-7s%6s", name, xs); - } + int ret; =20 - if (flags & PERF_IP_FLAG_TRACE_END) { - name =3D sample_flags_to_name(flags & ~(xf | PERF_IP_FLAG_TRACE_END)); - if (name) - return snprintf(str, sz, "tr end %-7s%6s", name, xs); - } + ret =3D sample_flags_to_name(flags, str, sz); + if (ret > 0) + return ret; =20 for (i =3D 0; i < n; i++, flags >>=3D 1) { if ((flags & 1) && pos < sz) --=20 2.34.1 From nobody Fri Dec 19 09:12:13 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 9B927239570; Mon, 17 Feb 2025 19:59:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739822368; cv=none; b=kK/B2VA78/c+1gaqh8427XL11YxEJFXFKLp9+Wk1gky86pYk9bI62OsedN60zyI81u4ZaAqY5DSmy1n+6h2bjFqXOPRE0+aJvXslog/eSKxcfmg5yz3DBQbGPtMYYoS/wLiOrEQq9Lt4tFEm1nzgUpeOMHpeHSQ/MYUEn4fhTcQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739822368; c=relaxed/simple; bh=/bzHaegk/WitL7gRtnefR4KYDpr12ID6MVZyPGJbb/E=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=IK56dXuaFxQrn8UyHmh8pkHJ2ghApnomiomkE4DsT39kMFPsrjIZ2CgvHfLB6qwJiPKO9q55vxmhsn1jnMlH/OWzq0McL1mnsw9gq4n/Ca0PDYpr/f0g0XM3rmikIM5DInjQenkV4QSHgdkXtCb0mHPTW7jkNk+K6Fwv22pH4bs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 57CB5152B; Mon, 17 Feb 2025 11:59:45 -0800 (PST) Received: from e132581.cambridge.arm.com (e132581.arm.com [10.2.76.71]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id D40643F6A8; Mon, 17 Feb 2025 11:59:23 -0800 (PST) From: Leo Yan To: Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , James Clark , Mike Leach , Mark Rutland , Alexander Shishkin , Jiri Olsa , Adrian Hunter , "Liang, Kan" , Will Deacon , Graham Woodward , Paschalis.Mpeis@arm.com, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Leo Yan Subject: [PATCH v3 03/12] perf script: Separate events from branch types Date: Mon, 17 Feb 2025 19:58:59 +0000 Message-Id: <20250217195908.176207-4-leo.yan@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250217195908.176207-1-leo.yan@arm.com> References: <20250217195908.176207-1-leo.yan@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Branch types and events are two different things. A branch type can be a conditional branch, an indirect branch, a procedure call, a return, or an exception taken, etc. The extra event information is provided for what happens during a branch, e.g. if a branch is mispredicted or not taken (specific to conditional branches). To deliver information about branches, this commit separates events from branch types. It parses branch types first, then appends event strings embraced by the '/' character. If multiple events occur, the events is separated with a comma (,). Also add a minor improvement by adding char 'm' in char array for branch mispredict event. Below are extracted sample flags. Before: branch: br miss instructions: br miss After: branch: jmp/miss/ instructions: jmp/miss/ Reviewed-by: Ian Rogers Reviewed-by: James Clark Signed-off-by: Leo Yan --- tools/perf/util/event.h | 5 +++- tools/perf/util/trace-event-scripting.c | 36 ++++++++++++++++++++++--- 2 files changed, 37 insertions(+), 4 deletions(-) diff --git a/tools/perf/util/event.h b/tools/perf/util/event.h index cd75efc09834..962fbc1714cf 100644 --- a/tools/perf/util/event.h +++ b/tools/perf/util/event.h @@ -69,7 +69,7 @@ enum { PERF_IP_FLAG_BRANCH_MISS =3D 1ULL << 15, }; =20 -#define PERF_IP_FLAG_CHARS "bcrosyiABExghDt" +#define PERF_IP_FLAG_CHARS "bcrosyiABExghDtm" =20 #define PERF_ADDITIONAL_STATE_MASK \ (PERF_IP_FLAG_IN_TX | \ @@ -90,6 +90,9 @@ enum { PERF_IP_FLAG_VMENTRY |\ PERF_IP_FLAG_VMEXIT) =20 +#define PERF_IP_FLAG_BRACH_EVENT_MASK \ + PERF_IP_FLAG_BRANCH_MISS + #define PERF_MEM_DATA_SRC_NONE \ (PERF_MEM_S(OP, NA) |\ PERF_MEM_S(LVL, NA) |\ diff --git a/tools/perf/util/trace-event-scripting.c b/tools/perf/util/trac= e-event-scripting.c index 712ba3a51bbe..55d7e4e612d5 100644 --- a/tools/perf/util/trace-event-scripting.c +++ b/tools/perf/util/trace-event-scripting.c @@ -309,7 +309,14 @@ static const struct { {PERF_IP_FLAG_BRANCH | PERF_IP_FLAG_TRACE_END, "tr end"}, {PERF_IP_FLAG_BRANCH | PERF_IP_FLAG_CALL | PERF_IP_FLAG_VMENTRY, "vmentry= "}, {PERF_IP_FLAG_BRANCH | PERF_IP_FLAG_CALL | PERF_IP_FLAG_VMEXIT, "vmexit"}, - {PERF_IP_FLAG_BRANCH | PERF_IP_FLAG_BRANCH_MISS, "br miss"}, + {0, NULL} +}; + +static const struct { + u32 flags; + const char *name; +} branch_events[] =3D { + {PERF_IP_FLAG_BRANCH_MISS, "miss"}, {0, NULL} }; =20 @@ -317,8 +324,9 @@ static int sample_flags_to_name(u32 flags, char *str, s= ize_t size) { int i; const char *prefix; - int pos =3D 0, ret; + int pos =3D 0, ret, ev_idx =3D 0; u32 xf =3D flags & PERF_ADDITIONAL_STATE_MASK; + u32 types, events; char xs[16] =3D { 0 }; =20 /* Clear additional state bits */ @@ -338,8 +346,9 @@ static int sample_flags_to_name(u32 flags, char *str, s= ize_t size) =20 flags &=3D ~(PERF_IP_FLAG_TRACE_BEGIN | PERF_IP_FLAG_TRACE_END); =20 + types =3D flags & ~PERF_IP_FLAG_BRACH_EVENT_MASK; for (i =3D 0; sample_flags[i].name; i++) { - if (sample_flags[i].flags !=3D flags) + if (sample_flags[i].flags !=3D types) continue; =20 ret =3D snprintf(str + pos, size - pos, "%s", sample_flags[i].name); @@ -349,6 +358,27 @@ static int sample_flags_to_name(u32 flags, char *str, = size_t size) break; } =20 + events =3D flags & PERF_IP_FLAG_BRACH_EVENT_MASK; + for (i =3D 0; branch_events[i].name; i++) { + if (!(branch_events[i].flags & events)) + continue; + + ret =3D snprintf(str + pos, size - pos, !ev_idx ? "/%s" : ",%s", + branch_events[i].name); + if (ret < 0) + return ret; + pos +=3D ret; + ev_idx++; + } + + /* Add an end character '/' for events */ + if (ev_idx) { + ret =3D snprintf(str + pos, size - pos, "/"); + if (ret < 0) + return ret; + pos +=3D ret; + } + if (!xf) return pos; =20 --=20 2.34.1 From nobody Fri Dec 19 09:12:13 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id A4980239578; Mon, 17 Feb 2025 19:59:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739822371; cv=none; b=bZ3h9oPz3Qytd0B1Cld/4/s1LkWwgc1jNwRb7ET7v9/rkAZPbZ0DuBlfgx4gRfyO4ZWamAlwk3t1JxWFbwAjjAXFsWh0nIgyK8y6JBXHoSX7RczvT1LkE33VxnLAswP9oehrBCW35v71goJNjm4sI9uO41CCvCWVjPaytwAdi4A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739822371; c=relaxed/simple; bh=Qh42oMYFXFD5ggPBjSt+TSYegIwWv0n+N1/9OzrBj5Y=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=PuGPiGTdQUIkvNqeiprHwuMSv8ihilPOTcHMvi44TOAnZV0HhOshThksiQCy3pgllX5mHOsBNqenvleli2tUENfhsGMsxvRAh+MurmuBhg8pFOZ958LvjASjy5VXkcQiRuIxJ+SRzK78vwWSQITtjVw4zrlHVXSyrsaV7dO3CYM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 059661692; Mon, 17 Feb 2025 11:59:48 -0800 (PST) Received: from e132581.cambridge.arm.com (e132581.arm.com [10.2.76.71]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 811CF3F6A8; Mon, 17 Feb 2025 11:59:26 -0800 (PST) From: Leo Yan To: Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , James Clark , Mike Leach , Mark Rutland , Alexander Shishkin , Jiri Olsa , Adrian Hunter , "Liang, Kan" , Will Deacon , Graham Woodward , Paschalis.Mpeis@arm.com, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Leo Yan Subject: [PATCH v3 04/12] perf script: Add not taken event for branches Date: Mon, 17 Feb 2025 19:59:00 +0000 Message-Id: <20250217195908.176207-5-leo.yan@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250217195908.176207-1-leo.yan@arm.com> References: <20250217195908.176207-1-leo.yan@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some hardware (e.g., Arm SPE) can trace the not taken event for branches. Add a flag for this event and support printing it. Reviewed-by: Ian Rogers Reviewed-by: James Clark Signed-off-by: Leo Yan --- tools/perf/util/event.h | 6 ++++-- tools/perf/util/trace-event-scripting.c | 1 + 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/tools/perf/util/event.h b/tools/perf/util/event.h index 962fbc1714cf..c7f4b4b841ca 100644 --- a/tools/perf/util/event.h +++ b/tools/perf/util/event.h @@ -67,9 +67,10 @@ enum { PERF_IP_FLAG_INTR_DISABLE =3D 1ULL << 13, PERF_IP_FLAG_INTR_TOGGLE =3D 1ULL << 14, PERF_IP_FLAG_BRANCH_MISS =3D 1ULL << 15, + PERF_IP_FLAG_NOT_TAKEN =3D 1ULL << 16, }; =20 -#define PERF_IP_FLAG_CHARS "bcrosyiABExghDtm" +#define PERF_IP_FLAG_CHARS "bcrosyiABExghDtmn" =20 #define PERF_ADDITIONAL_STATE_MASK \ (PERF_IP_FLAG_IN_TX | \ @@ -91,7 +92,8 @@ enum { PERF_IP_FLAG_VMEXIT) =20 #define PERF_IP_FLAG_BRACH_EVENT_MASK \ - PERF_IP_FLAG_BRANCH_MISS + (PERF_IP_FLAG_BRANCH_MISS | \ + PERF_IP_FLAG_NOT_TAKEN) =20 #define PERF_MEM_DATA_SRC_NONE \ (PERF_MEM_S(OP, NA) |\ diff --git a/tools/perf/util/trace-event-scripting.c b/tools/perf/util/trac= e-event-scripting.c index 55d7e4e612d5..29cc467be14a 100644 --- a/tools/perf/util/trace-event-scripting.c +++ b/tools/perf/util/trace-event-scripting.c @@ -317,6 +317,7 @@ static const struct { const char *name; } branch_events[] =3D { {PERF_IP_FLAG_BRANCH_MISS, "miss"}, + {PERF_IP_FLAG_NOT_TAKEN, "not_taken"}, {0, NULL} }; =20 --=20 2.34.1 From nobody Fri Dec 19 09:12:13 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 3CC0B23BFA3; Mon, 17 Feb 2025 19:59:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739822373; cv=none; b=G+U/xG4SMWI/6h6cTKY1B236pJrhTurvl0VlqIpjkWHPh6v+l8aP6q2cc2wxqKbSzRkkYJS4vNUlwLV09lnbekqx0AVvuCvirVeqcUQMKoVMzk/l/UEjrW4tRYzOcXhn9SPP0tTxbpLPudzjemj8n0rrB7EVyFf9fOAFUTnh9Vk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739822373; c=relaxed/simple; bh=uU3EuLZfN5DK1j7PmV2GtRBb+f0PWPjEbSeaJmQBwoQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=tv0k4C5G2/cbBtoKoHba522LJ5kIMlSogJw9b1YgGCXmEaYKfbHWskdWbDdQU5mR+Z35VNy1Gb9GbpWu+ogXEiRc8ej9CQTXPIdlAHXB5S4k5yJznNbnFGD+JOFps7/mPYqLRvdcb0Wi5f/GXiqJYQBy+02ZBZNLCUU0R9RClJI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A74D8152B; Mon, 17 Feb 2025 11:59:50 -0800 (PST) Received: from e132581.cambridge.arm.com (e132581.arm.com [10.2.76.71]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 2EE7D3F6A8; Mon, 17 Feb 2025 11:59:29 -0800 (PST) From: Leo Yan To: Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , James Clark , Mike Leach , Mark Rutland , Alexander Shishkin , Jiri Olsa , Adrian Hunter , "Liang, Kan" , Will Deacon , Graham Woodward , Paschalis.Mpeis@arm.com, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Leo Yan Subject: [PATCH v3 05/12] perf script: Add not taken event for branch stack Date: Mon, 17 Feb 2025 19:59:01 +0000 Message-Id: <20250217195908.176207-6-leo.yan@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250217195908.176207-1-leo.yan@arm.com> References: <20250217195908.176207-1-leo.yan@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The branch stack has an existed field for printing mispredict, extend the field for printing events and add support not-taken event. Reviewed-by: Ian Rogers Reviewed-by: James Clark Signed-off-by: Leo Yan --- tools/perf/builtin-script.c | 20 +++++++++++++------- tools/perf/util/branch.h | 3 ++- 2 files changed, 15 insertions(+), 8 deletions(-) diff --git a/tools/perf/builtin-script.c b/tools/perf/builtin-script.c index 2c4b1fb7dc72..43bf327bb72b 100644 --- a/tools/perf/builtin-script.c +++ b/tools/perf/builtin-script.c @@ -935,19 +935,25 @@ static int perf_sample__fprintf_start(struct perf_scr= ipt *script, return printed; } =20 -static inline char -mispred_str(struct branch_entry *br) +static inline size_t +bstack_event_str(struct branch_entry *br, char *buf, size_t sz) { - if (!(br->flags.mispred || br->flags.predicted)) - return '-'; + if (!(br->flags.mispred || br->flags.predicted || br->flags.not_taken)) + return snprintf(buf, sz, "-"); =20 - return br->flags.predicted ? 'P' : 'M'; + return snprintf(buf, sz, "%s%s", + br->flags.predicted ? "P" : "M", + br->flags.not_taken ? "N" : ""); } =20 static int print_bstack_flags(FILE *fp, struct branch_entry *br) { - return fprintf(fp, "/%c/%c/%c/%d/%s/%s ", - mispred_str(br), + char events[16] =3D { 0 }; + size_t pos; + + pos =3D bstack_event_str(br, events, sizeof(events)); + return fprintf(fp, "/%s/%c/%c/%d/%s/%s ", + pos < 0 ? "-" : events, br->flags.in_tx ? 'X' : '-', br->flags.abort ? 'A' : '-', br->flags.cycles, diff --git a/tools/perf/util/branch.h b/tools/perf/util/branch.h index b80c12c74bbb..7429530fa774 100644 --- a/tools/perf/util/branch.h +++ b/tools/perf/util/branch.h @@ -25,7 +25,8 @@ struct branch_flags { u64 spec:2; u64 new_type:4; u64 priv:3; - u64 reserved:31; + u64 not_taken:1; + u64 reserved:30; }; }; }; --=20 2.34.1 From nobody Fri Dec 19 09:12:13 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D4CFA23C8AD; Mon, 17 Feb 2025 19:59:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739822376; cv=none; b=Zt5x+fn2bWWxR7fQXbE/9kcE/HmEXPlYYEZRxZWQnK/dhXb05dvQWgRfWRA5DD2jrQlsnoEHf9uJ7o873dkPiftDVB8svXGWBsWN8PrwykCSgoUVRqo3BH7j31AXpdbonDsGPcDOJ/2iml1W9aTifIYRJDwRvmNQPfNnl/S1A+M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739822376; c=relaxed/simple; bh=BWuAcsNBTw4pRqVuUJk51mAjNVUbrJpBjXxGGaV96Es=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=OSMTG2HzluBRnOHWjrLxuadgVcJirzIWJ6eel9Va2Z6J1SQGd0OZXCNSpZXuEc6BYj2SiFN6dUhpG+rdEIPQS4SjMXAyFN/CTHTKxxcYy2qgJLYjYdAstGJlsPmSNsuzIR8bY2uDjq7o8D9lw14xqGBC8uOX4BFiid5ylN9WcKE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 55125152B; Mon, 17 Feb 2025 11:59:53 -0800 (PST) Received: from e132581.cambridge.arm.com (e132581.arm.com [10.2.76.71]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id D0D193F6A8; Mon, 17 Feb 2025 11:59:31 -0800 (PST) From: Leo Yan To: Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , James Clark , Mike Leach , Mark Rutland , Alexander Shishkin , Jiri Olsa , Adrian Hunter , "Liang, Kan" , Will Deacon , Graham Woodward , Paschalis.Mpeis@arm.com, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Leo Yan Subject: [PATCH v3 06/12] perf arm-spe: Fix load-store operation checking Date: Mon, 17 Feb 2025 19:59:02 +0000 Message-Id: <20250217195908.176207-7-leo.yan@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250217195908.176207-1-leo.yan@arm.com> References: <20250217195908.176207-1-leo.yan@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The ARM_SPE_OP_LD and ARM_SPE_OP_ST operations are secondary operation type, they are overlapping with other second level's operation types belonging to SVE and branch operations. As a result, a non load-store operation can be parsed for data source and memory sample. To fix the issue, this commit introduces a is_ldst_op() macro for checking LDST operation, and apply the checking when synthesize data source and memory samples. Fixes: a89dbc9b988f ("perf arm-spe: Set sample's data source field") Signed-off-by: Leo Yan Reviewed-by: James Clark --- tools/perf/util/arm-spe.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c index 251d214adf7f..0e8e05c87fd7 100644 --- a/tools/perf/util/arm-spe.c +++ b/tools/perf/util/arm-spe.c @@ -37,6 +37,8 @@ #include "../../arch/arm64/include/asm/cputype.h" #define MAX_TIMESTAMP (~0ULL) =20 +#define is_ldst_op(op) (!!((op) & ARM_SPE_OP_LDST)) + struct arm_spe { struct auxtrace auxtrace; struct auxtrace_queues queues; @@ -681,6 +683,10 @@ static u64 arm_spe__synth_data_source(struct arm_spe_q= ueue *speq, { union perf_mem_data_src data_src =3D { .mem_op =3D PERF_MEM_OP_NA }; =20 + /* Only synthesize data source for LDST operations */ + if (!is_ldst_op(record->op)) + return 0; + if (record->op & ARM_SPE_OP_LD) data_src.mem_op =3D PERF_MEM_OP_LOAD; else if (record->op & ARM_SPE_OP_ST) @@ -779,7 +785,7 @@ static int arm_spe_sample(struct arm_spe_queue *speq) * When data_src is zero it means the record is not a memory operation, * skip to synthesize memory sample for this case. */ - if (spe->sample_memory && data_src) { + if (spe->sample_memory && is_ldst_op(record->op)) { err =3D arm_spe__synth_mem_sample(speq, spe->memory_id, data_src); if (err) return err; --=20 2.34.1 From nobody Fri Dec 19 09:12:13 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 9E78523C8C9; Mon, 17 Feb 2025 19:59:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739822379; cv=none; b=NWIZ23TOQfPgUKgpDi5d+jEEGAVxx/0kMaoLCnG4WJnUiyKNccGn5ptGXFF7MbnomGv0ae5YMB7Hp4WXNLwdz0QjbO+WtyBmif7GSvV/xV4nQ2s+Tqz14v7gbIfuFcRmgAWFvunco9SFYYbIxllRet0zwMpJwBxBYkq3gbNFnME= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739822379; c=relaxed/simple; bh=w8c5p/0eH9XySzVR5LkRGe//0ZjFFicuESB+QRP+4+8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=rG3IHFfxCURewBQXh57T0dE88g3h7EDeWV9MrphW0IYy9nZ0m7TWOMw4V9huEr+m7SoyXWCaVjtZsaDcJmOIHgTF+NkYpReZkV19JrMxBuqsXf3onzYG838a0Syqw1xbIK6OIME4pBPeSWIX+q13qRdzW0qSvtzg9CkB0XUuYu0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 025A4152B; Mon, 17 Feb 2025 11:59:56 -0800 (PST) Received: from e132581.cambridge.arm.com (e132581.arm.com [10.2.76.71]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 7E73A3F6A8; Mon, 17 Feb 2025 11:59:34 -0800 (PST) From: Leo Yan To: Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , James Clark , Mike Leach , Mark Rutland , Alexander Shishkin , Jiri Olsa , Adrian Hunter , "Liang, Kan" , Will Deacon , Graham Woodward , Paschalis.Mpeis@arm.com, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Leo Yan Subject: [PATCH v3 07/12] perf arm-spe: Extend branch operations Date: Mon, 17 Feb 2025 19:59:03 +0000 Message-Id: <20250217195908.176207-8-leo.yan@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250217195908.176207-1-leo.yan@arm.com> References: <20250217195908.176207-1-leo.yan@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In Arm ARM (ARM DDI 0487, L.a), the section "D18.2.7 Operation Type packet", the branch subclass is extended for Call Return (CR), Guarded control stack data access (GCS). This commit adds support CR and GCS operations. The IND (indirect) operation is defined only in bit [1], its macro is updated accordingly. Move the COND (Conditional) macro into the same group with other operations for better maintenance. Reviewed-by: Ian Rogers Reviewed-by: James Clark Signed-off-by: Leo Yan --- .../perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c | 12 +++++++++--- .../perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h | 11 ++++++++--- 2 files changed, 17 insertions(+), 6 deletions(-) diff --git a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c b/tools/= perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c index 4cef10a83962..625834da7e20 100644 --- a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c +++ b/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c @@ -397,10 +397,16 @@ static int arm_spe_pkt_desc_op_type(const struct arm_= spe_pkt *packet, =20 if (payload & SPE_OP_PKT_COND) arm_spe_pkt_out_string(&err, &buf, &buf_len, " COND"); - - if (SPE_OP_PKT_IS_INDIRECT_BRANCH(payload)) + if (payload & SPE_OP_PKT_INDIRECT_BRANCH) arm_spe_pkt_out_string(&err, &buf, &buf_len, " IND"); - + if (payload & SPE_OP_PKT_GCS) + arm_spe_pkt_out_string(&err, &buf, &buf_len, " GCS"); + if (SPE_OP_PKT_CR_BL(payload)) + arm_spe_pkt_out_string(&err, &buf, &buf_len, " CR-BL"); + if (SPE_OP_PKT_CR_RET(payload)) + arm_spe_pkt_out_string(&err, &buf, &buf_len, " CR-RET"); + if (SPE_OP_PKT_CR_NON_BL_RET(payload)) + arm_spe_pkt_out_string(&err, &buf, &buf_len, " CR-NON-BL-RET"); break; default: /* Unknown index */ diff --git a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h b/tools/= perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h index 464a912b221c..32d760ede701 100644 --- a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h +++ b/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h @@ -7,6 +7,7 @@ #ifndef INCLUDE__ARM_SPE_PKT_DECODER_H__ #define INCLUDE__ARM_SPE_PKT_DECODER_H__ =20 +#include #include #include =20 @@ -116,8 +117,6 @@ enum arm_spe_events { =20 #define SPE_OP_PKT_IS_OTHER_SVE_OP(v) (((v) & (BIT(7) | BIT(3) | BIT(0)))= =3D=3D 0x8) =20 -#define SPE_OP_PKT_COND BIT(0) - #define SPE_OP_PKT_LDST_SUBCLASS_GET(v) ((v) & GENMASK_ULL(7, 1)) #define SPE_OP_PKT_LDST_SUBCLASS_GP_REG 0x0 #define SPE_OP_PKT_LDST_SUBCLASS_SIMD_FP 0x4 @@ -148,7 +147,13 @@ enum arm_spe_events { #define SPE_OP_PKT_SVE_PRED BIT(2) #define SPE_OP_PKT_SVE_FP BIT(1) =20 -#define SPE_OP_PKT_IS_INDIRECT_BRANCH(v) (((v) & GENMASK_ULL(7, 1)) =3D=3D= 0x2) +#define SPE_OP_PKT_CR_MASK GENMASK_ULL(4, 3) +#define SPE_OP_PKT_CR_BL(v) (FIELD_GET(SPE_OP_PKT_CR_MASK, (v)) =3D=3D 1) +#define SPE_OP_PKT_CR_RET(v) (FIELD_GET(SPE_OP_PKT_CR_MASK, (v)) =3D=3D = 2) +#define SPE_OP_PKT_CR_NON_BL_RET(v) (FIELD_GET(SPE_OP_PKT_CR_MASK, (v)) = =3D=3D 3) +#define SPE_OP_PKT_GCS BIT(2) +#define SPE_OP_PKT_INDIRECT_BRANCH BIT(1) +#define SPE_OP_PKT_COND BIT(0) =20 const char *arm_spe_pkt_name(enum arm_spe_pkt_type); =20 --=20 2.34.1 From nobody Fri Dec 19 09:12:13 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id DCD2D23C8D9; Mon, 17 Feb 2025 19:59:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739822381; cv=none; b=kznQL3Jt/ZaqxC3rJq955J++vgujm9Ozt1v+OUpSb9nBzzWsBWTB6eC84URI1o+KTBdKoxNfEqJTzx2F7ICteWQrLln3Ww7cFDWxVOqfZQBrLvDwSVEs8gZ/b3hnNCuhG6ChQjCMKTPDybUQi0TYCcEvwMX0PllTalSKelJfJo0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739822381; c=relaxed/simple; bh=CrnV5bWVV2l2BqmcATUoCHtkREJf4AsKQ1zaxNHeeCc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=d+hsS5qAFSdC1XAYE4gPgmiV6lmtOENpmRxdw7Q0gKbgYOLnvl63HMWnrC0A44oXv0V6DV18OLwsaasqpgP+rzhGJPef4WAJMOh4aLLZVk8jLtTL3G8+kxiR6EX9qWSFsyXPQpAmaJbFQpEuKDFZ1dDqGapu2QeSx75xBSpE8N4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A44A6152B; Mon, 17 Feb 2025 11:59:58 -0800 (PST) Received: from e132581.cambridge.arm.com (e132581.arm.com [10.2.76.71]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 2BD4A3F6A8; Mon, 17 Feb 2025 11:59:37 -0800 (PST) From: Leo Yan To: Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , James Clark , Mike Leach , Mark Rutland , Alexander Shishkin , Jiri Olsa , Adrian Hunter , "Liang, Kan" , Will Deacon , Graham Woodward , Paschalis.Mpeis@arm.com, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Leo Yan Subject: [PATCH v3 08/12] perf arm-spe: Decode transactional event Date: Mon, 17 Feb 2025 19:59:04 +0000 Message-Id: <20250217195908.176207-9-leo.yan@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250217195908.176207-1-leo.yan@arm.com> References: <20250217195908.176207-1-leo.yan@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The bit[16] in an event payload indicates an operation is in transactional state. Decode the bit. Reviewed-by: Ian Rogers Reviewed-by: James Clark Signed-off-by: Leo Yan --- tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c | 2 ++ tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h | 1 + 2 files changed, 3 insertions(+) diff --git a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c b/tools/= perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c index 625834da7e20..13cadb2f1cea 100644 --- a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c +++ b/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c @@ -308,6 +308,8 @@ static int arm_spe_pkt_desc_event(const struct arm_spe_= pkt *packet, arm_spe_pkt_out_string(&err, &buf, &buf_len, " REMOTE-ACCESS"); if (payload & BIT(EV_ALIGNMENT)) arm_spe_pkt_out_string(&err, &buf, &buf_len, " ALIGNMENT"); + if (payload & BIT(EV_TRANSACTIONAL)) + arm_spe_pkt_out_string(&err, &buf, &buf_len, " TXN"); if (payload & BIT(EV_PARTIAL_PREDICATE)) arm_spe_pkt_out_string(&err, &buf, &buf_len, " SVE-PARTIAL-PRED"); if (payload & BIT(EV_EMPTY_PREDICATE)) diff --git a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h b/tools/= perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h index 32d760ede701..2cdf9f6da268 100644 --- a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h +++ b/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h @@ -105,6 +105,7 @@ enum arm_spe_events { EV_LLC_MISS =3D 9, EV_REMOTE_ACCESS =3D 10, EV_ALIGNMENT =3D 11, + EV_TRANSACTIONAL =3D 16, EV_PARTIAL_PREDICATE =3D 17, EV_EMPTY_PREDICATE =3D 18, }; --=20 2.34.1 From nobody Fri Dec 19 09:12:13 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D557523ED62; Mon, 17 Feb 2025 19:59:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739822384; cv=none; b=h7/+u/5Zlz5AimgtvA54slWLYcJ3o9KEU8AsaCNsbXJArjB8lQicawZtDGd3R+0NQAER37i0CMHsvQWKm4el2ynQbYUnmxcUNwkJZt21dGhMRlenaXuaKpEUyvq0sZ69M4bu10Ep1NpuIrguea7SP2Pldgyz7rpPlCfIgcjYuck= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739822384; c=relaxed/simple; bh=jnuiUq48AE2Cj9DM/fpwvDRM6qTOxoMjsaeMWefoo1Y=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=lGoM798J7ygXiRn1naObJMfzCZlpnOob/wiucTFee4eP8nUR8rV41pnOINUTO9tuD2DaLZ2UbuRuLKm7/255fLRlVoQ8ZQ7Q04te+L2Wb11etih1GwWzgIXI0yHkVXTieUq6EEkXxD1iA5KmOIhgkFd88sFtSx1UHPu/+kWCPtM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5148D152B; Mon, 17 Feb 2025 12:00:01 -0800 (PST) Received: from e132581.cambridge.arm.com (e132581.arm.com [10.2.76.71]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id CD0F13F6A8; Mon, 17 Feb 2025 11:59:39 -0800 (PST) From: Leo Yan To: Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , James Clark , Mike Leach , Mark Rutland , Alexander Shishkin , Jiri Olsa , Adrian Hunter , "Liang, Kan" , Will Deacon , Graham Woodward , Paschalis.Mpeis@arm.com, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Leo Yan Subject: [PATCH v3 09/12] perf arm-spe: Fill branch operations and events to record Date: Mon, 17 Feb 2025 19:59:05 +0000 Message-Id: <20250217195908.176207-10-leo.yan@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250217195908.176207-1-leo.yan@arm.com> References: <20250217195908.176207-1-leo.yan@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The new added branch operations and events are filled into record, the information will be consumed when synthesizing samples. Reviewed-by: Ian Rogers Reviewed-by: James Clark Signed-off-by: Leo Yan --- .../util/arm-spe-decoder/arm-spe-decoder.c | 18 ++++++++++++++++++ .../util/arm-spe-decoder/arm-spe-decoder.h | 10 ++++++++-- 2 files changed, 26 insertions(+), 2 deletions(-) diff --git a/tools/perf/util/arm-spe-decoder/arm-spe-decoder.c b/tools/perf= /util/arm-spe-decoder/arm-spe-decoder.c index ba807071d3c1..52bd0a4ea96d 100644 --- a/tools/perf/util/arm-spe-decoder/arm-spe-decoder.c +++ b/tools/perf/util/arm-spe-decoder/arm-spe-decoder.c @@ -207,6 +207,18 @@ static int arm_spe_read_record(struct arm_spe_decoder = *decoder) break; case SPE_OP_PKT_HDR_CLASS_BR_ERET: decoder->record.op |=3D ARM_SPE_OP_BRANCH_ERET; + if (payload & SPE_OP_PKT_COND) + decoder->record.op |=3D ARM_SPE_OP_BR_COND; + if (payload & SPE_OP_PKT_INDIRECT_BRANCH) + decoder->record.op |=3D ARM_SPE_OP_BR_INDIRECT; + if (payload & SPE_OP_PKT_GCS) + decoder->record.op |=3D ARM_SPE_OP_BR_GCS; + if (SPE_OP_PKT_CR_BL(payload)) + decoder->record.op |=3D ARM_SPE_OP_BR_CR_BL; + if (SPE_OP_PKT_CR_RET(payload)) + decoder->record.op |=3D ARM_SPE_OP_BR_CR_RET; + if (SPE_OP_PKT_CR_NON_BL_RET(payload)) + decoder->record.op |=3D ARM_SPE_OP_BR_CR_NON_BL_RET; break; default: pr_err("Get packet error!\n"); @@ -238,6 +250,12 @@ static int arm_spe_read_record(struct arm_spe_decoder = *decoder) if (payload & BIT(EV_MISPRED)) decoder->record.type |=3D ARM_SPE_BRANCH_MISS; =20 + if (payload & BIT(EV_NOT_TAKEN)) + decoder->record.type |=3D ARM_SPE_BRANCH_NOT_TAKEN; + + if (payload & BIT(EV_TRANSACTIONAL)) + decoder->record.type |=3D ARM_SPE_IN_TXN; + if (payload & BIT(EV_PARTIAL_PREDICATE)) decoder->record.type |=3D ARM_SPE_SVE_PARTIAL_PRED; =20 diff --git a/tools/perf/util/arm-spe-decoder/arm-spe-decoder.h b/tools/perf= /util/arm-spe-decoder/arm-spe-decoder.h index 4bcd627e859f..85b688a97436 100644 --- a/tools/perf/util/arm-spe-decoder/arm-spe-decoder.h +++ b/tools/perf/util/arm-spe-decoder/arm-spe-decoder.h @@ -24,6 +24,8 @@ enum arm_spe_sample_type { ARM_SPE_REMOTE_ACCESS =3D 1 << 7, ARM_SPE_SVE_PARTIAL_PRED =3D 1 << 8, ARM_SPE_SVE_EMPTY_PRED =3D 1 << 9, + ARM_SPE_BRANCH_NOT_TAKEN =3D 1 << 10, + ARM_SPE_IN_TXN =3D 1 << 11, }; =20 enum arm_spe_op_type { @@ -52,8 +54,12 @@ enum arm_spe_op_type { ARM_SPE_OP_SVE_SG =3D 1 << 27, =20 /* Second level operation type for BRANCH_ERET */ - ARM_SPE_OP_BR_COND =3D 1 << 16, - ARM_SPE_OP_BR_INDIRECT =3D 1 << 17, + ARM_SPE_OP_BR_COND =3D 1 << 16, + ARM_SPE_OP_BR_INDIRECT =3D 1 << 17, + ARM_SPE_OP_BR_GCS =3D 1 << 18, + ARM_SPE_OP_BR_CR_BL =3D 1 << 19, + ARM_SPE_OP_BR_CR_RET =3D 1 << 20, + ARM_SPE_OP_BR_CR_NON_BL_RET =3D 1 << 21, }; =20 enum arm_spe_common_data_source { --=20 2.34.1 From nobody Fri Dec 19 09:12:13 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 3526823ED70; Mon, 17 Feb 2025 19:59:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739822386; cv=none; b=h8NoKzh51bCGKBAhWh0JthlVUB3EOzUCPZQxKBv88OAEt/Ho4yJzMo6ROQrVJaI8wMnLbeUBT8YbQkdjyykegYYiUUaoqKfpWM2+0rcmhwg5mVykemuolGhTlNkvwEhYFAEcaDD6Qf/CnE5xheGVWTWoS1+NK7uvelalvK2XnRs= ARC-Message-Signature: i=1; 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Mon, 17 Feb 2025 11:59:42 -0800 (PST) From: Leo Yan To: Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , James Clark , Mike Leach , Mark Rutland , Alexander Shishkin , Jiri Olsa , Adrian Hunter , "Liang, Kan" , Will Deacon , Graham Woodward , Paschalis.Mpeis@arm.com, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Leo Yan Subject: [PATCH v3 10/12] perf arm-spe: Set sample flags with supplement info Date: Mon, 17 Feb 2025 19:59:06 +0000 Message-Id: <20250217195908.176207-11-leo.yan@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250217195908.176207-1-leo.yan@arm.com> References: <20250217195908.176207-1-leo.yan@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Based on the supplement information in the record, this commit sets the sample flags for conditional branch, function call, return. It also sets events in flags, such as mispredict, not taken, and in transaction. Reviewed-by: Ian Rogers Reviewed-by: James Clark Signed-off-by: Leo Yan --- tools/perf/util/arm-spe.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c index 0e8e05c87fd7..daecf9e1017a 100644 --- a/tools/perf/util/arm-spe.c +++ b/tools/perf/util/arm-spe.c @@ -484,6 +484,26 @@ static void arm_spe__sample_flags(struct arm_spe_queue= *speq) =20 if (record->type & ARM_SPE_BRANCH_MISS) speq->flags |=3D PERF_IP_FLAG_BRANCH_MISS; + + if (record->type & ARM_SPE_BRANCH_NOT_TAKEN) + speq->flags |=3D PERF_IP_FLAG_NOT_TAKEN; + + if (record->type & ARM_SPE_IN_TXN) + speq->flags |=3D PERF_IP_FLAG_IN_TX; + + if (record->op & ARM_SPE_OP_BR_COND) + speq->flags |=3D PERF_IP_FLAG_CONDITIONAL; + + if (record->op & ARM_SPE_OP_BR_CR_BL) + speq->flags |=3D PERF_IP_FLAG_CALL; + else if (record->op & ARM_SPE_OP_BR_CR_RET) + speq->flags |=3D PERF_IP_FLAG_RETURN; + /* + * Indirect branch instruction without link (e.g. BR), + * take it as a function return. + */ + else if (record->op & ARM_SPE_OP_BR_INDIRECT) + speq->flags |=3D PERF_IP_FLAG_RETURN; } } =20 --=20 2.34.1 From nobody Fri Dec 19 09:12:13 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D7B5F23F295; Mon, 17 Feb 2025 19:59:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739822389; cv=none; b=CvfiEGKg36yjwoxHE2aZZnHV8vxtIfOkz/bQRf4HvCrAcQ/WXTm80FNUlgNc+6Z6LW92pWE9NTd1vC1LjUvo/zPlrSZ5iw97qJjyBYY5EToGsGoIoGXerlF2ZMJI1msc/JOZUmkL6Cd4KtH0ASnjsR+MrfROxhg8GzhfjEiwYQs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739822389; c=relaxed/simple; bh=UsyBwrJV9wFy95Fj5nIBK4fL8yenb7w/Ki9AmRJ2tsU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=K9O+lOdv5ydpk44HihAxNs9zQ2JEei8IA8qzZ+sgqIvd1K3QJxA9MZmL/ZFSNIx4XNo1JxDgF2oCvT0mStdqucMGkot7ooXphY2AcosKUYprWoYFxUjb2LjO1Jb+xcZU6oDYCBNy5ZFtsKVkyNJUqHev3rhxJilxvtFkVyVO+sU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A154D152B; Mon, 17 Feb 2025 12:00:06 -0800 (PST) Received: from e132581.cambridge.arm.com (e132581.arm.com [10.2.76.71]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 28E453F6A8; Mon, 17 Feb 2025 11:59:45 -0800 (PST) From: Leo Yan To: Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , James Clark , Mike Leach , Mark Rutland , Alexander Shishkin , Jiri Olsa , Adrian Hunter , "Liang, Kan" , Will Deacon , Graham Woodward , Paschalis.Mpeis@arm.com, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Leo Yan Subject: [PATCH v3 11/12] perf arm-spe: Add branch stack Date: Mon, 17 Feb 2025 19:59:07 +0000 Message-Id: <20250217195908.176207-12-leo.yan@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250217195908.176207-1-leo.yan@arm.com> References: <20250217195908.176207-1-leo.yan@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Although Arm SPE cannot generate continuous branch records, this commit creates a branch stack with only one branch entry. A single branch info can be used for performance optimization. A branch stack structure is dynamically allocated in the decode queue. The branch stack and stack flags are synthesized based on branch types and associated events. After: # perf script --itrace=3Dbl1 -F flags,addr,brstack jcc ffffc0fad9c6b214 0xffffc0fad9c6b234/0xffffc0fad9c6b= 214/P/-/-/7/COND/- jcc/miss,not_taken/ ffffc0fadaaebb30 0xffffc0fadaaebb2c/0xffffc0fadaaeb= b30/MN/-/-/7/COND/- jmp ffffc0fadaaea358 0xffffc0fadaaea5ec/0xffffc0fadaaea= 358/P/-/-/5//- jcc/not_taken/ ffffc0fadaae6494 0xffffc0fadaae6490/0xffffc0fadaae6= 494/PN/-/-/11/COND/- jcc/not_taken/ ffff7f83ab54 0xffff7f83ab50/0xffff7f83ab54/PN/-= /-/13/COND/- jcc/not_taken/ ffff7f83ab08 0xffff7f83ab04/0xffff7f83ab08/PN/-= /-/8/COND/- jcc ffff7f83aa80 0xffff7f83aa58/0xffff7f83aa80/P/-/= -/10/COND/- jcc ffff7f9a45d0 0xffff7f9a43f0/0xffff7f9a45d0/P/-/= -/29/COND/- jcc/not_taken/ ffffc0fad9ba6db4 0xffffc0fad9ba6db0/0xffffc0fad9ba6= db4/PN/-/-/44/COND/- jcc ffffc0fadaac2964 0xffffc0fadaac2970/0xffffc0fadaac2= 964/P/-/-/6/COND/- jcc ffffc0fad99ddc10 0xffffc0fad99ddc04/0xffffc0fad99dd= c10/P/-/-/72/COND/- jcc/not_taken/ ffffc0fad9b3f21c 0xffffc0fad9b3f218/0xffffc0fad9b3f= 21c/PN/-/-/64/COND/- jcc ffffc0fad9c3b604 0xffffc0fad9c3b5f8/0xffffc0fad9c3b= 604/P/-/-/13/COND/- jcc ffffc0fadaad6048 0xffffc0fadaad5f8c/0xffffc0fadaad6= 048/P/-/-/5/COND/- return/miss/ ffff7f84e614 0xffffc0fad98a2274/0xffff7f84e614/= M/-/-/13/RET/- jcc/not_taken/ ffffc0fadaac4eb4 0xffffc0fadaac4eb0/0xffffc0fadaac4= eb4/PN/-/-/5/COND/- jmp ffff7f8e3130 0xffff7f87555c/0xffff7f8e3130/P/-/= -/5//- jcc/not_taken/ ffffc0fad9b3d9b0 0xffffc0fad9b3d9ac/0xffffc0fad9b3d= 9b0/PN/-/-/14/COND/- return ffffc0fad9b91950 0xffffc0fad98c3e28/0xffffc0fad9b91= 950/P/-/-/12/RET/- Reviewed-by: Ian Rogers Reviewed-by: James Clark Signed-off-by: Leo Yan --- tools/perf/util/arm-spe.c | 99 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 99 insertions(+) diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c index daecf9e1017a..ed89b7dbc244 100644 --- a/tools/perf/util/arm-spe.c +++ b/tools/perf/util/arm-spe.c @@ -103,6 +103,7 @@ struct arm_spe_queue { struct thread *thread; u64 period_instructions; u32 flags; + struct branch_stack *last_branch; }; =20 struct data_source_handle { @@ -233,6 +234,16 @@ static struct arm_spe_queue *arm_spe__alloc_queue(stru= ct arm_spe *spe, params.get_trace =3D arm_spe_get_trace; params.data =3D speq; =20 + if (spe->synth_opts.last_branch) { + size_t sz =3D sizeof(struct branch_stack); + + /* Allocate one entry for TGT */ + sz +=3D sizeof(struct branch_entry); + speq->last_branch =3D zalloc(sz); + if (!speq->last_branch) + goto out_free; + } + /* create new decoder */ speq->decoder =3D arm_spe_decoder_new(¶ms); if (!speq->decoder) @@ -242,6 +253,7 @@ static struct arm_spe_queue *arm_spe__alloc_queue(struc= t arm_spe *spe, =20 out_free: zfree(&speq->event_buf); + zfree(&speq->last_branch); free(speq); =20 return NULL; @@ -348,6 +360,73 @@ static void arm_spe_prep_sample(struct arm_spe *spe, event->sample.header.size =3D sizeof(struct perf_event_header); } =20 +static void arm_spe__prep_branch_stack(struct arm_spe_queue *speq) +{ + struct arm_spe_record *record =3D &speq->decoder->record; + struct branch_stack *bstack =3D speq->last_branch; + struct branch_flags *bs_flags; + size_t sz =3D sizeof(struct branch_stack) + + sizeof(struct branch_entry) /* TGT */; + + /* Clean up branch stack */ + memset(bstack, 0x0, sz); + + if (!(speq->flags & PERF_IP_FLAG_BRANCH)) + return; + + bstack->entries[0].from =3D record->from_ip; + bstack->entries[0].to =3D record->to_ip; + + bs_flags =3D &bstack->entries[0].flags; + bs_flags->value =3D 0; + + if (record->op & ARM_SPE_OP_BR_CR_BL) { + if (record->op & ARM_SPE_OP_BR_COND) + bs_flags->type |=3D PERF_BR_COND_CALL; + else + bs_flags->type |=3D PERF_BR_CALL; + /* + * Indirect branch instruction without link (e.g. BR), + * take this case as function return. + */ + } else if (record->op & ARM_SPE_OP_BR_CR_RET || + record->op & ARM_SPE_OP_BR_INDIRECT) { + if (record->op & ARM_SPE_OP_BR_COND) + bs_flags->type |=3D PERF_BR_COND_RET; + else + bs_flags->type |=3D PERF_BR_RET; + } else if (record->op & ARM_SPE_OP_BR_CR_NON_BL_RET) { + if (record->op & ARM_SPE_OP_BR_COND) + bs_flags->type |=3D PERF_BR_COND; + else + bs_flags->type |=3D PERF_BR_UNCOND; + } else { + if (record->op & ARM_SPE_OP_BR_COND) + bs_flags->type |=3D PERF_BR_COND; + else + bs_flags->type |=3D PERF_BR_UNKNOWN; + } + + if (record->type & ARM_SPE_BRANCH_MISS) { + bs_flags->mispred =3D 1; + bs_flags->predicted =3D 0; + } else { + bs_flags->mispred =3D 0; + bs_flags->predicted =3D 1; + } + + if (record->type & ARM_SPE_BRANCH_NOT_TAKEN) + bs_flags->not_taken =3D 1; + + if (record->type & ARM_SPE_IN_TXN) + bs_flags->in_tx =3D 1; + + bs_flags->cycles =3D min(record->latency, 0xFFFFU); + + bstack->nr =3D 1; + bstack->hw_idx =3D -1ULL; +} + static int arm_spe__inject_event(union perf_event *event, struct perf_samp= le *sample, u64 type) { event->header.size =3D perf_event__sample_event_size(sample, type, 0); @@ -416,6 +495,7 @@ static int arm_spe__synth_branch_sample(struct arm_spe_= queue *speq, sample.addr =3D record->to_ip; sample.weight =3D record->latency; sample.flags =3D speq->flags; + sample.branch_stack =3D speq->last_branch; =20 ret =3D arm_spe_deliver_synth_event(spe, speq, event, &sample); perf_sample__exit(&sample); @@ -450,6 +530,7 @@ static int arm_spe__synth_instruction_sample(struct arm= _spe_queue *speq, sample.period =3D spe->instructions_sample_period; sample.weight =3D record->latency; sample.flags =3D speq->flags; + sample.branch_stack =3D speq->last_branch; =20 ret =3D arm_spe_deliver_synth_event(spe, speq, event, &sample); perf_sample__exit(&sample); @@ -787,6 +868,10 @@ static int arm_spe_sample(struct arm_spe_queue *speq) } } =20 + if (spe->synth_opts.last_branch && + (spe->sample_branch || spe->sample_instructions)) + arm_spe__prep_branch_stack(speq); + if (spe->sample_branch && (record->op & ARM_SPE_OP_BRANCH_ERET)) { err =3D arm_spe__synth_branch_sample(speq, spe->branch_id); if (err) @@ -1278,6 +1363,7 @@ static void arm_spe_free_queue(void *priv) thread__zput(speq->thread); arm_spe_decoder_free(speq->decoder); zfree(&speq->event_buf); + zfree(&speq->last_branch); free(speq); } =20 @@ -1497,6 +1583,19 @@ arm_spe_synth_events(struct arm_spe *spe, struct per= f_session *session) id +=3D 1; } =20 + if (spe->synth_opts.last_branch) { + if (spe->synth_opts.last_branch_sz > 1) + pr_debug("Arm SPE supports only one bstack entry (TGT).\n"); + + attr.sample_type |=3D PERF_SAMPLE_BRANCH_STACK; + /* + * We don't use the hardware index, but the sample generation + * code uses the new format branch_stack with this field, + * so the event attributes must indicate that it's present. + */ + attr.branch_sample_type |=3D PERF_SAMPLE_BRANCH_HW_INDEX; + } + if (spe->synth_opts.branches) { spe->sample_branch =3D true; =20 --=20 2.34.1 From nobody Fri Dec 19 09:12:13 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 858A623ED70; Mon, 17 Feb 2025 19:59:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739822392; cv=none; b=Q7vvoTfLTeyUI/UTJyWJ5O8VtiKtwem6GMpXZPzdZ9sNIzv7cC1/PlbjZtN+NfFZ7FV030/axK905iwGdoVCQ+MBr/u7CFFtTsI5XGQgm67cfUmqolcSnNBY9W8ntOwI384dGdfWKK+Azxg30mk+7OcyrSCpMmDW/WYSKdZglIQ= ARC-Message-Signature: i=1; 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Mon, 17 Feb 2025 11:59:47 -0800 (PST) From: Leo Yan To: Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , James Clark , Mike Leach , Mark Rutland , Alexander Shishkin , Jiri Olsa , Adrian Hunter , "Liang, Kan" , Will Deacon , Graham Woodward , Paschalis.Mpeis@arm.com, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Leo Yan Subject: [PATCH v3 12/12] perf arm-spe: Support previous branch target (PBT) address Date: Mon, 17 Feb 2025 19:59:08 +0000 Message-Id: <20250217195908.176207-13-leo.yan@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250217195908.176207-1-leo.yan@arm.com> References: <20250217195908.176207-1-leo.yan@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When FEAT_SPE_PBT is implemented, the previous branch target address (named as PBT) before the sampled operation, will be recorded. This commit first introduces a 'prev_br_tgt' field in the record for saving the PBT address in the decoder. If the current operation is a branch instruction, by combining with PBT, it can create a chain with two consecutive branches. As the branch stack stores branches in descending order, meaning a newer branch is stored in a lower entry in the stack. Arm SPE stores the latest branch in the first entry of branch stack, and the previous branch coming from PBT is stored into the second entry. Otherwise, if current operation is not a branch, the last branch will be saved for PBT only. PBT lacks associated information such as branch source address, branch type, and events. The branch entry fills zeros for the corresponding fields and only set its target address. After: perf script -f --itrace=3Dbl -F flags,addr,brstack jcc ffff800080187914 0xffff8000801878fc/0xffff800080187= 914/P/-/-/1/COND/- 0x0/0xffff8000801878f8/-/-/-/0//- jcc ffff8000802d12d8 0xffff8000802d12f8/0xffff8000802d1= 2d8/P/-/-/1/COND/- 0x0/0xffff8000802d12ec/-/-/-/0//- jcc ffff8000813fe200 0xffff8000813fe20c/0xffff8000813fe= 200/P/-/-/1/COND/- 0x0/0xffff8000813fe200/-/-/-/0//- jcc ffff8000813fe200 0xffff8000813fe20c/0xffff8000813fe= 200/P/-/-/1/COND/- 0x0/0xffff8000813fe200/-/-/-/0//- jmp ffff800081410980 0xffff800081419108/0xffff800081410= 980/P/-/-/1//- 0x0/0xffff800081419104/-/-/-/0//- return ffff80008036e064 0xffff80008141ba84/0xffff80008036e= 064/P/-/-/1/RET/- 0x0/0xffff80008141ba60/-/-/-/0//- jcc ffff8000803d54f0 0xffff8000803d54e8/0xffff8000803d5= 4f0/P/-/-/1/COND/- 0x0/0xffff8000803d54e0/-/-/-/0//- jmp ffff80008015e468 0xffff8000803d46dc/0xffff80008015e= 468/P/-/-/1//- 0x0/0xffff8000803d46c8/-/-/-/0//- jmp ffff8000806e2d50 0xffff80008040f710/0xffff8000806e2= d50/P/-/-/1//- 0x0/0xffff80008040f6e8/-/-/-/0//- jcc ffff800080721704 0xffff8000807216b4/0xffff800080721= 704/P/-/-/1/COND/- 0x0/0xffff8000807216ac/-/-/-/0//- Reviewed-by: Ian Rogers Reviewed-by: James Clark Signed-off-by: Leo Yan --- .../util/arm-spe-decoder/arm-spe-decoder.c | 5 +- .../util/arm-spe-decoder/arm-spe-decoder.h | 1 + tools/perf/util/arm-spe.c | 114 ++++++++++-------- 3 files changed, 70 insertions(+), 50 deletions(-) diff --git a/tools/perf/util/arm-spe-decoder/arm-spe-decoder.c b/tools/perf= /util/arm-spe-decoder/arm-spe-decoder.c index 52bd0a4ea96d..688fe6d75244 100644 --- a/tools/perf/util/arm-spe-decoder/arm-spe-decoder.c +++ b/tools/perf/util/arm-spe-decoder/arm-spe-decoder.c @@ -28,7 +28,8 @@ static u64 arm_spe_calc_ip(int index, u64 payload) =20 /* Instruction virtual address or Branch target address */ if (index =3D=3D SPE_ADDR_PKT_HDR_INDEX_INS || - index =3D=3D SPE_ADDR_PKT_HDR_INDEX_BRANCH) { + index =3D=3D SPE_ADDR_PKT_HDR_INDEX_BRANCH || + index =3D=3D SPE_ADDR_PKT_HDR_INDEX_PREV_BRANCH) { ns =3D SPE_ADDR_PKT_GET_NS(payload); el =3D SPE_ADDR_PKT_GET_EL(payload); =20 @@ -181,6 +182,8 @@ static int arm_spe_read_record(struct arm_spe_decoder *= decoder) decoder->record.virt_addr =3D ip; else if (idx =3D=3D SPE_ADDR_PKT_HDR_INDEX_DATA_PHYS) decoder->record.phys_addr =3D ip; + else if (idx =3D=3D SPE_ADDR_PKT_HDR_INDEX_PREV_BRANCH) + decoder->record.prev_br_tgt =3D ip; break; case ARM_SPE_COUNTER: if (idx =3D=3D SPE_CNT_PKT_HDR_INDEX_TOTAL_LAT) diff --git a/tools/perf/util/arm-spe-decoder/arm-spe-decoder.h b/tools/perf= /util/arm-spe-decoder/arm-spe-decoder.h index 85b688a97436..5d232188643b 100644 --- a/tools/perf/util/arm-spe-decoder/arm-spe-decoder.h +++ b/tools/perf/util/arm-spe-decoder/arm-spe-decoder.h @@ -89,6 +89,7 @@ struct arm_spe_record { u32 latency; u64 from_ip; u64 to_ip; + u64 prev_br_tgt; u64 timestamp; u64 virt_addr; u64 phys_addr; diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c index ed89b7dbc244..2a9775649cc2 100644 --- a/tools/perf/util/arm-spe.c +++ b/tools/perf/util/arm-spe.c @@ -237,8 +237,9 @@ static struct arm_spe_queue *arm_spe__alloc_queue(struc= t arm_spe *spe, if (spe->synth_opts.last_branch) { size_t sz =3D sizeof(struct branch_stack); =20 - /* Allocate one entry for TGT */ - sz +=3D sizeof(struct branch_entry); + /* Allocate up to two entries for PBT + TGT */ + sz +=3D sizeof(struct branch_entry) * + min(spe->synth_opts.last_branch_sz, 2U); speq->last_branch =3D zalloc(sz); if (!speq->last_branch) goto out_free; @@ -362,68 +363,83 @@ static void arm_spe_prep_sample(struct arm_spe *spe, =20 static void arm_spe__prep_branch_stack(struct arm_spe_queue *speq) { + struct arm_spe *spe =3D speq->spe; struct arm_spe_record *record =3D &speq->decoder->record; struct branch_stack *bstack =3D speq->last_branch; struct branch_flags *bs_flags; + unsigned int last_branch_sz =3D spe->synth_opts.last_branch_sz; + bool have_tgt =3D !!(speq->flags & PERF_IP_FLAG_BRANCH); + bool have_pbt =3D last_branch_sz >=3D (have_tgt + 1U) && record->prev_br_= tgt; size_t sz =3D sizeof(struct branch_stack) + - sizeof(struct branch_entry) /* TGT */; + sizeof(struct branch_entry) * min(last_branch_sz, 2U) /* PBT + TGT *= /; + int i =3D 0; =20 /* Clean up branch stack */ memset(bstack, 0x0, sz); =20 - if (!(speq->flags & PERF_IP_FLAG_BRANCH)) + if (!have_tgt && !have_pbt) return; =20 - bstack->entries[0].from =3D record->from_ip; - bstack->entries[0].to =3D record->to_ip; + if (have_tgt) { + bstack->entries[i].from =3D record->from_ip; + bstack->entries[i].to =3D record->to_ip; =20 - bs_flags =3D &bstack->entries[0].flags; - bs_flags->value =3D 0; + bs_flags =3D &bstack->entries[i].flags; + bs_flags->value =3D 0; =20 - if (record->op & ARM_SPE_OP_BR_CR_BL) { - if (record->op & ARM_SPE_OP_BR_COND) - bs_flags->type |=3D PERF_BR_COND_CALL; - else - bs_flags->type |=3D PERF_BR_CALL; - /* - * Indirect branch instruction without link (e.g. BR), - * take this case as function return. - */ - } else if (record->op & ARM_SPE_OP_BR_CR_RET || - record->op & ARM_SPE_OP_BR_INDIRECT) { - if (record->op & ARM_SPE_OP_BR_COND) - bs_flags->type |=3D PERF_BR_COND_RET; - else - bs_flags->type |=3D PERF_BR_RET; - } else if (record->op & ARM_SPE_OP_BR_CR_NON_BL_RET) { - if (record->op & ARM_SPE_OP_BR_COND) - bs_flags->type |=3D PERF_BR_COND; - else - bs_flags->type |=3D PERF_BR_UNCOND; - } else { - if (record->op & ARM_SPE_OP_BR_COND) - bs_flags->type |=3D PERF_BR_COND; - else - bs_flags->type |=3D PERF_BR_UNKNOWN; - } + if (record->op & ARM_SPE_OP_BR_CR_BL) { + if (record->op & ARM_SPE_OP_BR_COND) + bs_flags->type |=3D PERF_BR_COND_CALL; + else + bs_flags->type |=3D PERF_BR_CALL; + /* + * Indirect branch instruction without link (e.g. BR), + * take this case as function return. + */ + } else if (record->op & ARM_SPE_OP_BR_CR_RET || + record->op & ARM_SPE_OP_BR_INDIRECT) { + if (record->op & ARM_SPE_OP_BR_COND) + bs_flags->type |=3D PERF_BR_COND_RET; + else + bs_flags->type |=3D PERF_BR_RET; + } else if (record->op & ARM_SPE_OP_BR_CR_NON_BL_RET) { + if (record->op & ARM_SPE_OP_BR_COND) + bs_flags->type |=3D PERF_BR_COND; + else + bs_flags->type |=3D PERF_BR_UNCOND; + } else { + if (record->op & ARM_SPE_OP_BR_COND) + bs_flags->type |=3D PERF_BR_COND; + else + bs_flags->type |=3D PERF_BR_UNKNOWN; + } =20 - if (record->type & ARM_SPE_BRANCH_MISS) { - bs_flags->mispred =3D 1; - bs_flags->predicted =3D 0; - } else { - bs_flags->mispred =3D 0; - bs_flags->predicted =3D 1; - } + if (record->type & ARM_SPE_BRANCH_MISS) { + bs_flags->mispred =3D 1; + bs_flags->predicted =3D 0; + } else { + bs_flags->mispred =3D 0; + bs_flags->predicted =3D 1; + } + + if (record->type & ARM_SPE_BRANCH_NOT_TAKEN) + bs_flags->not_taken =3D 1; =20 - if (record->type & ARM_SPE_BRANCH_NOT_TAKEN) - bs_flags->not_taken =3D 1; + if (record->type & ARM_SPE_IN_TXN) + bs_flags->in_tx =3D 1; =20 - if (record->type & ARM_SPE_IN_TXN) - bs_flags->in_tx =3D 1; + bs_flags->cycles =3D min(record->latency, 0xFFFFU); + i++; + } =20 - bs_flags->cycles =3D min(record->latency, 0xFFFFU); + if (have_pbt) { + bs_flags =3D &bstack->entries[i].flags; + bs_flags->type |=3D PERF_BR_UNKNOWN; + bstack->entries[i].to =3D record->prev_br_tgt; + i++; + } =20 - bstack->nr =3D 1; + bstack->nr =3D i; bstack->hw_idx =3D -1ULL; } =20 @@ -1584,8 +1600,8 @@ arm_spe_synth_events(struct arm_spe *spe, struct perf= _session *session) } =20 if (spe->synth_opts.last_branch) { - if (spe->synth_opts.last_branch_sz > 1) - pr_debug("Arm SPE supports only one bstack entry (TGT).\n"); + if (spe->synth_opts.last_branch_sz > 2) + pr_debug("Arm SPE supports only two bstack entries (PBT+TGT).\n"); =20 attr.sample_type |=3D PERF_SAMPLE_BRANCH_STACK; /* --=20 2.34.1