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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next v3] net: ethernet: mediatek: add EEE support Date: Mon, 17 Feb 2025 11:39:53 +0800 Message-ID: <20250217033954.3698772-1-dqfext@gmail.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add EEE support to MediaTek SoC Ethernet. The register fields are similar to the ones in MT7531, except that the LPI threshold is in milliseconds. Signed-off-by: Qingfang Deng --- v3: use phylink managed EEE drivers/net/ethernet/mediatek/mtk_eth_soc.c | 65 +++++++++++++++++++++ drivers/net/ethernet/mediatek/mtk_eth_soc.h | 11 ++++ 2 files changed, 76 insertions(+) diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethe= rnet/mediatek/mtk_eth_soc.c index 0ad965ced5ef..985010a7b277 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c @@ -815,12 +815,58 @@ static void mtk_mac_link_up(struct phylink_config *co= nfig, mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); } =20 +static void mtk_mac_disable_tx_lpi(struct phylink_config *config) +{ + struct mtk_mac *mac =3D container_of(config, struct mtk_mac, + phylink_config); + struct mtk_eth *eth =3D mac->hw; + + mtk_m32(eth, MAC_MCR_EEE100M | MAC_MCR_EEE1G, 0, MTK_MAC_MCR(mac->id)); +} + +static int mtk_mac_enable_tx_lpi(struct phylink_config *config, u32 timer, + bool tx_clk_stop) +{ + struct mtk_mac *mac =3D container_of(config, struct mtk_mac, + phylink_config); + struct mtk_eth *eth =3D mac->hw; + u32 val; + + /* Tx idle timer in ms */ + timer =3D DIV_ROUND_UP(timer, 1000); + + /* If the timer is zero, then set LPI_MODE, which allows the + * system to enter LPI mode immediately rather than waiting for + * the LPI threshold. + */ + if (!timer) + val =3D MAC_EEE_LPI_MODE; + else if (FIELD_FIT(MAC_EEE_LPI_TXIDLE_THD, timer)) + val =3D FIELD_PREP(MAC_EEE_LPI_TXIDLE_THD, timer); + else + val =3D MAC_EEE_LPI_TXIDLE_THD; + + if (tx_clk_stop) + val |=3D MAC_EEE_CKG_TXIDLE; + + /* PHY Wake-up time, this field does not have a reset value, so use the + * reset value from MT7531 (36us for 100M and 17us for 1000M). + */ + val |=3D FIELD_PREP(MAC_EEE_WAKEUP_TIME_1000, 17) | + FIELD_PREP(MAC_EEE_WAKEUP_TIME_100, 36); + + mtk_w32(eth, val, MTK_MAC_EEECR(mac->id)); + mtk_m32(eth, 0, MAC_MCR_EEE100M | MAC_MCR_EEE1G, MTK_MAC_MCR(mac->id)); +} + static const struct phylink_mac_ops mtk_phylink_ops =3D { .mac_select_pcs =3D mtk_mac_select_pcs, .mac_config =3D mtk_mac_config, .mac_finish =3D mtk_mac_finish, .mac_link_down =3D mtk_mac_link_down, .mac_link_up =3D mtk_mac_link_up, + .mac_disable_tx_lpi =3D mtk_mac_disable_tx_lpi, + .mac_enable_tx_lpi =3D mtk_mac_enable_tx_lpi, }; =20 static int mtk_mdio_init(struct mtk_eth *eth) @@ -4469,6 +4515,20 @@ static int mtk_set_pauseparam(struct net_device *dev= , struct ethtool_pauseparam return phylink_ethtool_set_pauseparam(mac->phylink, pause); } =20 +static int mtk_get_eee(struct net_device *dev, struct ethtool_keee *eee) +{ + struct mtk_mac *mac =3D netdev_priv(dev); + + return phylink_ethtool_get_eee(mac->phylink, eee); +} + +static int mtk_set_eee(struct net_device *dev, struct ethtool_keee *eee) +{ + struct mtk_mac *mac =3D netdev_priv(dev); + + return phylink_ethtool_set_eee(mac->phylink, eee); +} + static u16 mtk_select_queue(struct net_device *dev, struct sk_buff *skb, struct net_device *sb_dev) { @@ -4501,6 +4561,8 @@ static const struct ethtool_ops mtk_ethtool_ops =3D { .set_pauseparam =3D mtk_set_pauseparam, .get_rxnfc =3D mtk_get_rxnfc, .set_rxnfc =3D mtk_set_rxnfc, + .get_eee =3D mtk_get_eee, + .set_eee =3D mtk_set_eee, }; =20 static const struct net_device_ops mtk_netdev_ops =3D { @@ -4610,6 +4672,9 @@ static int mtk_add_mac(struct mtk_eth *eth, struct de= vice_node *np) mac->phylink_config.type =3D PHYLINK_NETDEV; mac->phylink_config.mac_capabilities =3D MAC_ASYM_PAUSE | MAC_SYM_PAUSE | MAC_10 | MAC_100 | MAC_1000 | MAC_2500FD; + mac->phylink_config.lpi_capabilities =3D MAC_100FD | MAC_1000FD | + MAC_2500FD; + mac->phylink_config.lpi_timer_default =3D 1000; =20 /* MT7623 gmac0 is now missing its speed-specific PLL configuration * in its .mac_config method (since state->speed is not valid there. diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethe= rnet/mediatek/mtk_eth_soc.h index 0d5225f1d3ee..90a377ab4359 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h @@ -453,6 +453,8 @@ #define MAC_MCR_RX_FIFO_CLR_DIS BIT(12) #define MAC_MCR_BACKOFF_EN BIT(9) #define MAC_MCR_BACKPR_EN BIT(8) +#define MAC_MCR_EEE1G BIT(7) +#define MAC_MCR_EEE100M BIT(6) #define MAC_MCR_FORCE_RX_FC BIT(5) #define MAC_MCR_FORCE_TX_FC BIT(4) #define MAC_MCR_SPEED_1000 BIT(3) @@ -461,6 +463,15 @@ #define MAC_MCR_FORCE_LINK BIT(0) #define MAC_MCR_FORCE_LINK_DOWN (MAC_MCR_FORCE_MODE) =20 +/* Mac EEE control registers */ +#define MTK_MAC_EEECR(x) (0x10104 + (x * 0x100)) +#define MAC_EEE_WAKEUP_TIME_1000 GENMASK(31, 24) +#define MAC_EEE_WAKEUP_TIME_100 GENMASK(23, 16) +#define MAC_EEE_LPI_TXIDLE_THD GENMASK(15, 8) +#define MAC_EEE_CKG_TXIDLE BIT(3) +#define MAC_EEE_CKG_RXLPI BIT(2) +#define MAC_EEE_LPI_MODE BIT(0) + /* Mac status registers */ #define MTK_MAC_MSR(x) (0x10108 + (x * 0x100)) #define MAC_MSR_EEE1G BIT(7) --=20 2.43.0