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Mon, 17 Feb 2025 06:18:10 -0800 (PST) From: Jun Nie Date: Mon, 17 Feb 2025 22:16:02 +0800 Subject: [PATCH v6 13/15] drm/msm/dpu: support SSPP assignment for quad-pipe case Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250217-sm8650-v6-14-hmd-deckard-mdss-quad-upstream-oldbootwrapper-36-prep-v6-13-c11402574367@linaro.org> References: <20250217-sm8650-v6-14-hmd-deckard-mdss-quad-upstream-oldbootwrapper-36-prep-v6-0-c11402574367@linaro.org> In-Reply-To: <20250217-sm8650-v6-14-hmd-deckard-mdss-quad-upstream-oldbootwrapper-36-prep-v6-0-c11402574367@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1739801787; l=4059; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=7p8Cf2cc/bnE8b/fucvAxqQfmQCibLQPXtQ8uTs5zao=; b=gfPi485oSXgo49FYw33li21uSnP9+HXe8ePAytCi/gAzb22q722yTuHv6ToMd//mLSrcS+Lyl Al8Rn5R+5uNCWF1U7Y/oDbn9bGmG4jYjFeQbUvvLcynFv//T46ltJ+e X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= Currently, SSPPs are assigned to a maximum of two pipes. However, quad-pipe usage scenarios require four pipes and involve configuring two stages. In quad-pipe case, the first two pipes share a set of mixer configurations and enable multi-rect mode when certain conditions are met. The same applies to the subsequent two pipes. Assign SSPPs to the pipes in each stage using a unified method and to loop the stages accordingly. Signed-off-by: Jun Nie Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 63 +++++++++++++++++++--------= ---- 1 file changed, 39 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/ms= m/disp/dpu1/dpu_plane.c index d67f2ad20b4754ca4bcb759a65a39628b7236b0f..b87da2bd20861370e7b3b1fa60a= 689a145c2fab7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -1115,8 +1115,9 @@ static int dpu_plane_virtual_assign_resources(struct = drm_crtc *crtc, struct dpu_sw_pipe *r_pipe; struct dpu_sw_pipe_cfg *pipe_cfg; struct dpu_sw_pipe_cfg *r_pipe_cfg; + struct dpu_plane *pdpu =3D to_dpu_plane(plane); const struct msm_format *fmt; - int i; + int i, num_lm, stage_id, num_stages; =20 if (plane_state->crtc) crtc_state =3D drm_atomic_get_new_crtc_state(state, @@ -1124,11 +1125,6 @@ static int dpu_plane_virtual_assign_resources(struct= drm_crtc *crtc, =20 pstate =3D to_dpu_plane_state(plane_state); =20 - pipe =3D &pstate->pipe[0]; - r_pipe =3D &pstate->pipe[1]; - pipe_cfg =3D &pstate->pipe_cfg[0]; - r_pipe_cfg =3D &pstate->pipe_cfg[1]; - for (i =3D 0; i < PIPES_PER_PLANE; i++) pstate->pipe[i].sspp =3D NULL; =20 @@ -1142,24 +1138,43 @@ static int dpu_plane_virtual_assign_resources(struc= t drm_crtc *crtc, =20 reqs.rot90 =3D drm_rotation_90_or_270(plane_state->rotation); =20 - pipe->sspp =3D dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, &req= s); - if (!pipe->sspp) - return -ENODEV; - - if (!dpu_plane_try_multirect_parallel(pipe, pipe_cfg, r_pipe, r_pipe_cfg, - pipe->sspp, - msm_framebuffer_format(plane_state->fb), - dpu_kms->catalog->caps->max_linewidth)) { - /* multirect is not possible, use two SSPP blocks */ - r_pipe->sspp =3D dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, &= reqs); - if (!r_pipe->sspp) - return -ENODEV; - - pipe->multirect_index =3D DPU_SSPP_RECT_SOLO; - pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_NONE; - - r_pipe->multirect_index =3D DPU_SSPP_RECT_SOLO; - r_pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_NONE; + num_lm =3D dpu_crtc_get_num_lm(crtc_state); + num_stages =3D (num_lm + 1) / 2; + for (stage_id =3D 0; stage_id < num_stages; stage_id++) { + for (i =3D stage_id * PIPES_PER_STAGE; i < (stage_id + 1) * PIPES_PER_ST= AGE; i++) { + pipe =3D &pstate->pipe[i]; + pipe_cfg =3D &pstate->pipe_cfg[i]; + + if (drm_rect_width(&pipe_cfg->src_rect) =3D=3D 0) + break; + + pipe->sspp =3D dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, &r= eqs); + if (!pipe->sspp) + return -ENODEV; + + r_pipe =3D &pstate->pipe[i + 1]; + r_pipe_cfg =3D &pstate->pipe_cfg[i + 1]; + + /* + * If current pipe is the first pipe in pipe pair, check + * multi-rect opportunity for the 2nd pipe in the pair. + * SSPP multi-rect mode cross mixer pairs is not supported. + */ + if ((i % PIPES_PER_STAGE =3D=3D 0) && + drm_rect_width(&r_pipe_cfg->src_rect) !=3D 0 && + dpu_plane_try_multirect_parallel(pipe, pipe_cfg, r_pipe, r_pipe_cfg, + pipe->sspp, + msm_framebuffer_format(plane_state->fb), + dpu_kms->catalog->caps->max_linewidth)) { + i++; + } else { + /* multirect is not possible, use two SSPP blocks */ + pipe->multirect_index =3D DPU_SSPP_RECT_SOLO; + pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_NONE; + DPU_DEBUG_PLANE(pdpu, "allocating sspp_%d for pipe %d.\n", + pipe->sspp->idx - SSPP_NONE, i); + } + } } =20 return dpu_plane_atomic_check_sspp(plane, state, crtc_state); --=20 2.34.1